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2022-02-21MAINTAINERS: Add Akihiko Odaki to macOS-relatedsAkihiko Odaki1-0/+2
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220213021215.1974-1-akihiko.odaki@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21include: Move hardware version declarations to new qemu/hw-version.hPeter Maydell11-16/+36
The "hardware version" machinery (qemu_set_hw_version(), qemu_hw_version(), and the QEMU_HW_VERSION define) is used by fewer than 10 files. Move it out from osdep.h into a new qemu/hw-version.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-6-peter.maydell@linaro.org
2022-02-21include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.hPeter Maydell9-5/+28
The qemu_icache_linesize, qemu_icache_linesize_log, qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not used in many files. Move them out of osdep.h to a new qemu/cacheinfo.h, and document them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-5-peter.maydell@linaro.org
2022-02-21include: Move QEMU_MAP_* constants to mmap-alloc.hPeter Maydell2-25/+23
The QEMU_MAP_* constants are used only as arguments to the qemu_ram_mmap() function. Move them to mmap-alloc.h, where that function's prototype is defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-4-peter.maydell@linaro.org
2022-02-21include: Move qemu_mprotect_*() to new qemu/mprotect.hPeter Maydell4-4/+16
The qemu_mprotect_*() family of functions are used in very few files; move them from osdep.h to a new qemu/mprotect.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-3-peter.maydell@linaro.org
2022-02-21include: Move qemu_madvise() and related #defines to new qemu/madvise.hPeter Maydell12-82/+105
The function qemu_madvise() and the QEMU_MADV_* constants associated with it are used in only 10 files. Move them out of osdep.h to a new qemu/madvise.h header that is included where it is needed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-2-peter.maydell@linaro.org
2022-02-21hw/arm/armv7m: Handle disconnected clock inputsPeter Maydell1-4/+22
In the armv7m object, handle clock inputs that aren't connected. This is always an error for 'cpuclk'. For 'refclk' it is OK for this to be disconnected, but we need to handle it by not trying to connect a sourceless-clock to the systick device. This fixes a bug where on the mps2-an521 and similar boards (which do not have a refclk) the systick device incorrectly reset with SYST_CSR.CLKSOURCE 0 ("use refclk") rather than 1 ("use CPU clock"). Cc: qemu-stable@nongnu.org Reported-by: Richard Petri <git@rpls.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208171643.3486277-1-peter.maydell@linaro.org
2022-02-21Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c busPeter Maydell1-0/+10
For arm boards with an i2c bus which a user could reasonably want to plug arbitrary devices, add 'imply I2C_DEVICES' to the Kconfig stanza. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20220208155911.3408455-3-peter.maydell@linaro.org
2022-02-21Kconfig: Add I2C_DEVICES device groupPeter Maydell4-2/+18
Currently there is no way for a board model's Kconfig stanza to say "I have an i2c bus which the user can plug an i2c device into, build all the free-standing i2c devices". The Kconfig mechanism for this is the "device group". Add an I2C_DEVICES group along the same lines as the existing PCI_DEVICES. Simple free-standing i2c devices which a user might plausibly want to be able to plug in on the QEMU commandline should have default y if I2C_DEVICES and board models which have an i2c bus that is user-accessible should use imply I2C_DEVICES to cause those pluggable devices to be built. In this commit we mark only a fairly conservative set of i2c devices as belonging to the I2C_DEVICES group: the simple sensors and RTCs (not including PMBus devices or devices which need GPIO lines to be connected). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20220208155911.3408455-2-peter.maydell@linaro.org
2022-02-21target/arm: Support PAuth extension for hvfPeter Maydell1-4/+10
Currently we don't allow guests under hvf to use the PAuth extension, because we didn't have any special code to handle that, and therefore in arm_cpu_pauth_finalize() we will sanitize the ID_AA64ISAR1 value the guest sees to clear the PAuth related fields. Add support for this in the same way that KVM does it, by defaulting to "PAuth enabled" if the host CPU has it and allowing the user to disable it via '-cpu pauth=no' on the command line. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-7-peter.maydell@linaro.org
2022-02-21target/arm: Fix '-cpu max' for HVFPeter Maydell1-2/+3
Currently when using hvf we mishandle '-cpu max': we fall through to the TCG version of its initfn, which then sets a lot of feature bits that the real host CPU doesn't have. The hvf accelerator code then exposes these bogus ID register values to the guest because it doesn't check that the host really has the features. Make '-cpu host' be like '-cpu max' for hvf, as we do with kvm. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-6-peter.maydell@linaro.org
2022-02-21target/arm: Unindent unnecessary else-clausePeter Maydell1-160/+163
Now that the if() branch of the condition in aarch64_max_initfn() returns early, we don't need to keep the rest of the code in the function inside an else block. Remove the else, unindenting that code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-5-peter.maydell@linaro.org
2022-02-21target/arm: Make KVM -cpu max exactly like -cpu hostPeter Maydell1-6/+8
Currently for KVM the intention is that '-cpu max' and '-cpu host' are the same thing, but because we did this with two separate pieces of code they have got a little bit out of sync. Specifically, 'max' has a 'sve-max-vq' property, and 'host' does not. Bring the two together by having the initfn for 'max' actually call the initfn for 'host'. This will result in 'max' no longer exposing the 'sve-max-vq' property when using KVM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-4-peter.maydell@linaro.org
2022-02-21target/arm: Use aarch64_cpu_register() for 'host' CPU typePeter Maydell1-13/+4
Use the aarch64_cpu_register() machinery to register the 'host' CPU type. This doesn't gain us anything functionally, but it does mean that the code for initializing it looks more like that for the other CPU types, in that its initfn then doesn't need to call arm_cpu_post_init() (because aarch64_cpu_instance_init() does that for it). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-3-peter.maydell@linaro.org
2022-02-21target/arm: Move '-cpu host' code to cpu64.cPeter Maydell2-30/+30
Now that KVM has dropped AArch32 host support, the 'host' CPU type is always AArch64, and we can move it to cpu64.c. This move will allow us to share code between it and '-cpu max', which should behave the same as '-cpu host' when using KVM or HVF. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-2-peter.maydell@linaro.org
2022-02-21checkpatch: Ensure that TypeInfos are constBernhard Beschow1-0/+1
Now that all static TypeInfo instances are declared const, prevent that new non-const instances are created. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220117145805.173070-3-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21Mark remaining global TypeInfo instances as constBernhard Beschow39-42/+42
More than 1k of TypeInfo instances are already marked as const. Mark the remaining ones, too. This commit was created with: git grep -z -l 'static TypeInfo' -- '*.c' | \ xargs -0 sed -i 's/static TypeInfo/static const TypeInfo/' Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20220117145805.173070-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21hvf: arm: Handle unknown ID registers as RES0Alexander Graf1-0/+14
Recent Linux versions added support to read ID_AA64ISAR2_EL1. On M1, those reads trap into QEMU which handles them as faults. However, AArch64 ID registers should always read as RES0. Let's handle them accordingly. This fixes booting Linux 5.17 guests. Cc: qemu-stable@nongnu.org Reported-by: Ivan Babrou <ivan@cloudflare.com> Signed-off-by: Alexander Graf <agraf@csgraf.de> Message-id: 20220209124135.69183-2-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21hvf: arm: Use macros for sysreg shift/maskingAlexander Graf1-22/+47
We are parsing the syndrome field for sysregs in multiple places across the hvf code, but repeat shift/mask operations with hard coded constants every time. This is an error prone approach and makes it harder to reason about the correctness of these operations. Let's introduce macros that allow us to unify the constants used as well as create new helpers to extract fields from the sysreg value. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Cameron Esfahani <dirty@apple.com <mailto:dirty@apple.com>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220209124135.69183-1-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-20MAINTAINERS: Adding myself as a reviewer of some componentsAni Sinha1-0/+3
Added myself as a reviewer of vmgenid, unimplemented device and empty slot. Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220131122001.1476101-1-ani@anisinha.ca Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-20Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into ↵Peter Maydell22-1334/+2132
staging ppc-7.0 queue * target/ppc: SPR registration cleanups (Fabiano) * ppc: nested KVM HV for spapr virtual hypervisor (Nicholas) * spapr: nvdimm: Introduce spapr-nvdimm device (Shivaprasad) # gpg: Signature made Fri 18 Feb 2022 07:59:29 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-ppc-20220218: (39 commits) target/ppc: Move common SPR functions out of cpu_init target/ppc: cpu_init: Move check_pow and QOM macros to a header target/ppc: cpu_init: Move SPR registration macros to a header target/ppc: cpu_init: Expose some SPR registration helpers target/ppc: Rename spr_tcg.h to spr_common.h target/ppc: cpu_init: Remove register_usprg3_sprs target/ppc: cpu_init: Rename register_ne_601_sprs target/ppc: cpu_init: Reuse init_proc_745 for the 755 target/ppc: cpu_init: Reuse init_proc_604 for the 604e target/ppc: cpu_init: Reuse init_proc_603 for the e300 target/ppc: cpu_init: Move 604e SPR registration into a function target/ppc: cpu_init: Move e300 SPR registration into a function target/ppc: cpu_init: Move 755 L2 cache SPRs into a function target/ppc: cpu_init: Deduplicate 7xx SPR registration target/ppc: cpu_init: Deduplicate 745/755 SPR registration target/ppc: cpu_init: Deduplicate 604 SPR registration target/ppc: cpu_init: Deduplicate 603 SPR registration target/ppc: cpu_init: Deduplicate 440 SPR registration target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx target/ppc: cpu_init: Decouple G2 SPR registration from 755 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-19Merge remote-tracking branch ↵Peter Maydell34-132/+1123
'remotes/dgilbert-gitlab/tags/pull-virtiofs-20220217b' into staging V3: virtiofs pull 2022-02-17 Security label improvements from Vivek - includes a fix for building against new kernel headers [V3: checkpatch style fixes] [V2: Fix building on old Linux] Blocking flock disable from Sebastian SYNCFS support from Greg Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> # gpg: Signature made Thu 17 Feb 2022 17:24:25 GMT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert-gitlab/tags/pull-virtiofs-20220217b: virtiofsd: Add basic support for FUSE_SYNCFS request virtiofsd: Add an option to enable/disable security label virtiofsd: Create new file using O_TMPFILE and set security context virtiofsd: Create new file with security context virtiofsd: Add helpers to work with /proc/self/task/tid/attr/fscreate virtiofsd: Move core file creation code in separate function virtiofsd, fuse_lowlevel.c: Add capability to parse security context virtiofsd: Extend size of fuse_conn_info->capable and ->want fields virtiofsd: Parse extended "struct fuse_init_in" linux-headers: Update headers to v5.17-rc1 virtiofsd: Fix breakage due to fuse_init_in size change virtiofsd: Do not support blocking flock Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-19Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20220217' ↵Peter Maydell7-92/+96
into staging 9pfs: fixes and cleanup * Fifth patch fixes a 9pfs server crash that happened on some systems due to incorrect (system dependant) handling of struct dirent size. * Tests: Second patch fixes a test error that happened on some systems due mkdir() being called twice for creating the test directory for the 9p 'local' tests. * Tests: Third patch fixes a memory leak. * Tests: The remaining two patches are code cleanup. # gpg: Signature made Thu 17 Feb 2022 16:19:25 GMT # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * remotes/cschoenebeck/tags/pull-9p-20220217: 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread tests/9pfs: Use g_autofree and g_autoptr where possible tests/9pfs: Fix leak of local_test_path tests/9pfs: fix mkdir() being called twice tests/9pfs: use g_autofree where possible Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-18target/ppc: Move common SPR functions out of cpu_initFabiano Rosas3-400/+403
Let's leave cpu_init with just generic CPU initialization and QOM-related functions. The rest of the SPR registration functions will be moved in the following patches along with the code that uses them. These are only the commonly used ones. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-28-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move check_pow and QOM macros to a headerFabiano Rosas2-37/+39
These will need to be accessed from other files once we move the CPUs code to separate files. The check_pow_hid0 and check_pow_hid0_74xx are too specific to be moved to a header so I'll deal with them later when splitting this code between the multiple CPU families. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-27-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move SPR registration macros to a headerFabiano Rosas2-56/+65
Put the SPR registration macros in a header that is accessible outside of cpu_init.c. The following patches will move CPU-specific code to separate files and will need to access it. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-26-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Expose some SPR registration helpersFabiano Rosas2-7/+15
The following patches will move CPU-specific code into separate files, so expose the most used SPR registration functions: register_sdr1_sprs | 22 callers register_low_BATs | 20 callers register_non_embedded_sprs | 19 callers register_high_BATs | 10 callers register_thrm_sprs | 8 callers register_usprgh_sprs | 6 callers register_6xx_7xx_soft_tlb | only 3 callers, but it helps to keep the soft TLB code consistent. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: Rename spr_tcg.h to spr_common.hFabiano Rosas3-4/+4
Initial intent for the spr_tcg header was to expose the spr_read|write callbacks that are only used by TCG code. However, although these routines are TCG-specific, the KVM code needs access to env->sprs which creation is currently coupled to the callback registration. We are probably not going to decouple SPR creation and TCG callback registration any time soon, so let's rename the header to spr_common to accomodate the register_*_sprs functions that will be moved out of cpu_init.c in the following patches. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-24-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Remove register_usprg3_sprsFabiano Rosas1-10/+11
This function registers just one SPR and has only two callers, so open code it. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-23-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Rename register_ne_601_sprsFabiano Rosas1-21/+20
The important part of this function is that it applies to non-embedded CPUs, not that it also applies to the 601. We removed support for the 601 anyway, so rename this function. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-22-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Reuse init_proc_745 for the 755Fabiano Rosas1-17/+1
The init_proc_755 function is identical to the 745 one except for the 755-specific registers. I think it is worth it to make them share code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-21-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Reuse init_proc_604 for the 604eFabiano Rosas1-11/+1
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-20-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Reuse init_proc_603 for the e300Fabiano Rosas1-58/+46
init_proc_603 is defined after init_proc_e300, so I had to move some code around to make it work. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-19-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move 604e SPR registration into a functionFabiano Rosas1-19/+24
This is done to improve init_proc readability and to make subsequent patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-18-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move e300 SPR registration into a functionFabiano Rosas1-29/+35
This is done to improve init_proc readability and to make subsequent patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-17-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move 755 L2 cache SPRs into a functionFabiano Rosas1-9/+15
This is just to have 755-specific registers contained into a function, intead of leaving them open-coded in init_proc_755. It makes init_proc easier to read and keeps later patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-16-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 7xx SPR registrationFabiano Rosas1-57/+11
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-15-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 745/755 SPR registrationFabiano Rosas1-31/+19
The 745 and 755 can share the HID registration, so move it all into register_755_sprs, which applies for both CPUs. Also rename that function to register_745_sprs, since the 745 is the earliest of the two. This will help with separating 755-specific registers in a subsequent patch. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-14-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 604 SPR registrationFabiano Rosas1-10/+7
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-13-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 603 SPR registrationFabiano Rosas1-19/+9
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 440 SPR registrationFabiano Rosas1-74/+26
Move some of the 440 registers that are being repeated in the 440* CPUs to register_440_sprs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Decouple 74xx SPR registration from 7xxFabiano Rosas1-16/+91
We're considering these two to be from different CPU families, so duplicate some code to keep them separate. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Decouple G2 SPR registration from 755Fabiano Rosas1-5/+20
We're considering these two to be in different CPU families (6xx and 7xx), so keep their SPR registration separate. The code was copied into register_G2_sprs and the common function was renamed to apply only to the 755. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move G2 SPRs into register_G2_sprsFabiano Rosas1-19/+22
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move 405 SPRs into register_405_sprsFabiano Rosas1-11/+13
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Avoid nested SPR register functionsFabiano Rosas1-3/+3
Make sure that every register_*_sprs function only has calls to spr_register* to register individual SPRs. Do not allow nesting. This makes the code easier to follow and a look at init_proc_* should suffice to know what SPRs a CPU has. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move Timebase registration into the common functionFabiano Rosas1-80/+18
Now that the 601 was removed, all of our CPUs have a timebase, so that can be moved into the common function. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Group registration of generic SPRsFabiano Rosas1-26/+32
The top level init_proc calls register_generic_sprs but also registers some other SPRs outside of that function. Let's group everything into a single place. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Remove G2LE init codeFabiano Rosas1-41/+1
The G2LE CPU initialization code is the same as the G2. Use the latter for both. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Remove not implemented commentsFabiano Rosas1-329/+253
The /* XXX : not implemented */ comments all over cpu_init are confusing and ambiguous. Do they mean not implemented by QEMU, not implemented in a specific access mode? Not implemented by the CPU? Do they apply to just the register right after or to a whole block? Do they mean we have an action to take in the future to implement these? Are they only informative? Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
generated by cgit v1.1 at 2024-12-29 09:19:20 +0000