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2016-06-20trace: split out trace events for hw/intc/ directoryDaniel P. Berrange3-81/+124
Move all trace-events for files in the hw/intc/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-10-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for hw/char/ directoryDaniel P. Berrange3-48/+50
Move all trace-events for files in the hw/char/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-9-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for hw/block/ directoryDaniel P. Berrange3-16/+18
Move all trace-events for files in the hw/block/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-8-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for block/ directoryDaniel P. Berrange3-115/+117
Move all trace-events for files in the block/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-7-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for migration/ directoryDaniel P. Berrange3-208/+210
Move all trace-events for files in the migration/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-6-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for io/ directoryDaniel P. Berrange3-62/+64
Move all trace-events for files in the io/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-5-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for crypto/ directoryDaniel P. Berrange3-18/+20
Move all trace-events for files in the crypto/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-4-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: split out trace events for util/ directoryDaniel P. Berrange3-12/+14
Move all trace-events for files in the util/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-3-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: add build framework for merging trace-events filesDaniel P. Berrange7-33/+45
Switch make rules over to use trace-events-all as the master trace events input file. Add rule that will construct trace-events-all from $(trace-events-y). Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1466066426-16657-2-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20trace: [all] Add "guest_mem_before" eventLluís Vilanova6-0/+158
The event is described in "trace-events". Note that the "MO_AMASK" flag is not traced, since it does not seem to affect the visible semantics of instructions. [s/inline inline/inline/ to fix clang build. --Stefan] Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 146549350711.18437.726780393247474362.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova21-0/+25
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20Merge remote-tracking branch 'remotes/otubo/tags/pull-seccomp-20160620' into ↵Peter Maydell1-0/+3
staging seccomp branch queue # gpg: Signature made Mon 20 Jun 2016 10:06:59 BST # gpg: using RSA key 0xFD0CFF5B12F8BD2F # gpg: Good signature from "Eduardo Otubo (Software Engineer @ ProfitBricks) <eduardo.otubo@profitbricks.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 1C96 46B6 E1D1 C38A F2EC 3FDE FD0C FF5B 12F8 BD2F * remotes/otubo/tags/pull-seccomp-20160620: seccomp: Add support for ppc/ppc64 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-20hw/intc/arm_gicv3: Fix compilation with simple trace backendPeter Maydell2-0/+2
Fix missing includes of qemu/log.h, which broke compilation with the simple trace backend (the default backend pulls in log.h implicitly via trace.h). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Tested-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1466416634-9798-1-git-send-email-peter.maydell@linaro.org
2016-06-20seccomp: Add support for ppc/ppc64Michael Strosaker1-0/+3
Support for ppc/ppc64 is official in libseccomp 2.3.0, so modify the configuration script to allow qemuu to enable seccomp for those platforms. Signed-off-by: Michael Strosaker <strosake@linux.vnet.ibm.com>
2016-06-17Merge remote-tracking branch ↵Peter Maydell25-60/+4394
'remotes/pmaydell/tags/pull-target-arm-20160617' into staging target-arm queue: * GICv3 emulation # gpg: Signature made Fri 17 Jun 2016 15:24:28 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160617: (22 commits) ACPI: ARM: Present GIC version in MADT table hw/timer: Add value matching support to aspeed_timer target-arm/monitor.c: Advertise emulated GICv3 in capabilities target-arm/machine.c: Allow user to request GICv3 emulation hw/intc/arm_gicv3: Add IRQ handling CPU interface registers hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers hw/intc/arm_gicv3: Implement gicv3_cpuif_update() hw/intc/arm_gicv3: Implement GICv3 CPU interface registers hw/intc/arm_gicv3: Implement gicv3_set_irq() hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions hw/intc/arm_gicv3: Implement GICv3 redistributor registers hw/intc/arm_gicv3: Implement GICv3 distributor registers hw/intc/arm_gicv3: Implement functions to identify next pending irq hw/intc/arm_gicv3: ARM GICv3 device framework hw/intc/arm_gicv3: Add vmstate descriptors hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure hw/intc/arm_gicv3: Add state information target-arm: Add mp-affinity property for ARM CPU class target-arm: Provide hook to tell GICv3 about changes of security state target-arm: Define new arm_is_el3_or_mon() function ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17Merge remote-tracking branch 'remotes/ehabkost/tags/machine-pull-request' ↵Peter Maydell3-8/+10
into staging Machine queue, 2016-06-17 # gpg: Signature made Fri 17 Jun 2016 14:45:48 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-pull-request: vnc: Wrap vnc initialization code with CONFIG_VNC qdev: Use GList for global properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17ACPI: ARM: Present GIC version in MADT tableShannon Zhao2-1/+4
In ACPI 5.1 Errata, it adds GIC version in GIC distributor structure. This is useful for guest kernel to identify which version GIC hardware is. Update GIC distributor structure and present GIC version in MADT table. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1465960955-17388-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/timer: Add value matching support to aspeed_timerAndrew Jeffery2-39/+104
Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1465974248-20434-1-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17target-arm/monitor.c: Advertise emulated GICv3 in capabilitiesPeter Maydell1-2/+1
Now we have an emulated GICv3 we should advertise it via the capabilities in the monitor protocol. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-21-git-send-email-peter.maydell@linaro.org
2016-06-17target-arm/machine.c: Allow user to request GICv3 emulationPeter Maydell1-2/+1
Now we have an emulated GICv3, remove the restriction in gicv3_class_name() so that the user can request a GICv3 with -machine gic-version=3 even when not using KVM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-20-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Add IRQ handling CPU interface registersPeter Maydell3-0/+449
Add the CPU interface registers which deal with acknowledging and dismissing interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Implement CPU i/f SGI generation registersPeter Maydell4-0/+168
Implement the registers in the GICv3 CPU interface which generate new SGI interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-18-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Implement gicv3_cpuif_update()Peter Maydell3-5/+142
Implement the gicv3_cpuif_update() function which deals with correctly asserting IRQ and FIQ based on the current running priority of the CPU, the priority of the highest priority pending interrupt and the CPU's current exception level and security state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-17-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Implement GICv3 CPU interface registersPeter Maydell5-0/+666
Implement the CPU interface registers for the GICv3; these are CPU system registers, not MMIO registers. This commit implements all the registers which are simple accessors for GIC state, but not those which act as interfaces for acknowledging, dismissing or generating interrupts. (Those will be added in a later commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-16-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell5-1/+65
Implement the code which updates the GIC state when an interrupt input into the GIC is asserted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-15-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regionsPeter Maydell1-1/+14
Wire up the MMIO functions exposed by the distributor and the redistributor into MMIO regions exposed by the GICv3 device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-14-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Implement GICv3 redistributor registersShlomo Pongratz4-0/+512
Implement the redistributor registers of a GICv3. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-13-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled/rewritten: * use the new data structures * restructure register read/write to handle different width accesses natively, since almost all registers are 32-bit only, rather than implementing everything as byte accesses * implemented security extension support ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/intc/arm_gicv3: Implement GICv3 distributor registersShlomo Pongratz4-0/+869
Implement the distributor registers of a GICv3. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-12-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled/rewritten: * use the new bitmap data structures * restructure register read/write to handle different width accesses natively, since almost all registers are 32-bit only, rather than implementing everything as byte accesses * implemented security extension support ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/intc/arm_gicv3: Implement functions to identify next pending irqPeter Maydell4-0/+441
Implement the GICv3 logic to recalculate the highest priority pending interrupt for each CPU after some part of the GIC state has changed. We avoid unnecessary full recalculation where possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: ARM GICv3 device frameworkShlomo Pongratz4-0/+131
This patch includes the device class itself, some ID register value functions which will be needed by both distributor and redistributor, and some skeleton functions for handling interrupts coming in and going out, which will be filled in in a subsequent patch. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-10-git-send-email-peter.maydell@linaro.org [PMM: pulled this patch earlier in the sequence, and left some code out of it for a later patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
2016-06-17hw/intc/arm_gicv3: Add vmstate descriptorsPavel Fedin2-1/+57
Add state structure descriptors for the GICv3 state. We mark the KVM GICv3 device as having a migration blocker until the code to save and restore the state in the kernel is implemented. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-9-git-send-email-peter.maydell@linaro.org [PMM: Adjust to renamed struct fields; switched to using uint32_t array backed bitmaps; add migration blocker setting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structurePeter Maydell2-8/+4
Move the GICv3 parent_irq and parent_fiq pointers into the GICv3CPUState structure rather than giving them their own array. This will make it easy to assert the IRQ and FIQ lines for a particular CPU interface without having to know or calculate the CPU index for the GICv3CPUState we are working on. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-8-git-send-email-peter.maydell@linaro.org
2016-06-17hw/intc/arm_gicv3: Add state informationPavel Fedin3-5/+518
Add state information to GICv3 object structure and implement arm_gicv3_common_reset(). This commit includes accessor functions for the fields which are stored as bitmaps in uint32_t arrays. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-7-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled: * Add missing qom/cpu.h include * Remove legacy-only state fields (we can add them later if/when we add legacy emulation) * Use arrays of uint32_t to store the various distributor bitmaps, and provide accessor functions for the various set/test/etc operations * Add various missing register offset #defines * Accessor macros which combine distributor and redistributor behaviour removed * Fields in state structures renamed to match architectural register names * Corrected the reset value for GICR_IENABLER0 since we don't support legacy mode * Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in non-secure" so that we can fake up the firmware-mandated reconfiguration only when we need it ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
2016-06-17target-arm: Add mp-affinity property for ARM CPU classPavel Fedin1-0/+1
This allows to override default affinity IDs on a per-machine basis, and possibility to retrieve IDs will be used by vGICv3 live migration code. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-6-git-send-email-peter.maydell@linaro.org
2016-06-17target-arm: Provide hook to tell GICv3 about changes of security statePeter Maydell5-0/+57
The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be called on such changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-5-git-send-email-peter.maydell@linaro.org
2016-06-17target-arm: Define new arm_is_el3_or_mon() functionPeter Maydell1-2/+11
The GICv3 system registers need to know if the CPU is AArch64 in EL3 or AArch32 in Monitor mode. This happens to be the first part of the check for arm_is_secure(), so factor it out into a new arm_is_el3_or_mon() function that the GIC can also use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-4-git-send-email-peter.maydell@linaro.org
2016-06-17bitops.h: Implement half-shuffle and half-unshuffle opsPeter Maydell2-0/+180
A half-shuffle operation takes a word with zeros in the high half: 0000 0000 0000 0000 ABCD EFGH IJKL MNOP and spreads the bits out so they are in every other bit of the word: 0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P A half-unshuffle performs the reverse operation. Provide functions in bitops.h which implement these operations for 32-bit and 64-bit inputs, and add tests for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-3-git-send-email-peter.maydell@linaro.org
2016-06-17migration: Define VMSTATE_UINT64_2DARRAYPeter Maydell1-0/+6
Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we already have for other type sizes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-2-git-send-email-peter.maydell@linaro.org
2016-06-17nbd/client.c: Correct trace format stringPeter Maydell1-1/+1
The trace format string in nbd_send_request uses PRIu16 for request->type, but request->type is a uint32_t. This provokes compiler warnings on the OSX clang. Use PRIu32 instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1466167331-17063-1-git-send-email-peter.maydell@linaro.org
2016-06-17vnc: Wrap vnc initialization code with CONFIG_VNCChao Peng1-0/+2
commit f8c75b2486 (vnc: Initialization stubs) removed CONFIG_VNC in vl.c code. However qemu_find_opts("vnc") is NULL when vnc is configured out. Crash will happen in qemu_opts_foreach() before stub vnc_init_func() is called. This patch add it back. Cc: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-17qdev: Use GList for global propertiesEduardo Habkost2-8/+8
If the same GlobalProperty struct is registered twice, the list entry gets corrupted, making tqe_next points to itself, and qdev_prop_set_globals() gets stuck in a loop. The bug can be easily reproduced by running: $ qemu-system-x86_64 -rtc-td-hack -rtc-td-hack Change global_props to use GList instead of queue.h, making the code simpler and able to deal with properties being registered twice. Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-17Merge remote-tracking branch ↵Peter Maydell7-129/+191
'remotes/amit-migration/tags/migration-for-2.7-5' into staging Migration: - many compression/decompression fixes - trace improvements - static checker fix for detecting size mismatch in unused fields - fix VM save after snapshot # gpg: Signature made Fri 17 Jun 2016 13:59:44 BST # gpg: using RSA key 0xEB0B4DFC657EF670 # gpg: Good signature from "Amit Shah <amit@amitshah.net>" # gpg: aka "Amit Shah <amit@kernel.org>" # gpg: aka "Amit Shah <amitshah@gmx.net>" # Primary key fingerprint: 48CA 3722 5FE7 F4A8 B337 2735 1E9A 3B5F 8540 83B6 # Subkey fingerprint: CC63 D332 AB8F 4617 4529 6534 EB0B 4DFC 657E F670 * remotes/amit-migration/tags/migration-for-2.7-5: vmstate-static-checker: fix size mismatch detection in unused fields migration: code clean up migration: refine the decompression code migration: refine the compression code migration: protect the quit flag by lock migration: refine ram_save_compressed_page qemu-file: Fix qemu_put_compression_data flaw migration: remove useless code migration: Fix a potential issue migration: Fix multi-thread compression bug migration: fix inability to save VM after snapshot migration: Trace improvements migration: Don't use *_to_cpup() and cpu_to_*w() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17vmstate-static-checker: fix size mismatch detection in unused fieldsAmit Shah1-1/+1
If a field changed from something to unused, the checker wasn't flagging if the field size mismatched. This was noticed in: http://thread.gmane.org/gmane.comp.emulators.qemu/419802 where the 4->1 size change along with field name change to 'unused' wasn't being flagged. Fix this. Signed-off-by: Amit Shah <amit.shah@redhat.com> Message-Id: <d7ec03a9b2edfa0616764887a51ba8f64fdd3f68.1466165736.git.amit.shah@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17migration: code clean upLiang Li1-21/+15
Use 'QemuMutex comp_done_lock' and 'QemuCond comp_done_cond' instead of 'QemuMutex *comp_done_lock' and 'QemuCond comp_done_cond'. To keep consistent with 'QemuMutex decomp_done_lock' and 'QemuCond comp_done_cond'. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-10-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17migration: refine the decompression codeLiang Li1-25/+25
The current code for multi-thread decompression is not clear, especially in the aspect of using lock. Refine the code to make it clear. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-9-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17migration: refine the compression codeLiang Li1-44/+40
The current code for multi-thread compression is not clear, especially in the aspect of using lock. Refine the code to make it clear. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-8-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17migration: protect the quit flag by lockLiang Li1-16/+16
quit_comp_thread and quit_decomp_thread are accessed by several thread, it's better to protect them with locks. We use a per thread flag to replace the global one, and the new flag is protected by a lock. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-7-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17migration: refine ram_save_compressed_pageLiang Li1-14/+13
Use qemu_put_compression_data to do the compression directly instead of using do_compress_ram_page, avoid some data copy. very small improvement, at the same time, add code to check if the compression is successful. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-6-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17qemu-file: Fix qemu_put_compression_data flawLiang Li2-7/+34
Current qemu_put_compression_data can only work with no writable QEMUFile, and can't work with the writable QEMUFile. But it does not provide any measure to prevent users from using it with a writable QEMUFile. We should fix this flaw to make it works with writable QEMUFile. Signed-off-by: Liang Li <liang.z.li@intel.com> Suggested-by: Juan Quintela <quintela@redhat.com> Message-Id: <1462433579-13691-5-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-06-17migration: remove useless codeLiang Li1-1/+0
page_buffer is set twice repeatedly, remove the previous set. Signed-off-by: Liang Li <liang.z.li@intel.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <1462433579-13691-4-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
generated by cgit v1.1 at 2024-10-18 18:29:26 +0000