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2022-03-02target/ppc: implement vsrqMatheus Ferst2-10/+31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-22-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: implement vslqMatheus Ferst2-0/+41
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-21-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: move vs[lr][a][bhwd] to decodetreeMatheus Ferst3-26/+45
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-20-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: implement vgnbMatheus Ferst2-0/+140
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-19-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: implement vcntmb[bhwd]Matheus Ferst2-0/+40
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-18-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: implement vclrrbMatheus Ferst2-8/+25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-17-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: implement vclrlbMatheus Ferst2-0/+42
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-16-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: implement vstri[bh][lr]Matheus Ferst4-0/+72
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-15-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Implement Vector Compare QuadwordMatheus Ferst2-0/+51
Implement the following PowerISA v3.1 instructions: vcmpsq: Vector Compare Signed Quadword vcmpuq: Vector Compare Unsigned Quadword Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-14-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Implement Vector Compare Greater Than QuadwordMatheus Ferst2-0/+41
Implement the following PowerISA v3.1 instructions: vcmpgtsq: Vector Compare Greater Than Signed Quadword vcmpgtuq: Vector Compare Greater Than Unsigned Quadword Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-13-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Implement Vector Compare Equal QuadwordMatheus Ferst2-0/+37
Implement the following PowerISA v3.1 instructions: vcmpequq: Vector Compare Equal Quadword Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-12-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Move Vector Compare Not Equal or Zero to decodetreeMatheus Ferst5-52/+80
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-11-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetreeMatheus Ferst5-124/+88
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-10-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Implement vextsd2qLucas Coutinho2-0/+19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-9-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Move vexts[bhw]2[wd] to decodetreeLucas Coutinho5-30/+61
Move the following instructions to decodetree: vextsb2w: Vector Extend Sign Byte To Word vextsh2w: Vector Extend Sign Halfword To Word vextsb2d: Vector Extend Sign Byte To Doubleword vextsh2d: Vector Extend Sign Halfword To Doubleword vextsw2d: Vector Extend Sign Word To Doubleword Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-8-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Implement vmsumudm instructionVíctor Colombo2-0/+35
Based on [1] by Lijun Pan <ljp@linux.ibm.com>, which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-7-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Implement vmsumcud instructionVíctor Colombo2-0/+57
Based on [1] by Lijun Pan <ljp@linux.ibm.com>, which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: vmulh* instructions without helpersLucas Mateus Castro (alqotel)3-43/+87
Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to not use helpers. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225210936.1749575-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Moved vector multiply high and low to decodetreeLucas Mateus Castro (alqotel)5-18/+30
Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: moved vector even and odd multiplication to decodetreeLucas Mateus Castro (alqotel)6-52/+112
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub, vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw, muleuw and vmulouw from legacy to decodetree. Implemented the instructions vmulesd, vmulosd, vmuleud, vmuloud. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: Introduce TRANS*FLAGS macrosLuis Pires2-25/+31
New macros that add FLAGS and FLAGS2 checking were added for both TRANS and TRANS64. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> [ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E - Use the new macros in load/store vector insns ] Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: trigger PERFM EBBs from power8-pmu.cDaniel Henrique Barboza3-2/+54
This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are set, do_ebb() will attempt to trigger a PERFM EBB event. If the EBB facility is enabled in both FSCR and HFSCR we consider that the EBB is valid and set BESCR_PMEO. After that, if we're running in problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll queue a PPC_INTERRUPT_EBB. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: add PPC_INTERRUPT_EBB and EBB exceptionsDaniel Henrique Barboza3-1/+41
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur. ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External EBB exception. They are being added as POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB. PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that occurred and trigger the appropriate exception. Both exceptions are doing the same thing in this first implementation: clear BESCR_GE and enter the branch with env->nip retrieved from SPR_EBBHR. The checks being done by the interrupt code are msr_pr and BESCR_GE states. All other checks (EBB facility check, BESCR_PME bit, specific bits related to the event type) must be done beforehand. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: finalize pre-EBB PMU logicDaniel Henrique Barboza1-2/+34
There are still PMU exclusive bits to handle in fire_PMC_interrupt() before implementing the EBB support. Let's finalize it now to avoid dealing with PMU and EBB logic at the same time in the next patches. fire_PMC_interrupt() will fire an Performance Monitor alert depending on MMCR0_PMAE. If we are required to freeze the timers (MMCR0_FCECE) we'll also need to update summaries and delete the existing overflow timers. In all cases we're going to update the cycle counters. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02target/ppc: make power8-pmu.c CONFIG_TCG onlyDaniel Henrique Barboza4-13/+15
This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing meson.build accordingly will prevent problems --disable-tcg and --disable-linux-user later on. We're also changing the uses of !kvm_enabled() to tcg_enabled() to avoid adding "defined(CONFIG_TCG)" ifdefs, since tcg_enabled() will be defaulted to false with --disable-tcg and the block will always be skipped. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: fix default PHB4 QOM hierarchyDaniel Henrique Barboza1-20/+16
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s") changed phb4_pec code to create the default PHB4 objects in pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was removed and each PHB4 object is tied together with its PEC via the phb->pec pointer. This change also broke the previous QOM hierarchy - the PHB4 objects are being created and not being parented to their respective chips. This can be verified by 'info pic' in a powernv9 domain with default settings. pnv_chip_power9_pic_print_info() will fail to find the PHBs because object_child_foreach_recursive() won't find any. The solution is to set the parent chip and the parent bus, in the same way done for user created PHB4 devices, for all PHB4 devices. Fixes: 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220218202804.413157-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/pnv: Determine ns16550's IRQ number from QOM propertyBernhard Beschow1-1/+4
Determine the IRQ number in the same way as for pnv_dt_ipmi_bt(). This resolves one usage of ISADevice::isairq[] which allows it to be removed eventually. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-6-shentey@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-01Merge remote-tracking branch ↵Peter Maydell16-742/+362
'remotes/bsdimp/tags/bsd-user-preen-2022q1-pull-request' into staging bsd-user: Prepare for future upstream of system calls. This series of patches does three things. First, it starts to give up on the idea that you can run FooBSD binaries on BarBSD. They are too different to make that happen any time soon, though I've kept the support for Net/OpenBSD, even though they haven't built. We'll need a lot of work to make that happen, though, and I need to simplify to get things upstream. Second, it starts to move some of the ifdef trees into target.h. Third, it starts to upstream bsd-file.h, but the remainder of the file in the bsd-user fork had some issues that will be resolved before next quarter's update. # gpg: Signature made Mon 28 Feb 2022 18:11:47 GMT # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * remotes/bsdimp/tags/bsd-user-preen-2022q1-pull-request: bsd-user: Add safe system call macros bsd-user: Define target_arg64 bsd-user: introduce target.h bsd-user/bsd-file.h: Implementation details for the filesystem calls bsd-user/freebsd/os-syscall.c: Add get_errno and host_to_target_errno bsd-user/sycall.c: Now obsolete, remove bsd-user: Move system call building to os-syscall.c bsd-user/freebsd/os-syscall.c: Move syscall processing here bsd-user: Remove bsd_type bsd-user/x86_64/target_arch_thread.h: Assume a FreeBSD target bsd-user/arm/target_arch_thread.h: Assume a FreeBSD target bsd-user/arm/target_arch_cpu.h: Only support FreeBSD sys calls bsd-user/i386/target_arch_cpu.h: Remove openbsd syscall bsd-user/x86_64/target_arch_cpu.h: Remove openbsd syscall bsd-user/x86_64/target_arch_cpu.h: int $80 never was a BSD system call on amd64 bsd-user/main.c: Drop syscall flavor arg -bsd Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220228' ↵Peter Maydell7-14/+27
into staging Fix typecode generation for tcg helpers Fix single stepping into interrupt handlers Fix out-of-range offsets for stores in TCI # gpg: Signature made Mon 28 Feb 2022 18:07:13 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20220228: tcg/tci: Use tcg_out_ldst in tcg_out_st accel/tcg/cpu-exec: Fix precise single-stepping after interrupt tcg: Remove dh_alias indirection for dh_typecode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch ↵Peter Maydell13-20/+241
'remotes/thuth-gitlab/tags/pull-request-2022-02-28' into staging * Fix emulation of the SET CLOCK instruction * Fix the s390x avocado test with Fedora * Update the s390x Travis jobs to Focal (instead of Bionic) * Implement the z15 Misc Instruction Extension 3 Facility # gpg: Signature made Mon 28 Feb 2022 10:34:47 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2022-02-28: tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3 s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1 s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x travis.yml: Update the s390x jobs to Ubuntu Focal tests/avocado/machine_s390_ccw_virtio: Adapt test to new default resolution s390x: sck: load into a temporary not into in1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-01Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2022-02-28' into ↵Peter Maydell14-61/+64
staging QAPI patches patches for 2022-02-28 # gpg: Signature made Mon 28 Feb 2022 10:40:22 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2022-02-28: qapi: Belatedly adjust limitations documentation rtc: Have event RTC_CHANGE identify the RTC by QOM path hw/rtc: Compile pl031 once-only qapi: Document some missing details of RTC_CHANGE event qapi: Move RTC_CHANGE back out of target schema qapi/migration: Fix examples document wrong field name for arguments qapi: Fix stale reference to scripts/qapi.py in a comment keyval: Fix grammar comment to cover downstream prefix scripts/qapi: minor delinting Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28tcg/tci: Use tcg_out_ldst in tcg_out_stRichard Henderson1-3/+2
The tcg_out_ldst helper will handle out-of-range offsets. We haven't actually encountered any, since we haven't run across the assert within tcg_out_op_rrs, but an out-of-range offset would not be impossible in future. Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28accel/tcg/cpu-exec: Fix precise single-stepping after interruptLuc Michel1-2/+6
In some cases, cpu->exit_request can be false after handling the interrupt, leading to another TB being executed instead of returning to the main loop. Fix this by returning true unconditionally when in single-step mode. Fixes: ba3c35d9c402 ("tcg/cpu-exec: precise single-stepping after an interrupt") Signed-off-by: Luc Michel <lmichel@kalray.eu> Message-Id: <20220214132656.11397-1-lmichel@kalray.eu> [rth: Unlock iothread mutex; simplify indentation] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28tcg: Remove dh_alias indirection for dh_typecodeRichard Henderson5-9/+19
The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call parameters. This bug was detected when running the 'arm' emulator on an s390 system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect sign data in the typemask for each argument caused the values to be extended as unsigned values. This simple program exhibits the problem: static volatile int num = -9; static volatile int den = -5; int main(void) { int quo = num / den; printf("num %d den %d quo %d\n", num, den, quo); exit(0); } When run on the broken qemu, this results in: num -9 den -5 quo 0 The correct result is: num -9 den -5 quo 1 Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-28Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' ↵Peter Maydell13-79/+236
into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28tests/tcg: port SYS_HEAPINFO to a system testAlex Bennée2-0/+94
This allows us to check our new SYS_HEAPINFO implementation generates sane values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220225172021.3493923-19-alex.bennee@linaro.org>
2022-02-28semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFOAlex Bennée3-61/+163
The previous numbers were a guess at best and rather arbitrary without taking into account anything that might be loaded. Instead of using guesses based on the state of registers implement a new function that: a) scans the MemoryRegions for the largest RAM block b) iterates through all "ROM" blobs looking for the biggest gap The "ROM" blobs include all code loaded via -kernel and the various -device loader techniques. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Andrew Strauss <astrauss11@gmail.com> Cc: Keith Packard <keithp@keithp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220225172021.3493923-18-alex.bennee@linaro.org>
2022-02-28tests/tcg: completely disable threadcount for sh4Alex Bennée1-0/+2
The previous disabling of threadcount 3bdc19af00 ("tests/tcg/sh4: disable another unreliable test") just for plugins was being too conservative. It's all broken so skip it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-17-alex.bennee@linaro.org>
2022-02-28gitlab: upgrade the job definition for s390x to 20.04Alex Bennée2-15/+15
The new s390x machine has more of everything including the OS. As 18.04 will soon be going we might as well get onto something moderately modern. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-16-alex.bennee@linaro.org>
2022-02-28travis.yml: Update the s390x jobs to Ubuntu FocalThomas Huth1-7/+5
QEMU will soon drop the support for Ubuntu 18.04, so let's update the Travis jobs that were still using this version to 20.04 instead. While we're at it, also remove an obsolete comment about Ubuntu Xenial being the default for our Travis jobs. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220221153423.1028465-1-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-15-alex.bennee@linaro.org>
2022-02-28tests/tcg: add vectorised sha512 versionsAlex Bennée7-2/+56
This builds vectorised versions of sha512 to exercise the vector code: - aarch64 (AdvSimd) - i386 (SSE) - s390x (MVX) - ppc64/ppc64le (power10 vectors) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-14-alex.bennee@linaro.org>
2022-02-28tests/tcg: add sha512 testAlex Bennée1-0/+990
This imports the sha512 algorithm and related tests from ccan which offers a cleaner hash implementation with its own validation tests with which we can exercise TCG code generations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-13-alex.bennee@linaro.org>
2022-02-28tests/tcg: build sha1-vector with O3 and compareAlex Bennée2-0/+19
The aim of this is to test code generation for vectorised operations. Unfortunately gcc struggles to do much with the messy sha1 code (try -fopt-info-vec-missed to see why). However it's better than nothing. We assume the non-vectorised output is gold and baring compiler bugs the outputs should match. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-12-alex.bennee@linaro.org>
2022-02-28tests/tcg/ppc64: clean-up handling of byte-reverseAlex Bennée1-9/+4
Rather than having an else leg for the missing compiler case we can simply just not add the test - the same way as is done for ppc64le. Also while we are at it fix up the compiler invocation. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-11-alex.bennee@linaro.org>
2022-02-28gitlab: add a new aarch32 custom runner definitionAlex Bennée2-0/+30
Although running on aarch64 hardware we can still target 32bit builds with a cross compiler and run the resulting binaries. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220225172021.3493923-10-alex.bennee@linaro.org>
2022-02-28scripts/ci: allow for a secondary runnerAlex Bennée1-0/+38
Some HW can run multiple architecture profiles so we can install a secondary runner to build and run tests for those profiles. This allows setting up secondary service. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-9-alex.bennee@linaro.org>
2022-02-28scripts/ci: add build env rules for aarch32 on aarch64Alex Bennée1-0/+25
At least the current crop of Aarch64 HW can support running 32 bit EL0 code. Before we can build and test we need a minimal set of packages installed. We can't use "apt build-dep" because it currently gets confused trying to keep two sets of build-deps installed at once. Instead we install a minimal set of libraries that will allow us to continue. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-8-alex.bennee@linaro.org>
2022-02-28tests/docker: introduce debian-riscv64-test-crossAlex Bennée4-1/+22
Cross building QEMU for riscv64 still involves messing about with sid and ports. However for building tests we can have a slimmer compiler only container which should be more stable. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-7-alex.bennee@linaro.org>
2022-02-28tests/docker: update debian-s390x-cross with lcitoolAlex Bennée4-28/+162
A later compiler is needed for some upcomming tests so we might as well migrate to an lcitool generated docker file. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-6-alex.bennee@linaro.org>
2022-02-28tests/docker: update debian-arm64-cross with lcitoolAlex Bennée6-52/+173
Using lcitool update debian-arm64-cross to a Debian 11 based system. As a result we can drop debian-arm64-test-cross just for building tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-5-alex.bennee@linaro.org>
generated by cgit v1.1 at 2025-09-24 20:57:48 +0000