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2017-09-06migration: dump str in migrate_set_state tracePeter Xu2-2/+3
Strings are more readable for debugging. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <1504081950-2528-5-git-send-email-peterx@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Fixed up merge with 977c73
2017-09-06nbd: Use new qio_channel_*_all() functionsEric Blake5-93/+18
Rather than open-coding our own read/write-all functions, we can make use of the recently-added qio code. It slightly changes the error message in one of the iotests. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20170905191114.5959-4-eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
2017-09-06io: Add new qio_channel_read{, v}_all_eof functionsEric Blake2-8/+93
Some callers want to distinguish between clean EOF (no bytes read) vs. a short read (at least one byte read, but EOF encountered before reaching the desired length), as it allows clients the ability to do a graceful shutdown when a server shuts down at defined safe points in the protocol, rather than treating all shutdown scenarios as an error due to EOF. However, we don't want to require all callers to have to check for early EOF. So add another wrapper function that can be used by the callers that care about the distinction. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20170905191114.5959-3-eblake@redhat.com> Acked-by: Daniel P. Berrange <berrange@redhat.com>
2017-09-06io: Yield rather than wait when already in coroutineEric Blake1-2/+10
The new qio_channel_{read,write}{,v}_all functions are documented as yielding until data is available. When used on a blocking channel, this yield is done via qio_channel_wait() which spawns a nested event loop under the hood (so it is that secondary loop which yields as needed); but if we are already in a coroutine (at which point QIO_CHANNEL_ERR_BLOCK is only possible if we are a non-blocking channel), we want to yield the current coroutine instead of spawning a nested event loop. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20170905191114.5959-2-eblake@redhat.com> Acked-by: Daniel P. Berrange <berrange@redhat.com> [commit message updated] Signed-off-by: Eric Blake <eblake@redhat.com>
2017-09-06target/arm: Perform per-insn cross-page check only for ThumbRichard Henderson1-25/+33
ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: Split out thumb_tr_translate_insnRichard Henderson1-41/+80
We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: Move ss check to init_disas_contextRichard Henderson1-5/+8
We can check for single-step just once. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [a64] Move page and ss checks to init_disas_contextRichard Henderson1-8/+9
Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to generic translation frameworkLluís Vilanova3-183/+41
Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002631325.22386.10348327185029496649.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg,a64] Port to disas_logLluís Vilanova1-5/+14
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002606914.22386.15524101311003685068.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to disas_logLluís Vilanova1-5/+13
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002582711.22386.191527630537864599.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg,a64] Port to tb_stopLluís Vilanova1-60/+67
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002558503.22386.1149037590886263349.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to tb_stopLluís Vilanova1-77/+84
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg,a64] Port to translate_insnLluís Vilanova1-28/+43
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to translate_insnLluís Vilanova2-75/+91
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg,a64] Port to breakpoint_checkLluís Vilanova1-17/+31
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg,a64] Port to insn_startLluís Vilanova2-22/+44
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to insn_startLluís Vilanova1-4/+11
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to tb_startLluís Vilanova1-38/+44
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg,a64] Port to init_disas_contextLluís Vilanova1-14/+24
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to init_disas_contextLluís Vilanova1-38/+50
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002316201.22386.12115078843605656029.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [tcg] Port to DisasContextBaseLluís Vilanova3-121/+120
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002291931.22386.11441154993010495674.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to generic translation frameworkLluís Vilanova1-87/+19
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Emilio G. Cota <cota@braap.org> Tested-by: Emilio G. Cota <cota@braap.org> Message-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to disas_logLluís Vilanova1-13/+19
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002243497.22386.8888053391875656102.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to tb_stopLluís Vilanova1-12/+14
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002219289.22386.17959138704858928730.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to translate_insnLluís Vilanova1-24/+42
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Emilio G. Cota <cota@braap.org> Message-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to breakpoint_checkLluís Vilanova1-12/+34
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Emilio G. Cota <cota@braap.org> Message-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to insn_startLluís Vilanova1-1/+8
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002146647.22386.13380064201042141261.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to init_disas_contextLluís Vilanova1-19/+27
Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: [tcg] Port to DisasContextBaseLluís Vilanova1-71/+69
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002098212.22386.17313318023406046314.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg: Add generic translation frameworkLluís Vilanova3-0/+243
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002073981.22386.9870422422367410100.stgit@frigg.lan> [rth: Moved max_insns adjustment from tb_start to init_disas_context. Removed pc_next return from translate_insn. Removed tcg_check_temp_count from generic loop. Moved gen_io_end to exactly match gen_io_start. Use qemu_log instead of error_report for temporary leaks. Moved TB size/icount assignments before disas_log.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: Delay check for magic kernel pageRichard Henderson1-11/+11
There's nothing magic about the exception that we generate in order to execute the magic kernel page. We can and should allow gdb to set a breakpoint at this location. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova14-46/+104
Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: Use DISAS_NORETURNRichard Henderson3-29/+30
Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/i386: Use generic DISAS_* enumeratorsRichard Henderson1-13/+15
This target is not sophisticated in its use of cleanups at the end of the translation loop. For the most part, any condition that exits the TB is dealt with by emitting the exiting opcode right then and there. Therefore the only is_jmp indicator that is needed is DISAS_NORETURN. For two stack segment modifying cases, we have not yet exited the TB (therefore DISAS_NORETURN feels wrong), but intend to exit. The caller of gen_movl_seg_T0 currently checks for any non-zero value, therefore DISAS_TOO_MANY seems acceptable for that usage. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg: Add generic DISAS_NORETURNRichard Henderson1-0/+1
This will allow some amount of cleanup to happen before switching the backends over to enum DisasJumpType. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Use slbgr for setcond le and leuRichard Henderson1-76/+43
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Use load-on-condition-2 facilityRichard Henderson2-17/+63
This allows LOAD HALFWORD IMMEDIATE ON CONDITION, eliminating one insn in some common cases. Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Use distinct-operands facilityRichard Henderson2-28/+91
This allows using a 3-operand insn form for some arithmetic, logicals and shifts. Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge ori+xori facilities check to tcg_target_op_defRichard Henderson1-68/+33
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge add2i facilities check to tcg_target_op_defRichard Henderson1-24/+14
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge muli facilities check to tcg_target_op_defRichard Henderson1-20/+25
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge cmpi facilities check to tcg_target_op_defRichard Henderson1-38/+30
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Fully convert tcg_target_op_defRichard Henderson1-124/+154
Use a switch instead of searching a table. Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06snapshot/tests: Try loadvm twiceDr. David Alan Gilbert2-1/+5
It's legal to loadvm twice, modify the existing save/loadvm test to do it twice. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170825141940.20740-3-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-09-06disas/i386: Add disassembly of rorxRichard Henderson1-2/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06disas/i386: Add disassembly of vex.0f38.f5Richard Henderson1-3/+12
Which includes pext, pdep and bzhi. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06disas/i386: Fix disassembly of two-byte vex prefixesRichard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06migration: Reset rather than destroy main_thread_load_eventDr. David Alan Gilbert1-1/+1
migration_incoming_state_destroy doesn't really destroy, it cleans up. After a loadvm it's called, but the loadvm command can be run twice, and so destroying an init-once mutex breaks on the second loadvm. Reported-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170825141940.20740-2-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Tested-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-09-06runstate/migrate: Two more transitionsDr. David Alan Gilbert1-0/+2
There's a race if someone does a 'stop' near the end of migrate; the migration process goes through two runstates: 'finish migrate' 'postmigrate' If the user issues a 'stop' between the two we end up with invalid state transitions. Add the transitions as valid. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170804175011.21944-1-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
generated by cgit v1.1 at 2024-09-29 08:38:22 +0000