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2020-12-10qapi: Normalize version references x.y.0 to just x.yMarkus Armbruster15-123/+123
2020-12-10Tweak a few "Parameter 'NAME' expects THING" error messageMarkus Armbruster5-6/+6
2020-12-10qom: Improve {qom,device}-list-properties error messagesMarkus Armbruster1-11/+6
2020-12-10qga: Tweak a guest-shutdown error messageMarkus Armbruster1-1/+1
2020-12-10qga: Replace an unreachable error by abort()Markus Armbruster1-2/+1
2020-12-10ui: Tweak a client_migrate_info error messageMarkus Armbruster1-1/+1
2020-12-10ui: Improve a client_migrate_info error messageMarkus Armbruster2-4/+1
2020-12-10ui: Improve some set_passwd, expire_password error messagesMarkus Armbruster2-26/+15
2020-12-10block: Improve some block-commit, block-stream error messagesMarkus Armbruster3-14/+15
2020-12-10qerror: Eliminate QERR_ macros used in just one placeMarkus Armbruster3-14/+5
2020-12-10qerror: Drop unused QERR_ macrosMarkus Armbruster1-6/+0
2020-12-10Clean up includesMarkus Armbruster27-78/+5
2020-12-10Merge remote-tracking branch 'remotes/kraxel/tags/microvm-20201210-pull-reque...Peter Maydell10-32/+128
2020-12-10Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201210'...Peter Maydell34-150/+2710
2020-12-10hw/arm/armv7m: Correct typo in QOM object namePeter Maydell1-1/+1
2020-12-10hw/intc/armv7m_nvic: Implement read/write for RAS register blockPeter Maydell2-0/+57
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell3-0/+31
2020-12-10hw/intc/armv7m_nvic: Fix "return from inactive handler" checkPeter Maydell1-27/+32
2020-12-10target/arm: Implement CCR_S.TRD behaviour for SG insnsPeter Maydell1-0/+86
2020-12-10hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell2-8/+20
2020-12-10target/arm: Implement new v8.1M VLLDM and VLSTM encodingsPeter Maydell2-1/+26
2020-12-10target/arm: Implement new v8.1M NOCP check for exception returnPeter Maydell1-1/+21
2020-12-10target/arm: Implement v8.1M REVIDR registerPeter Maydell1-0/+5
2020-12-10target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failuresPeter Maydell1-1/+5
2020-12-10target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entryPeter Maydell1-4/+12
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell3-1/+16
2020-12-10target/arm: Implement FPCXT_S fp system registerPeter Maydell1-0/+58
2020-12-10target/arm: Factor out preserve-fp-state from full_vfp_access_check()Peter Maydell1-18/+27
2020-12-10target/arm: Use new FPCR_NZCV_MASK constantPeter Maydell1-2/+2
2020-12-10target/arm: Implement M-profile FPSCR_nzcvqcPeter Maydell2-0/+40
2020-12-10target/arm: Implement VLDR/VSTR system registerPeter Maydell2-0/+105
2020-12-10target/arm: Move general-use constant expanders up in translate.cPeter Maydell1-21/+25
2020-12-10target/arm: Refactor M-profile VMSR/VMRS handlingPeter Maydell2-11/+168
2020-12-10target/arm: Enforce M-profile VMRS/VMSR register restrictionsPeter Maydell1-1/+4
2020-12-10target/arm: Implement CLRM instructionPeter Maydell2-1/+43
2020-12-10target/arm: Implement VSCCLRM insnPeter Maydell4-11/+111
2020-12-10target/arm: Don't clobber ID_PFR1.Security on M-profile coresPeter Maydell1-1/+1
2020-12-10target/arm: Implement v8.1M PXN extensionPeter Maydell1-1/+6
2020-12-10hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFaultPeter Maydell3-12/+69
2020-12-10i.MX6ul: Fix bad printf format specifiersAlex Chen1-2/+2
2020-12-10i.MX6: Fix bad printf format specifiersAlex Chen2-11/+11
2020-12-10i.MX31: Fix bad printf format specifiersAlex Chen2-9/+9
2020-12-10i.MX25: Fix bad printf format specifiersAlex Chen1-6/+6
2020-12-10tests/qtest/npcm7xx_rng-test: dump random data on failureHavard Skinnemoen1-0/+12
2020-12-10sbsa-ref: allow to use Cortex-A53/57/72 cpusMarcin Juszkiewicz1-3/+20
2020-12-10MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controllerVikram Garhwal1-0/+8
2020-12-10tests/qtest: Introduce tests for Xilinx ZynqMP CAN controllerVikram Garhwal2-0/+361
2020-12-10xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllersVikram Garhwal3-0/+62
2020-12-10hw/net/can: Introduce Xilinx ZynqMP CAN controllerVikram Garhwal7-0/+1252
2020-12-10hw/arm/smmuv3: Fix up L1STD_SPAN decodingKunkun Jiang1-1/+1
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