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2021-10-13s390x: sigp: Force Set Architecture to return Invalid ParameterEric Farman1-17/+1
According to the Principles of Operation, the SIGP Set Architecture order will return Incorrect State if some CPUs are not stopped, but only if the CZAM facility is not present. If it is, the order will return Invalid Parameter because the architecture mode cannot be changed. Since CZAM always exists when S390_FEAT_ZARCH exists, which in turn exists for every defined CPU model, we can simplify this code. Fixes: 075e52b81664 ("s390x/cpumodel: we are always in zarchitecture mode") Signed-off-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Message-Id: <20211008203811.1980478-2-farman@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-10-13s390x/ipl: check kernel command line sizeMarc Hartmayer1-1/+11
Check if the provided kernel command line exceeds the maximum size of the s390x Linux kernel command line size, which is 896 bytes. Reported-by: Sven Schnelle <svens@linux.ibm.com> Signed-off-by: Marc Hartmayer <mhartmay@linux.ibm.com> Message-Id: <20211006092631.20732-1-mhartmay@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [thuth: Adjusted format specifier for size_t] Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-10-12Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-121021-2' ↵Richard Henderson22-158/+271
into staging Some testing and plugin updates: - don't override the test compiler when specified - split some multiarch tests by guest OS - add riscv64 docker image and cross-compile tests - drop release tarball test from Travis - skip check-patch on master repo - fix passing of TEST_TARGETS to cirrus - fix missing symbols in plugins - ensure s390x insn start ops precede plugin instrumentation - refactor plugin instruction boundary detection - update github repo lockdown - add a debian-native test image for multi-arch builds # gpg: Signature made Tue 12 Oct 2021 02:35:00 AM PDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] * remotes/stsquad/tags/pull-for-6.2-121021-2: tests/docker: add a debian-native image and make available .github: move repo lockdown to the v2 configuration accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is valid target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start plugins/: Add missing functions to symbol list gitlab: fix passing of TEST_TARGETS env to cirrus gitlab: skip the check-patch job on the upstream repo travis.yml: Remove the "Release tarball" job gitlab: Add cross-riscv64-system, cross-riscv64-user tests/docker: promote debian-riscv64-cross to a full image tests/tcg: move some multiarch files and make conditional tests/tcg/sha1: remove endian include configure: don't override the selected host test compiler if defined Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-12Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211012' into ↵Richard Henderson16-618/+1352
staging Aspeed patches : * I2C QOMify (Cedric) * SMC model cleanup and QOMify (Cedric) * ADC model (Peter and Andrew) * GPIO fixes (Peter) # gpg: Signature made Tue 12 Oct 2021 12:36:22 AM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/clg/tags/pull-aspeed-20211012: aspeed/smc: Dump address offset in trace events aspeed/wdt: Add trace events hw/arm: Integrate ADC model into Aspeed SoC hw/adc: Add basic Aspeed ADC model hw: aspeed_gpio: Fix GPIO array indexing hw: aspeed_gpio: Fix pin I/O type declarations aspeed/i2c: QOMify AspeedI2CBus aspeed/smc: Remove unused attribute 'irqline' aspeed/smc: Introduce a new addr_width() class handler aspeed/smc: Add default reset values aspeed/smc: QOMify AspeedSMCFlash aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs' aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash aspeed/smc: Drop AspeedSMCController structure aspeed/smc: Stop using the model name for the memory regions aspeed/smc: Introduce aspeed_smc_error() helper aspeed/smc: Add watchdog Control/Status Registers Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-12tests/docker: add a debian-native image and make availableAlex Bennée3-2/+61
This image is intended for building whatever the native versions of QEMU are for the host architecture. This will hopefully be an aid for 3rd parties who want to be able to build QEMU themselves without redoing all the dependencies themselves. We disable the registry because we currently don't have multi-arch support there. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Anders Roxell <anders.roxell@linaro.org> Acked-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210922151528.2192966-1-alex.bennee@linaro.org>
2021-10-12.github: move repo lockdown to the v2 configurationAlex Bennée2-34/+30
I was getting prompted by GitHub for new permissions but it turns out per https://github.com/dessant/repo-lockdown/issues/6: Repo Lockdown has been rewritten for GitHub Actions, offering new features and better control over your automation presets. The legacy GitHub App has been deprecated, and the public instance of the app has been shut down. So this is what I've done. As the issues tab is disabled I've removed the handling for issues from the new version. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20211004154308.2114870-1-alex.bennee@linaro.org>
2021-10-12accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is validAlex Bennée2-78/+85
Coverity doesn't know enough about how we have arranged our plugin TCG ops to know we will always have incremented insn_idx before injecting the callback. Let us assert it for the benefit of Coverity and protect ourselves from accidentally breaking the assumption and triggering harder to grok errors deeper in the code if we attempt a negative indexed array lookup. However to get to this point we re-factor the code and remove the second hand instruction boundary detection in favour of scanning the full set of ops and using the existing INDEX_op_insn_start to cleanly detect when the instruction has started. As we no longer need the plugin specific list of ops we delete that. My initial benchmarks shows no discernible impact of dropping the plugin specific ops list. Fixes: Coverity 1459509 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210917162332.3511179-12-alex.bennee@linaro.org>
2021-10-12target/s390x: move tcg_gen_insn_start to s390x_tr_insn_startRichard Henderson1-2/+8
We use INDEX_op_insn_start to make the start of instruction boundaries. If we don't do it in the .insn_start hook things get confused especially now plugins want to use that marking to identify the start of instructions and will bomb out if it sees instrumented ops before the first instruction boundary. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211011185332.166763-1-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-10-12plugins/: Add missing functions to symbol listLukas Jünger1-0/+3
Some functions of the plugin API were missing in the symbol list. However, they are all used by the contributed example plugins. QEMU fails to load the plugin if the function symbol is not exported. Signed-off-by: Lukas Jünger <lukas.junger@greensocs.com> Message-Id: <20210905140939.638928-2-lukas.junger@greensocs.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210917162332.3511179-11-alex.bennee@linaro.org>
2021-10-12gitlab: fix passing of TEST_TARGETS env to cirrusDaniel P. Berrangé2-1/+2
A typo meant the substitution would not work, and the placeholder in the target file didn't even exist. The result was that tests were never run on the FreeBSD and macOS jobs, only a basic build. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210915125452.1704899-3-berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210917162332.3511179-10-alex.bennee@linaro.org>
2021-10-12gitlab: skip the check-patch job on the upstream repoDaniel P. Berrangé1-1/+1
The check-patch job is intended to be used by contributors or subsystem maintainers to see if there are style mistakes. The false positive rate is too high to be used in a gating scenario so should not run it on the upstream repo ever. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210915125452.1704899-2-berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210917162332.3511179-9-alex.bennee@linaro.org>
2021-10-12travis.yml: Remove the "Release tarball" jobThomas Huth1-23/+0
This is a leftover from the days when we were using Travis excessively, but since x86 jobs are not really usable there anymore, this job has likely never been used since many months. Let's simply remove it now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210917094826.466047-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210917162332.3511179-8-alex.bennee@linaro.org>
2021-10-12gitlab: Add cross-riscv64-system, cross-riscv64-userRichard Henderson1-0/+19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210914185830.1378771-3-richard.henderson@linaro.org> [AJB: add allow_failure] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210917162332.3511179-6-alex.bennee@linaro.org>
2021-10-12tests/docker: promote debian-riscv64-cross to a full imageAlex Bennée3-8/+43
To be able to cross build QEMU itself we need to include a few more libraries. These are only available in Debian's unstable ports repo for now so we need to base the riscv64 image on sid with the the minimal libs needed to build QEMU (glib/pixman). The result works but is not as clean as using build-dep to bring in more dependencies. However sid is by definition a shifting pile of sand and by keeping the list of libs minimal we reduce the chance of having an image we can't build. It's good enough for a basic cross build testing of TCG. Cc: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210914185830.1378771-2-richard.henderson@linaro.org> [AJB: tweak allow_failure] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210917162332.3511179-5-alex.bennee@linaro.org>
2021-10-12tests/tcg: move some multiarch files and make conditionalAlex Bennée4-6/+15
We had some messy code to filter out stuff we can't build. Lets junk that and simplify the logic by pushing some stuff into subdirs. In particular we move: float_helpers into libs - not a standalone test linux-test into linux - so we only build on Linux hosts This allows for at least some of the tests to be nominally usable by *BSD user builds. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20210917162332.3511179-4-alex.bennee@linaro.org>
2021-10-12tests/tcg/sha1: remove endian includeAlex Bennée1-1/+0
This doesn't exist in BSD world and doesn't seem to be needed by either. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20210917162332.3511179-3-alex.bennee@linaro.org>
2021-10-12configure: don't override the selected host test compiler if definedAlex Bennée1-2/+4
There are not many cases you would want to do this but one is if you want to use a test friendly compiler like gcc instead of a system compiler like clang. Either way we should honour the users choice if they have made it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Warner Losh <imp@bsdimp.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20210917162332.3511179-2-alex.bennee@linaro.org>
2021-10-12aspeed/smc: Dump address offset in trace eventsCédric Le Goater1-3/+3
The register index is currently printed and this is confusing. Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/wdt: Add trace eventsCédric Le Goater2-0/+9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12hw/arm: Integrate ADC model into Aspeed SoCAndrew Jeffery3-0/+24
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20211005052604.1674891-3-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12hw/adc: Add basic Aspeed ADC modelAndrew Jeffery4-0/+486
This model implements enough behaviour to do basic functionality tests such as device initialisation and read out of dummy sample values. The sample value generation strategy is similar to the STM ADC already in the tree. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> [clg : support for multiple engines (AST2600) ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [pdel : refactored engine register struct fields to regs[] array field] [pdel : added guest-error checking for upper-8 channel regs in AST2600] [pdel : allow 16-bit reads of the channel data registers] Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20211005052604.1674891-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12hw: aspeed_gpio: Fix GPIO array indexingPeter Delevoryas2-50/+35
The gpio array is declared as a dense array: qemu_irq gpios[ASPEED_GPIO_NR_PINS]; (AST2500 has 228, AST2400 has 216, AST2600 has 208) However, this array is used like a matrix of GPIO sets (e.g. gpio[NR_SETS][NR_PINS_PER_SET] = gpio[8][32]) size_t offset = set * GPIOS_PER_SET + gpio; qemu_set_irq(s->gpios[offset], !!(new & mask)); This can result in an out-of-bounds access to "s->gpios" because the gpio sets do _not_ have the same length. Some of the groups (e.g. GPIOAB) only have 4 pins. 228 != 8 * 32 == 256. To fix this, I converted the gpio array from dense to sparse, to that match both the hardware layout and this existing indexing code. Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20211008033501.934729-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12hw: aspeed_gpio: Fix pin I/O type declarationsPeter Delevoryas1-4/+4
Some of the pin declarations in the Aspeed GPIO module were incorrect, probably because of confusion over which bits in the input and output uint32_t's correspond to which groups in the label array. Since the uint32_t literals are in big endian, it's sort of the opposite of what would be intuitive. The least significant bit in ast2500_set_props[6] corresponds to GPIOY0, not GPIOAB7. GPIOxx indicates input and output capabilities, GPIxx indicates only input, GPOxx indicates only output. AST2500: - Previously had GPIW0..GPIW7 and GPIX0..GPIX7, that's correct. - Previously had GPIOY0..GPIOY3, should have been GPIOY0..GPIOY7. - Previously had GPIOAB0..GPIOAB3 and GPIAB4..GPIAB7, should only have been GPIOAB0..GPIOAB3. AST2600: - GPIOT0..GPIOT7 should have been GPIT0..GPIT7. - GPIOU0..GPIOU7 should have been GPIU0..GPIU7. - GPIW0..GPIW7 should have been GPIOW0..GPIOW7. - GPIOY0..GPIOY7 and GPIOZ0...GPIOZ7 were disabled. Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Fixes: 36d737ee82b2972167e ("hw/gpio: Add in AST2600 specific implementation") Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Message-Id: <20210928032456.3192603-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/i2c: QOMify AspeedI2CBusCédric Le Goater3-25/+91
Introduce an AspeedI2CBus SysBusDevice model and attach the associated memory region and IRQ to the newly instantiated objects. Before this change, the I2C bus IRQs were all attached to the SysBusDevice model of the I2C controller. Adapt the AST2600 SoC realize routine to take into account this change. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Remove unused attribute 'irqline'Cédric Le Goater1-1/+0
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Introduce a new addr_width() class handlerCédric Le Goater2-7/+13
The AST2400 SPI controller has a transitional HW interface and it stores the address width currently in use in a different register than all the other SMC controllers. It needs special handling when working in 4B mode. Make it clear through a class handler. This also removes another use of the segments array. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Add default reset valuesCédric Le Goater2-25/+28
This simplifies the reset handler and has the benefit to remove some "bad" use of the segments array as an identifier of the controller model. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: QOMify AspeedSMCFlashCédric Le Goater2-12/+77
AspeedSMCFlash is a small structure representing the AHB memory window through which the contents of a flash device can be accessed with MMIOs. Introduce an AspeedSMCFlash SysBusDevice model and attach the associated memory region to the newly instantiated objects. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'Cédric Le Goater2-16/+16
'cs' is a more appropriate name to index SPI flash devices. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Remove the 'size' attribute from AspeedSMCFlashCédric Le Goater3-7/+6
AspeedSMCFlash::size is only used to compute the initial size of the boot_rom region. Not very useful, so directly call memory_region_size() instead. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlashCédric Le Goater2-7/+5
There is no need to keep a reference of the flash qdev in the AspeedSMCFlash state: the SPI bus takes ownership and will release its resources. Remove AspeedSMCFlash::flash. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Drop AspeedSMCController structureCédric Le Goater4-422/+511
The characteristics of the Aspeed controllers are described in a AspeedSMCController structure which is redundant with the AspeedSMCClass. Move all attributes under the class and adapt the code to use class attributes instead. This is a large change but it is functionally equivalent. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Stop using the model name for the memory regionsCédric Le Goater1-15/+10
There is no real reason to use this name. It's simply nice to have in the monitor output but it's a burden for the following patch which removes the AspeedSMCController structure describing the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Introduce aspeed_smc_error() helperCédric Le Goater1-52/+45
It unifies the errors reported by the Aspeed SMC model and also removes some use of ctrl->name which will help us for the next patches. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Add watchdog Control/Status RegistersCédric Le Goater1-1/+18
The Aspeed SoCs have a dual boot function for firmware fail-over recovery. The system auto-reboots from the second flash if the main flash does not boot successfully within a certain amount of time. This function is called alternate boot (ABR) in the FMC controllers. On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to enable the 2nd watchdog timer, on AST2600, through register SCU510. If the boot on the the main flash succeeds, the firmware should disable the 2nd watchdog timer. If not, the BMC is reset and the CE0 and CE1 mappings are swapped to restart the BMC from the 2nd flash. On the AST2600, the ABR registers controlling the 2nd watchdog timer were moved from the watchdog register to the FMC controller and the FMC model should be able to control WDT2 through its own register set. This requires more work. For now, add dummy read/write handlers to let the FW disable the 2nd watchdog without error. Reviewed-by: Peter Delevoryas <pdel@fb.com> Reported-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-11Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Richard Henderson1-13/+15
staging Pull request # gpg: Signature made Mon 11 Oct 2021 05:40:35 AM PDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] * remotes/stefanha/tags/block-pull-request: iothread: use IOThreadParamInfo in iothread_[set|get]_param() iothread: rename PollParamInfo to IOThreadParamInfo Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-08Merge remote-tracking branch ↵Richard Henderson4-30/+429
'remotes/vivier-m68k/tags/m68k-next-pull-request' into staging Pull request q800 20211008 macfb: fixes for booting MacOS # gpg: Signature made Fri 08 Oct 2021 04:44:44 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier-m68k/tags/m68k-next-pull-request: q800: wire macfb IRQ to separate video interrupt on VIA2 macfb: add vertical blank interrupt macfb: fix 24-bit RGB pixel encoding macfb: fix up 1-bit pixel encoding macfb: add common monitor modes supported by the MacOS toolbox ROM macfb: add qdev property to specify display type macfb: implement mode sense to allow display type to be detected macfb: add trace events for reading and writing the control registers macfb: use memory_region_init_ram() in macfb_common_realize() for the framebuffer macfb: fix overflow of color_palette array macfb: fix invalid object reference in macfb_common_realize() macfb: update macfb.c to use the Error API best practices macfb: handle errors that occur during realize Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-08q800: wire macfb IRQ to separate video interrupt on VIA2Mark Cave-Ayland1-2/+5
Whilst the in-built Quadra 800 framebuffer exists within the Nubus address space for slot 9, it has its own dedicated interrupt on VIA2. Force the macfb device to occupy slot 9 in the q800 machine and wire its IRQ to the separate video interrupt since this is what is expected by the MacOS interrupt handler. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-14-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: add vertical blank interruptMark Cave-Ayland2-0/+91
The MacOS driver expects a 60.15Hz vertical blank interrupt to be generated by the framebuffer which in turn schedules the mouse driver via the Vertical Retrace Manager. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: fix 24-bit RGB pixel encodingMark Cave-Ayland1-4/+4
According to Apple Technical Note HW26: "Macintosh Quadra Built-In Video" the in-built framebuffer encodes each 24-bit pixel into 4 bytes. Adjust the 24-bit RGB pixel encoding accordingly which agrees with the encoding expected by MacOS when changing into 24-bit colour mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: fix up 1-bit pixel encodingMark Cave-Ayland1-1/+3
The MacOS driver expects the RGB values for the pixel to be in entries 0 and 1 of the colour palette. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: add common monitor modes supported by the MacOS toolbox ROMMark Cave-Ayland4-21/+156
The monitor modes table is found by experimenting with the Monitors Control Panel in MacOS and analysing the reads/writes. From this it can be found that the mode is controlled by writes to the DAFB_MODE_CTRL1 and DAFB_MODE_CTRL2 registers. Implement the first block of DAFB registers as a register array including the existing sense register, the newly discovered control registers above, and also the DAFB_MODE_VADDR1 and DAFB_MODE_VADDR2 registers which are used by NetBSD to determine the current video mode. These experiments also show that the offset of the start of video RAM and the stride can change depending upon the monitor mode, so update macfb_draw_graphic() and both the BI_MAC_VADDR and BI_MAC_VROW bootinfo for the q800 machine accordingly. Finally update macfb_common_realize() so that only the resolution and depth supported by the display type can be specified on the command line, and add an error hint showing the list of supported resolutions and depths if the user tries to specify an invalid display mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: add qdev property to specify display typeMark Cave-Ayland3-1/+12
Since the available resolutions and colour depths are determined by the attached display type, add a qdev property to allow the display type to be specified. The main resolutions of interest are high resolution 1152x870 with 8-bit colour and SVGA resolution up to 800x600 with 24-bit colour so update the q800 machine to allow high resolution mode if specified and otherwise fall back to SVGA. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: implement mode sense to allow display type to be detectedMark Cave-Ayland3-2/+137
The MacOS toolbox ROM uses the monitor sense to detect the display type and then offer a fixed set of resolutions and colour depths accordingly. Implement the monitor sense using information found in Apple Technical Note HW26: "Macintosh Quadra Built-In Video" along with some local experiments. Since the default configuration is 640 x 480 with 8-bit colour then hardcode the sense register to return MACFB_DISPLAY_VGA for now. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: add trace events for reading and writing the control registersMark Cave-Ayland2-1/+11
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: use memory_region_init_ram() in macfb_common_realize() for the ↵Mark Cave-Ayland1-3/+2
framebuffer Currently macfb_common_realize() defines the framebuffer RAM memory region as being non-migrateable but then immediately registers it for migration. Replace memory_region_init_ram_nomigrate() with memory_region_init_ram() which is clearer and does exactly the same thing. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: fix overflow of color_palette arrayMark Cave-Ayland1-1/+3
The palette_current index counter has a maximum size of 256 * 3 to cover a full color palette of 256 RGB entries. Linux assumes that the palette_current index wraps back around to zero after writing 256 RGB entries so ensure that palette_current is reset at this point to prevent data corruption within MacfbState. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: fix invalid object reference in macfb_common_realize()Mark Cave-Ayland1-1/+1
During realize memory_region_init_ram_nomigrate() is used to initialise the RAM memory region used for the framebuffer but the owner object reference is incorrect since MacFbState is a typedef and not a QOM type. Change the memory region owner to be the corresponding DeviceState to fix the issue and prevent random crashes during macfb_common_realize(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: 8ac919a0654 ("hw/m68k: add Nubus macfb video card") Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: update macfb.c to use the Error API best practicesMark Cave-Ayland1-8/+8
As per the current Error API best practices, change macfb_commom_realize() to return a boolean indicating success to reduce errp boiler-plate handling code. Note that memory_region_init_ram_nomigrate() is also updated to use &error_abort to indicate a non-recoverable error, matching the behaviour recommended after similar discussions on memory API failures for the recent nubus changes. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-08macfb: handle errors that occur during realizeMark Cave-Ayland1-0/+11
Make sure any errors that occur within the macfb realize chain are detected and handled correctly to prevent crashes and to ensure that error messages are reported back to the user. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211007221253.29024-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.1 at 2025-01-13 11:30:58 +0000