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2019-05-17build: chardev is only needed for softmmu targetsLaurent Vivier2-2/+3
Move the dependency from SUBDIR_RULES to SOFTMMU_SUBDIR_RULES Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190401141222.30034-5-lvivier@redhat.com>
2019-05-17configure: qemu-ga is only needed with softmmu targetsLaurent Vivier1-1/+3
Remove it from the list of tools if --disable-system and --disable-tools are used as we don't need it for linux-user targets. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> [lv: I also disable it with disable-tools, not only with disable-system] Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190401141222.30034-4-lvivier@redhat.com>
2019-05-17build: replace GENERATED_FILES by generated-files-yLaurent Vivier4-36/+34
When possible use generated-files-$(FLAG) to disable some targets (like KEYCODEMAP_FILES). Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20190401141222.30034-3-lvivier@redhat.com>
2019-05-17trace: only include trace-event-subdirs when they are neededLaurent Vivier1-5/+7
Some directories are built only for softmmu targets, and the related trace-event-subdirs must do the same Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20190401141222.30034-2-lvivier@redhat.com>
2019-05-17sun4m: obey -vga nonePaolo Bonzini1-4/+2
Do not create a TCX if "-vga none" was passed on the command line. Remove some dead code along the way to avoid big reindentation. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17mips-fulong2e: obey -vga nonePaolo Bonzini1-4/+6
Do not create an ATI VGA if "-vga none" was passed on the command line. Cc: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17hw/i386/acpi: Assert a pointer is not null BEFORE using itPhilippe Mathieu-Daudé1-1/+1
Commit 72c194f7e75c added a non-null check on the 'obj' pointer. Later, commit 500b11ea5095 added code which uses the 'obj' pointer _before_ the assertion check. Move the assertion _before_ the pointer use. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190427144025.22880-4-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17hw/i386/acpi: Add object_resolve_type_unambiguous to improve modularityPhilippe Mathieu-Daudé5-30/+16
When building with CONFIG_Q35=n, we get: LINK x86_64-softmmu/qemu-system-x86_64 /usr/bin/ld: hw/i386/acpi-build.o: in function `acpi_get_misc_info': /source/qemu/hw/i386/acpi-build.c:243: undefined reference to `ich9_lpc_find' collect2: error: ld returned 1 exit status make[1]: *** [Makefile:204: qemu-system-x86_64] Error 1 This is due to a dependency in acpi-build.c on the ICH9_LPC (via ich9_lpc_find) and PIIX4_PM (via piix4_pm_find) devices. To allow better modularity (compile acpi-build.c with only Q35/ICH9 or ISAPC/PIIX4), refactor the similar helper as object_resolve_type_unambiguous(). This way we relax the linker dependencies and can build the x86 targets with a selection of machines (instead of all of them). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190427144025.22880-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17hw/acpi/piix4: Move TYPE_PIIX4_PM to a public headerPhilippe Mathieu-Daudé2-2/+2
Move the TYPE_PIIX4_PM definition to the corresponding header, so other files can use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190427144025.22880-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17memory: correct the comment to DIRTY_MEMORY_MIGRATIONWei Yang1-2/+2
The dirty bit is DIRTY_MEMORY_MIGRATION. Correct the comment. Signed-off-by: Wei Yang <richardw.yang@linux.intel.com> Message-Id: <20190426020927.25470-1-richardw.yang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17vl: fix -sandbox parsing crash when seccomp support is disabledMarc-André Lureau1-8/+10
$ ./x86_64-softmmu/qemu-system-x86_64 -sandbox off qemu-system-x86_64: -sandbox off: There is no option group 'sandbox' Segmentation fault Commit 5780760f5e ("seccomp: check TSYNC host capability") wrapped one use of the sandbox option group to produce a sensible error, it didn't do the same for another call to qemu_opts_parse_noisily(): (gdb) bt at util/qemu-option.c:829 #0 0x00000000105b36d8 in opts_parse (list=0x0, params=0x3ffffffffab5 "off", permit_abbrev=true, defaults=false, errp=0x3ffffffff080) at util/qemu-option.c:829 #1 0x00000000105b3b74 in qemu_opts_parse_noisily (list=<optimized out>, params=<optimized out>, permit_abbrev=<optimized out>) at util/qemu-option.c:890 #2 0x0000000010024964 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at vl.c:3589 Fixes: 5780760f5ea6163939a5dabe7427318b4f07d1a2 Cc: david@gibson.dropbear.id.au Cc: otubo@redhat.com Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190429134757.13570-1-marcandre.lureau@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-17hvf: Add missing break statementChen Zhang1-0/+1
In target/i386/hvf/hvf.c, a break statement was probably missing in `hvf_vcpu_exec()`, in handling EXIT_REASON_HLT. These lines seemed to be equivalent to `kvm_handle_halt()`. Signed-off-by: Chen Zhang <tgfbeta@me.com> Message-Id: <087F1D9C-109D-41D1-BE2C-CE5D840C981B@me.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-15megasas: fix mapped frame sizePeter Lieven1-1/+1
the current value of 1024 bytes (16 * MFI_FRAME_SIZE) we map is not enough to hold the maximum number of scatter gather elements we advertise. We actually need a maximum of 2048 bytes. This is 128 max sg elements * 16 bytes (sizeof (union mfi_sgl)). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Lieven <pl@kamp.de> Message-Id: <20190404121015.28634-1-pl@kamp.de> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-15vl: Add missing descriptions to the VGA adapters listPhilippe Mathieu-Daudé1-0/+2
Some VGA adapters do not contain an helpful description, this can be confusing: $ qemu-system-arm -M virt -vga help none std standard VGA cirrus Cirrus VGA (default) vmware VMWare SVGA xenfb Add a description to the missing adapters: $ qemu-system-arm -M virt -vga help none no graphic card std standard VGA cirrus Cirrus VGA (default) vmware VMWare SVGA xenfb Xen paravirtualized framebuffer Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Based-on: <20190412152713.16018-1-marcandre.lureau@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Message-Id: <20190412163706.3878-1-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-15Declare -realtime as deprecatedThomas Huth2-0/+7
The old -realtime mlock=on|off parameter does exactly the same as the new -overcommit mem-lock=on|off parameter. Additionally, "-realtime" does not activate any additional "realtime" capabilities as the name might indicate. We should avoid to confuse the users this way, so let's deprecate the old -realtime option. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190411175345.19414-1-thuth@redhat.com>
2019-05-15roms: assert if max rom size is less than the used sizeIgor Mammedov1-0/+1
It would ensure that we would notice attempt to write beyond the allocated buffer. In case of MemoryRegion backed ROM it's the host buffer and the guest RAM otherwise. assert can be triggered with: dd if=/dev/zero of=/tmp/blob bs=63k count=1 qemu-system-x86_64 `for i in {1..33}; do echo -n " -acpitable /tmp/blob"; done` Fixes: (a1666142db acpi-build: make ROMs RAM blocks resizeable) Reported-by: Wei Yang <richardw.yang@linux.intel.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1554982098-336210-1-git-send-email-imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-15hw/input: Add a CONFIG_PS2 switch for the ps2.c fileThomas Huth2-1/+6
ps2.c only needs to be compiled if we are building pckbd.c or pl050.c. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190411182240.5957-1-thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-05-14Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190513' into stagingPeter Maydell36-473/+2020
Improve code generation for vector duplication. Add vector expansions for shifts by non-constant scalar. Add vector expansions for shifts by vector. Add integer and vector expansions for absolute value. Several patches in preparation for Altivec. Bug fix for tcg/aarch64 vs min/max. # gpg: Signature made Tue 14 May 2019 00:58:02 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190513: (31 commits) tcg/aarch64: Do not advertise minmax for MO_64 target/xtensa: Use tcg_gen_abs_i32 target/tricore: Use tcg_gen_abs_tl target/s390x: Use tcg_gen_abs_i64 target/ppc: Use tcg_gen_abs_tl target/ppc: Use tcg_gen_abs_i32 target/cris: Use tcg_gen_abs_tl target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs tcg/aarch64: Support vector absolute value tcg/i386: Support vector absolute value tcg: Add support for vector absolute value tcg: Add support for integer absolute value tcg/i386: Support vector scalar shift opcodes tcg: Add gvec expanders for vector shift by scalar tcg/aarch64: Support vector variable shift opcodes tcg/i386: Support vector variable shift opcodes tcg: Add gvec expanders for variable shift tcg: Add INDEX_op_dupm_vec tcg/aarch64: Implement tcg_out_dupm_vec tcg/i386: Implement tcg_out_dupm_vec ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-13tcg/aarch64: Do not advertise minmax for MO_64Richard Henderson1-4/+4
The min/max instructions are not available for 64-bit elements. Fixes: 93f332a50371 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/xtensa: Use tcg_gen_abs_i32Richard Henderson1-8/+1
Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/tricore: Use tcg_gen_abs_tlPhilippe Mathieu-Daudé1-22/+5
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190423102145.14812-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/s390x: Use tcg_gen_abs_i64Richard Henderson1-7/+1
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/ppc: Use tcg_gen_abs_tlRichard Henderson1-44/+24
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/ppc: Use tcg_gen_abs_i32Philippe Mathieu-Daudé1-13/+1
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190423102145.14812-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/cris: Use tcg_gen_abs_tlRichard Henderson1-8/+1
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_absRichard Henderson4-51/+8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/aarch64: Support vector absolute valueRichard Henderson2-1/+7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Support vector absolute valueRichard Henderson2-1/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add support for vector absolute valueRichard Henderson11-0/+167
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add support for integer absolute valueRichard Henderson3-10/+25
Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Support vector scalar shift opcodesRichard Henderson2-1/+36
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add gvec expanders for vector shift by scalarRichard Henderson4-0/+279
Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Use a private structure for do_gvec_shifts.
2019-05-13tcg/aarch64: Support vector variable shift opcodesRichard Henderson3-1/+45
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Support vector variable shift opcodesRichard Henderson2-1/+36
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add gvec expanders for variable shiftRichard Henderson6-0/+384
The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add INDEX_op_dupm_vecRichard Henderson7-41/+70
Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Note that officially tcg_out_dupm_vec is allowed to fail. If it did, we could fix this up relatively easily: VECE == 32/64: Load the value into a vector register, then dup. Both of these must work. VECE == 8/16: If the value happens to be at an offset such that an aligned load would place the desired value in the least significant end of the register, go ahead and load w/garbage in high bits. Load the value w/INDEX_op_ld{8,16}_i32. Attempt a move directly to vector reg, which may fail. Store the value into the backing store for OTS. Load the value into the vector reg w/TCG_TYPE_I32, which must work. Duplicate from the vector reg into itself, which must work. All of which is well and good, except that all supported hosts can support dupm for all vece, so all of the failure paths would be dead code and untestable. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/aarch64: Implement tcg_out_dupm_vecRichard Henderson1-2/+35
The LD1R instruction does all the work. Note that the only useful addressing mode is a base register with no offset. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/i386: Implement tcg_out_dupm_vecRichard Henderson1-14/+43
At the same time, improve tcg_out_dupi_vec wrt broadcast from the constant pool. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add tcg_out_dupm_vec to the backend interfaceRichard Henderson3-1/+31
Currently stubbed out in all backends that support vectors. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Manually expand INDEX_op_dup_vecRichard Henderson3-10/+118
This case is similar to INDEX_op_mov_* in that we need to do different things depending on the current location of the source. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Added some commentary to the tcg_reg_alloc_* functions.
2019-05-13tcg: Promote tcg_out_{dup,dupi}_vec to backend interfaceRichard Henderson3-3/+26
The i386 backend already has these functions, and the aarch64 backend could easily split out one. Nothing is done with these functions yet, but this will aid register allocation of INDEX_op_dup_vec in a later patch. Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Support cross-class moves without instruction supportRichard Henderson1-3/+28
PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Return bool success from tcg_out_movRichard Henderson10-16/+31
This patch merely changes the interface, aborting on all failures, of which there are currently none. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg/arm: Use tcg_out_mov_reg in tcg_out_movRichard Henderson1-1/+1
We have a function that takes an additional condition parameter over the standard backend interface. It already takes care of eliding no-op moves. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Assert fixed_reg is read-onlyRichard Henderson1-47/+40
The only fixed_reg is cpu_env, and it should not be modified during any TB. Therefore code that tries to special-case moves into a fixed_reg is dead. Remove it. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Specify optional vector requirements with a listRichard Henderson7-162/+372
Replace the single opcode in .opc with a null-terminated array in .opt_opc. We still require that all opcodes be used with the same .vece. Validate the contents of this list with CONFIG_DEBUG_TCG. All tcg_gen_*_vec functions will check any list active during .fniv expansion. Swap the active list in and out as we expand other opcodes, or take control away from the front-end function. Convert all existing vector aware front ends. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expandedRichard Henderson1-16/+33
PowerPC Altivec does not support add and subtract of 64-bit elements. Prepare for that configuration by not assuming the operation is universally supported. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Do not recreate INDEX_op_neg_vec unless supportedRichard Henderson1-2/+6
Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec, so that we check the type and vece for the actual operation. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Implement tcg_gen_gvec_3i()David Hildenbrand2-0/+163
Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed for now. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190416185301.25344-2-david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13Merge remote-tracking branch ↵Peter Maydell14-173/+387
'remotes/huth-gitlab/tags/pull-request-2019-05-13' into staging Kconfig settings for the Arm machines # gpg: Signature made Mon 13 May 2019 09:19:43 BST # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2019-05-13: (29 commits) hw/arm: Remove hard-enablement of the remaining PCI devices hw/arm: Express dependencies of the musca machines with Kconfig hw/arm: Express dependencies of the xlnx-versal-virt machine with Kconfig hw/arm: Express dependencies of the ZynqMP zcu102 machine with Kconfig hw/arm: Express dependencies of the microbit / nrf51 machine with Kconfig hw/arm: Express dependencies of the remaining IMX boards with Kconfig hw/arm: Express dependencies of the MSF2 / EMCRAFT_SF2 machine with Kconfig hw/arm: Express dependencies of sabrelite with Kconfig hw/arm: Express dependencies of canon-a1100 with Kconfig hw/arm: Express dependencies of the raspi machines with Kconfig hw/arm: Express dependencies of the MPS2 boards with Kconfig hw/arm: Express dependencies of allwinner / cubieboard with Kconfig hw/arm: Express dependencies of netduino / stm32f2xx with Kconfig hw/arm: Express dependencies of the virt machine with Kconfig hw/arm: Express dependencies of the aspeed boards with Kconfig hw/arm: Express dependencies of collie with Kconfig hw/arm: Express dependencies of xilinx-zynq with Kconfig hw/arm: Express dependencies of the PXA2xx machines with Kconfig hw/arm: Express dependencies of realview, versatile and vexpress with Kconfig hw/arm: Express dependencies of stellaris with Kconfig ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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