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2023-10-22target/tricore: Use tcg_gen_*extract_tlRichard Henderson1-16/+4
The EXTR instructions can use the extract opcodes. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/rx: Use tcg_gen_ext_i32Richard Henderson1-8/+3
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/m68k: Use tcg_gen_ext_i32Richard Henderson1-20/+3
We still need to check OS_{BYTE,WORD,LONG}, because m68k includes floating point in OS_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/i386: Use tcg_gen_ext_tlRichard Henderson1-25/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/arm: Use tcg_gen_ext_i64Richard Henderson1-35/+2
The ext_and_shift_reg helper does this plus a shift. The non-zero check for shift count is duplicate to the one done within tcg_gen_shli_i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Define MO_TLPaolo Bonzini1-0/+2
This will also come in handy later for "less than" comparisons. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <03ba02fd-fade-4409-be16-2f81a5690b4c@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Export tcg_gen_ext_{i32,i64,tl}Richard Henderson3-4/+14
The two concrete type functions already existed, merely needing a bit of hardening to invalid inputs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: add negsetcondiPaolo Bonzini3-0/+18
This can be useful to write a shift bit extraction that does not depend on TARGET_LONG_BITS. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231019104648.389942-15-pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/i386: Use i128 for 128 and 256-bit loads and storesRichard Henderson1-34/+29
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Add tcg_gen_{ld,st}_i128Richard Henderson2-0/+25
Do not require the translators to jump through concat and extract of i64 in order to move values to and from env. Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Optimize past conditional branchesRichard Henderson1-3/+5
We already register allocate through extended basic blocks, optimize through extended basic blocks as well. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Use constant zero when expanding with divu2Richard Henderson1-8/+8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: drop unused tcg_temp_free defineMike Frysinger1-2/+0
Use of the API was removed a while back, but the define wasn't. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231015010046.16020-1-vapier@gentoo.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/s390x: Use tcg_use_softmmuRichard Henderson1-80/+77
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/riscv: Use tcg_use_softmmuRichard Henderson1-87/+90
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zeroRichard Henderson1-2/+4
Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the JIT") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use tcg_use_softmmuRichard Henderson1-127/+129
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/mips: Use tcg_use_softmmuRichard Henderson1-110/+105
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/loongarch64: Use tcg_use_softmmuRichard Henderson1-65/+61
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/i386: Use tcg_use_softmmuRichard Henderson1-101/+99
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/aarch64: Use tcg_use_softmmuRichard Henderson1-88/+87
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/arm: Use tcg_use_softmmuRichard Henderson1-109/+100
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Provide guest_base fallback for system modeRichard Henderson1-0/+4
Provide a define to allow !tcg_use_softmmu code paths to compile in system mode, but require elimination. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Introduce tcg_use_softmmuRichard Henderson3-12/+19
Begin disconnecting CONFIG_SOFTMMU from !CONFIG_USER_ONLY. Introduce a variable which can be set at startup to select one method or another for user-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Disable TCG_REG_TB for Power9/Power10Richard Henderson1-1/+1
This appears to slightly improve performance on power9/10. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PLD in tcg_out_goto_tbRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use prefixed instructions in tcg_out_dupi_vecRichard Henderson1-0/+9
The prefixed instructions have a pc-relative form to use here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PLD in tcg_out_movi for constant poolRichard Henderson1-0/+24
The prefixed instruction has a pc-relative form to use here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use prefixed instructions in tcg_out_mem_longRichard Henderson1-0/+66
When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PADDI in tcg_out_moviRichard Henderson1-0/+51
PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_goto_tbRichard Henderson1-2/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS for the constant poolRichard Henderson1-0/+12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_movi_intRichard Henderson1-0/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_tb_startRichard Henderson1-3/+22
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Reinterpret tb-relative to TB+4Richard Henderson1-5/+10
It saves one insn to load the address of TB+4 instead of TB. Adjust all of the indexing to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TBJordan Niethe1-31/+17
Direct branch patching was disabled when using TCG_REG_TB in commit 736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation"). The issue with direct branch patching with TCG_REG_TB is the lack of synchronization between the new TCG_REG_TB being established and the direct branch being patched in. If each translation block is responsible for establishing its own TCG_REG_TB then there can be no synchronization issue. Make each translation block begin by setting up its own TCG_REG_TB. Use the preferred 'bcl 20,31,$+4' sequence. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> [rth: Split out tcg_out_tb_start, power9 addpcis] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Untabify tcg-target.c.incRichard Henderson1-3/+3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-20Merge tag 'migration-20231020-pull-request' of ↵Stefan Hajnoczi44-195/+341
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request (20231020) In this pull request: - disable analyze-migration on s390x (thomas) - Fix parse_ramblock() (peter) - start merging live update (steve) - migration-test support for using several binaries (fabiano) - multifd cleanups (fabiano) CI: https://gitlab.com/juan.quintela/qemu/-/pipelines/1042492801 Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmUyJMsACgkQ9IfvGFhy # 1yP0AQ/9ELr6VJ0crqzfGm2dy2emnZMaQhDtzR4Kk4ciZF6U+GiATdGN9hK499mP # 6WzRIjtSzwD8YZvhLfegxIVTGcEttaM93uXFPznWrk7gwny6QTvuA4qtcRYejTSl # wE4GQQOsSrukVCUlqcZtY/t2aphVWQzlx8RRJE3XGaodT1gNLMjd+xp34NbbOoR3 # 32ixpSPUCOGvCd7hb+HG7pEzk+905Pn2URvbdiP71uqhgJZdjMAv8ehSGD3kufdg # FMrZyIEq7Eguk2bO1+7ZiVuIafXXRloIVqi1ENmjIyNDa/Rlv2CA85u0CfgeP6qY # Ttj+MZaz8PIhf97IJEILFn+NDXYgsGqEFl//uNbLuTeCpmr9NPhBzLw8CvCefPrR # rwBs3J+QbDHWX9EYjk6QZ9QfYJy/DXkl0KfdNtQy9Wf+0o1mHDn5/y3s782T24aJ # lGo0ph4VJLBNOx58rpgmoO5prRIjqzF5w4j8pCSeGUC4Bcub5af4TufYrwaf+cps # iIbNFx79dLXBlfkKIn7i9RLpz7641Fs/iTQ/MZh1eyvX++UDXAPWnbd4GDYOEewA # U3WKsTs/ipIbY8nqaO4j1VMzADPUfetBXznBw60xsZcfjynFJsPV6/F/0OpUupdv # qPEY4LZ2uwP4K7AlzrUzUn2f3BKrspL0ObX0qTn0WJ8WX5Jp/YA= # =m+uB # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 23:57:15 PDT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20231020-pull-request' of https://gitlab.com/juan.quintela/qemu: tests/qtest: Don't print messages from query instances tests/qtest/migration: Allow user to specify a machine type tests/qtest/migration: Support more than one QEMU binary tests/qtest/migration: Set q35 as the default machine for x86_86 tests/qtest/migration: Specify the geometry of the bootsector tests/qtest/migration: Define a machine for all architectures tests/qtest/migration: Introduce find_common_machine_version tests/qtest: Introduce qtest_resolve_machine_alias tests/qtest: Introduce qtest_has_machine_with_env tests/qtest: Allow qtest_get_machines to use an alternate QEMU binary tests/qtest: Introduce qtest_init_with_env tests/qtest: Allow qtest_qemu_binary to use a custom environment variable migration/multifd: Stop checking p->quit in multifd_send_thread migration: simplify notifiers migration: Fix parse_ramblock() on overwritten retvals migration: simplify blockers tests/qtest/migration-test: Disable the analyze-migration.py test on s390x Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20Merge tag 'pull-request-2023-10-20' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi35-125/+2285
staging * s390x CPU topology support * Simplify the KVM register synchronization code * Disable the analyze-migration.py test on s390x # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmUyDYMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUlgBAAkF3dvW0vMcb653sCI5vt2GHIvQQtc2Rw # ghRRcTBZ7wyVxKHtqohCh7/byzDW5YEuCWUyLsc2oIz/84pc00VR/5Ng1EAxLAfe # mvzzjr4jX96SmoO0DbJpqJQXaUPNYdmoshbRL0I3wkIfGtkvGRM8zHZuYINOg0hw # bH6gWZ2QL/NFjXh0uAOaJB1+hRtPWvHD2rnVt0g9U9W5QhRxGJqti5YEaLBH7hh5 # RydsquRZ/E6uFw4pMjjvCxDaswPwejddrP2YeR5Fd5Zo+Kzp53r9Hf/eJwlZ8yFL # 5f1dRb19NZYpW1hZuJVOP8tkPydYxAM85vkUunI7Qg4gez5KI0Nz6hQozw6ufMlQ # r8L17fwQMsCrwcRypImYNXyyrtHlNH5Y8FjqTct8aK64Bw3e7Qqi7d3ybFAuYZ+D # k2EJ8Rlwhbg69h+Q+ucHx4NkYu9+2MFS6G7w5EcM6xl3WHSwUxh9orlEMsIkyHS3 # OMFMTr1jjfFdEN6EafhPwFE/xKglFF2Fe3u6NoR+5pkv3UA5Z87giitxoekYecpH # J96P3anORpWW75qvOF+nccqrd7OrUL1/yYdOyJh5Tkm0oCIeQ9E5extVf3Gne3E/ # yWzr00GJRiHFO2qbGStgKHTQLItgQpccwNpSzEdgHCqwLbXl6e3Hoq42VIFOlbN/ # ZtgpyUkuYyQ= # =xDb+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 22:17:55 PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-10-20' of https://gitlab.com/thuth/qemu: (24 commits) tests/qtest/migration-test: Disable the analyze-migration.py test on s390x target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code target/s390x/kvm: Turn KVM_CAP_SYNC_REGS into a hard requirement tests/avocado: s390x cpu topology bad move tests/avocado: s390x cpu topology dedicated errors tests/avocado: s390x cpu topology test socket full tests/avocado: s390x cpu topology test dedicated CPU tests/avocado: s390x cpu topology entitlement tests tests/avocado: s390x cpu topology polarization tests/avocado: s390x cpu topology core docs/s390x/cpu topology: document s390x cpu topology qapi/s390x/cpu topology: add query-s390x-cpu-polarization command qapi/s390x/cpu topology: CPU_POLARIZATION_CHANGE QAPI event machine: adding s390 topology to info hotpluggable-cpus machine: adding s390 topology to query-cpu-fast qapi/s390x/cpu topology: set-cpu-topology qmp command target/s390x/cpu topology: activate CPU topology s390x/cpu topology: interception of PTF instruction s390x/cpu topology: resetting the Topology-Change-Report s390x/sclp: reporting the maximum nested topology entries ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into ↵Stefan Hajnoczi14-81/+1300
staging target/hppa: Add emulation of a C3700 HP-PARISC workstation This series adds a new PA-RISC machine emulation for the HP-PARISC C3700 workstation. The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to the existing emulation of a B160L workstation which is a 32-bit only machine and where it's Dino PCI controller isn't 64-bit capable. With the HP C3700 machine emulation (together with the emulated Astro Memory controller and the Elroy PCI bridge) it's now possible to enhance the hppa CPU emulation to support the 64-bit instruction set in upcoming patches. Helge v4 changes: - Fix testsuite error in astro by adding a realize() implementation v3 changes: based on feedback from BALATON Zoltan <balaton@eik.bme.hu>: - apply paches in different order to bring them logically closer to each other - update comments in lasips2 - rephrased title and commit message of MAINTAINERS patch v2 changes: suggestions by BALATON Zoltan <balaton@eik.bme.hu>: - merged pci_ids and tulip patch - dropped comments in lasips2 - mention additional cleanups in patch "Require at least SeaBIOS-hppa version 10" suggestions by Philippe Mathieu-Daudé <philmd@linaro.org>: - dropped static pci_bus variable # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZTGzDQAKCRD3ErUQojoP # X9psAP0cHfTuJuXMiBWhrJhfp5VV0TURvaNXjCGyK8qvfbK+zgEArg3nvKhZPvnu # jVSq6b/Ppf3eCAZIYSVIsfLITbElTQ4= # =Esj+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 15:51:57 PDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa: hw/hppa: Add new HP C3700 machine hw/hppa: Split out machine creation hw/hppa: Provide RTC and DebugOutputPort on CPU #0 hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg MAINTAINERS: Update HP-PARISC entries pci-host: Wire up new Astro/Elroy PCI bridge hw/pci-host: Add Astro system bus adapter found on PA-RISC machines lasips2: LASI PS/2 devices are not user-createable pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip hw/hppa: Require at least SeaBIOS-hppa version 10 target/hppa: Update to SeaBIOS-hppa version 10 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20Merge tag 'hw-misc-20231019' of https://github.com/philmd/qemu into stagingStefan Hajnoczi72-273/+232
Misc hardware patch queue - MAINTAINERS updates (Zoltan, Thomas) - Fix cutils::get_relocated_path on Windows host (Akihiko) - Housekeeping in Memory APIs (Marc-André) - SDHCI fix for SDMA transfer (Lu, Jianxian) - Various QOM/QDev/SysBus cleanups (Philippe) - Constify QemuInputHandler structure (Philippe) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmUxnKAACgkQ4+MsLN6t # wN6UPw//abFZgckpxDYow4UfMu7esvkhICBvXjqDEdX2U/PBYmef049T5RVW8oDm # NWnxRA9XydzTeToH56tU2tjXbjWKF5LcJVwrCNl6XFRdLYaR3hzejm96hX99C89J # PB/2ineeAwidBoFfgjkvz0FLRr1ePaN74YXedPSHzywG+0dAOvpNUubbsggn3i5k # 1wTlgfDvL6iz8NMEOSBp6cv5D4Ix0WshkqlCac0gQ74lYSM1tk/EeRiSy2IHWQQB # 4FHd9Wo9brzLQCbhbb4FapTK0POScy0LebzRWOWfLtyWS+FRBC3kxO126I67CwMb # XRS4YgBqC3U7IGsbzV+fWP01pVeJRzZ1vrv4vdiIYvqTdgNlmFbGjJUwEmPmrokt # q5UreAjMUNLMEXiY6QHFq3N5I+UMY1jslcf7K/ZwDqSlqaquAe+gbnQOAMXDYgb6 # GWsBrLM2WA5E9ObbxsHdxgZqW1NxcWJpSBvjNiOV9t/jqoqpxYwHr5HAvR1xUwm+ # qRKRayRpLlX/Yad4NlvJaH5jvsMrI4bnxTYWVevLvYzc07Xo3dVxW1c+P+WCdjfM # O3bLAvwO7Mw7GRiSNpU8zTbRJu/dS4NWDWZ24u606Cy7qD/qouz89JjkKVYYSFkX # vNp7YOenPf4K6pak/lC3NOLIPlYmnnCLv3RCiaO6wHi4bk1yEBU= # =9dZy # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 14:16:16 PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20231019' of https://github.com/philmd/qemu: (46 commits) ui/input: Constify QemuInputHandler structure hw/net: Declare link using static DEFINE_PROP_LINK() macro hw/dma: Declare link using static DEFINE_PROP_LINK() macro hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros hw/virtio/virtio-pmem: Replace impossible check by assertion hw/s390x/css-bridge: Realize sysbus device before accessing it hw/isa: Realize ISA bridge device before accessing it hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it hw/acpi: Realize ACPI_GED sysbus device before accessing it hw/pci-host/bonito: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region hw/audio/pcspk: Inline pcspk_init() hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Move sysbus_init_mmio() calls around hw/ppc/pnv: Do not use SysBus API to map local MMIO region ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20Merge tag 'pull-qapi-2023-10-19' of https://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi4-5/+11
QAPI patches patches for 2023-10-19 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmUxNoISHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTZ6EP+wdGaoxiodAAOxRWQVAt0mViFGNclRmD # 8vHNpTfJMdimPOjN+3yd6IQgyrrR6ocr5aDa71GH/eKU4sitaN1DB5cqB7nPaB57 # 7pIY3fTR3GeTM8M3SyGvqIVs7C5slDb+RAMMraajoj7MdfSWRsiHKgRslFnIvG3y # g9Y40vxqell8YRGuduxd+QcoHDOXVzJCcZ8BXu2tFYbkFet35XEtG/47Xqe9+ah9 # uav4KOGt6dAb2Zp1i7m0Fxdydmvgi3UfYMfDXm2jWLc7dlaSJnOvGfrDFpvxn09b # t9qaVo7BXHN9BdgZN/JC/tbwd7SUC5Zf6KjuV/+BzV6M60hAulrF5Ig3Ot+1+4SE # UV3Xk/OWyzUv2Z6u/DHiMuUUIBlX2/Coug75smXTH1Z3kOXvGgeQ7XZQJbIH9tZu # R+3maW4yDoPm5Y9GS61v+PtY3696DS3SBKYz+FuYFFfKBiq1L1Z3kNPh00x7WFxy # s5BNJ3shD20aV4Psw0bYFgvI/uL6rAbGvbtX24AWehYxLCw2MeBFoDsLFw4hTX2J # Q3F4SRkUF03lZK8NIcg6glb2IKMxn6+XtziNsGD1uLG8p85y3CyFtC4rf+TAQGtK # aLADaAYluoSoOC+Gv5oJJeCwMXpFnsKnA2aYZIVxRbwaj25PK3vg7WxyJpSgqW10 # AKpBhmiNJKtK # =KDfs # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 07:00:34 PDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2023-10-19' of https://repo.or.cz/qemu/armbru: qapi: provide a friendly string representation of QAPI classes qapi: Belatedly update CompatPolicy documentation for unstable qapi: re-establish linting baseline Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20Merge tag 'pull-target-arm-20231019' of ↵Stefan Hajnoczi33-359/+368
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder * hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot' * xlnx devices: remove deprecated device reset * xlnx-bbram: hw/nvram: Use dot in device type name * elf2dmp: fix coverity issues * elf2dmp: convert to g_malloc, g_new and g_free * target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0 * hw/arm: refactor virt PPI logic * arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg * target/arm: Permit T32 LDM with single register * smmuv3: Advertise SMMUv3.1-XNX * target/arm: Implement FEAT_HPMN0 * Remove some unnecessary include lines * target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL * hw/timer/npcm7xx_timer: Prevent timer from counting down past zero # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmUxMF4ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oJND/4p64q0Wxq8x8yXCDUZAHME # lZe2liBPBkqZusGfK0O4CpClwGbM5+8tMeLaRgSOUgJ/WGFiLCGAKEKB0S7EiCa5 # 1bNvVn+a7cdDj7FdYf+Dvp5fNZZIus4w+CUlUaiRyDhIfYquz53J1RD1wN5+SQ/I # g6JQRp2gONeqGM5hT+0v2J/wGMmhuI5XO+PtQ1QNGoUnAA4QNof1thYjqdTJxzfz # V2CUSOKnAT/PDcUWoy8BVPDDE+wYTnjTO1j/ZsQvnNQm7r18OiMUn85teLq1JtB+ # T3vyVZ2f2gc8lAgkKy5n3NH5fmLVgbO0WXgpWLHNkcp+shZMM6J5J/u/P6B/wk95 # DMzQy4slu/UfWMvsaxq+OjejhAtbdiIOeNfF6dAMy2NAyZplEAjlP8dsFrqAdACL # 9m/DA4ODAV6OJ3E0zQ0dI4o6kr+/wbPVseLklqn3Ss0dndjU1K9XR0qpC8OruUJq # 4h6kl5q6V3BHAoELvBtAqb0yHYdqhLqznpO8HsrUEmU5eTjDaOyyI4HW+AY5GG1R # dtvrCLSiPe0EMartMMtezaB2GxQb9O7e+OI3XL2zVxb1F+QQ+vRZE3zVIdXm+Ev4 # oBztF1peZC3c8zurjr7/MxnDSnzynpkSR1zOY8+WJnAqpQ+C1YvdF6/Llwn7IMHw # ZHh6sGzQsaAu7u/DW9yY5w== # =WreO # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 06:34:22 PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20231019' of https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits) contrib/elf2dmp: Use g_malloc(), g_new() and g_free() hw/timer/npcm7xx_timer: Prevent timer from counting down past zero target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL target/arm/common-semi-target.h: Remove unnecessary boot.h include target/arm/kvm64.c: Remove unused include target/arm: Implement FEAT_HPMN0 hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature hw/arm/smmuv3: Sort ID register setting into field order hw/arm/smmuv3: Update ID register bit field definitions target/arm: Permit T32 LDM with single register arm/kvm: convert to kvm_get_one_reg arm/kvm: convert to kvm_set_one_reg hw/arm/sbsa-ref: use bsa.h for PPI definitions include/hw/arm: move BSA definitions to bsa.h {include/}hw/arm: refactor virt PPI logic target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0 elf2dmp: check array bounds in pdb_get_file_size elf2dmp: limit print length for sign_rsds xlnx-bbram: hw/nvram: Use dot in device type name xlnx-versal-efuse: hw/nvram: Remove deprecated device reset ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20tests/qtest: Don't print messages from query instancesFabiano Rosas1-1/+8
Now that we can query more than one binary, the "starting QEMU..." message can get a little noisy. Mute those messages unless we're running with --verbose. Only affects qtest_init() calls from within libqtest. The tests continue to output as usual. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20231018192741.25885-13-farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com>
2023-10-20tests/qtest/migration: Allow user to specify a machine typeFabiano Rosas3-2/+31
Accept the QTEST_QEMU_MACHINE_TYPE environment variable to take a machine type to use in the tests. The full machine type is recognized (e.g. pc-q35-8.2). Aliases (e.g. pc) are also allowed and resolve to the latest machine version for that alias, or, if using two QEMU binaries, to the latest common machine version between the two. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-12-farosas@suse.de>
2023-10-20tests/qtest/migration: Support more than one QEMU binaryFabiano Rosas1-4/+24
We have strict rules around migration compatibility between different QEMU versions but no test to validate the migration state between different binaries. Add infrastructure to allow running the migration tests with two different QEMU binaries as migration source and destination. The code now recognizes two new environment variables QTEST_QEMU_BINARY_SRC and QTEST_QEMU_BINARY_DST. In the absence of either of them, the test will use the QTEST_QEMU_BINARY variable. If both are missing then the tests are run with single binary as previously. The machine type is selected automatically as the latest machine type version that works with both binaries. Usage (only one of SRC|DST is allowed): QTEST_QEMU_BINARY_SRC=../build-8.2.0/qemu-system-x86_64 \ QTEST_QEMU_BINARY=../build-8.1.0/qemu-system-x86_64 \ ./tests/qtest/migration-test Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-11-farosas@suse.de>
2023-10-20tests/qtest/migration: Set q35 as the default machine for x86_86Fabiano Rosas1-1/+6
Change the x86_64 to use the q35 machines in tests from now on. Keep testing the pc macine on 32bit. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-10-farosas@suse.de>
2023-10-20tests/qtest/migration: Specify the geometry of the bootsectorFabiano Rosas1-1/+3
We're about to enable the x86_64 tests to run with the q35 machine, but that machine does not work with the program we use to dirty the memory for the tests. The issue is that QEMU needs to guess the geometry of the "disk" we give to it and the guessed geometry doesn't pass the sanity checks done by SeaBIOS. This causes SeaBIOS to interpret the geometry as if needing a translation from LBA to CHS and SeaBIOS ends up miscomputing the number of cylinders and aborting due to that. The reason things work with the "pc" machine is that is uses ATA instead of AHCI like q35 and SeaBIOS has an exception for ATA that ends up skipping the sanity checks and ignoring translation altogether. Workaround this situation by specifying a geometry in the command line. Signed-off-by: Fabiano Rosas <farosas@suse.de> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-9-farosas@suse.de>
2023-10-20tests/qtest/migration: Define a machine for all architecturesFabiano Rosas1-3/+13
Stop relying on defaults and select a machine explicitly for every architecture. This is a prerequisite for being able to select machine types for migration using different QEMU binaries for source and destination. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-8-farosas@suse.de>
2023-10-20tests/qtest/migration: Introduce find_common_machine_versionFabiano Rosas2-0/+28
When using two different QEMU binaries for migration testing, we'll need to find what is the machine version that will work with both binaries. Add a helper for that. Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231018192741.25885-7-farosas@suse.de>
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