aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson22-89/+13
2021-09-21Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson34-669/+1844
2021-09-21Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...Peter Maydell24-168/+1825
2021-09-21target/arm: Optimize MVE 1op-immediate insnsPeter Maydell1-5/+21
2021-09-21target/arm: Optimize MVE VSLI and VSRIPeter Maydell1-2/+2
2021-09-21target/arm: Optimize MVE VSHLL and VMOVLPeter Maydell1-8/+59
2021-09-21target/arm: Optimize MVE VSHL, VSHR immediate formsPeter Maydell1-20/+63
2021-09-21target/arm: Optimize MVE VMVNPeter Maydell1-1/+1
2021-09-21target/arm: Optimize MVE VDUPPeter Maydell1-4/+8
2021-09-21target/arm: Optimize MVE VNEG, VABSPeter Maydell1-10/+22
2021-09-21target/arm: Optimize MVE arithmetic opsPeter Maydell1-9/+11
2021-09-21target/arm: Optimize MVE logic opsPeter Maydell1-15/+36
2021-09-21target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell7-9/+92
2021-09-21target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migrationPeter Maydell1-0/+13
2021-09-21target/arm: Avoid goto_tb if we're trying to exit to the main loopPeter Maydell1-1/+33
2021-09-21hvf: arm: Add rudimentary PMC supportAlexander Graf1-0/+179
2021-09-21arm: Add Hypervisor.framework build targetAlexander Graf3-0/+12
2021-09-21hvf: arm: Implement PSCI handlingAlexander Graf3-7/+139
2021-09-21hvf: arm: Implement -cpu hostPeter Maydell5-6/+124
2021-09-21arm/hvf: Add a WFI handlerPeter Collingbourne3-3/+82
2021-09-21Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' int...Peter Maydell15-76/+529
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2-16/+16
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang1-1/+2
2021-09-21docs/system/riscv: sifive_u: Update U-Boot instructionsBin Meng1-23/+26
2021-09-21hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang1-6/+6
2021-09-21hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan1-6/+10
2021-09-21hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang1-0/+9
2021-09-21hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang1-0/+19
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel3-1/+124
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel8-156/+339
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel11-15/+15
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis4-2/+69
2021-09-21hw/timer: Add SiFive PWM supportAlistair Francis5-0/+540
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis3-5/+17
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis7-12/+33
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis3-11/+16
2021-09-21hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis2-20/+50
2021-09-21target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis1-0/+30
2021-09-21target/riscv: Fix satp writeLIU Zhiwei1-1/+1
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis2-2/+3
2021-09-20Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...Peter Maydell2-8/+33
2021-09-20Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' ...Peter Maydell2-2/+8
2021-09-20hvf: Add Apple Silicon supportAlexander Graf7-1/+834
2021-09-20hvf: Introduce hvf_arch_init() callbackAlexander Graf3-1/+8
2021-09-20hvf: Add execute to dirty log permission bitmapAlexander Graf1-2/+2
2021-09-20arm: Move PMC register definitions to internals.hAlexander Graf2-44/+44
2021-09-20hw/intc: Set GIC maintenance interrupt level to only 0 or 1Shashi Mallela1-2/+3
2021-09-20target/arm: Consolidate ifdef blocks in resetPeter Maydell1-12/+10