| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-09-05 | target/arm: Convert RFE and SRS | Richard Henderson | 3 | -89/+75 |
| 2019-09-05 | target/arm: Convert SVC | Richard Henderson | 2 | -6/+17 |
| 2019-09-05 | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson | 4 | -109/+125 |
| 2019-09-05 | target/arm: Diagnose base == pc for LDM/STM | Richard Henderson | 1 | -2/+3 |
| 2019-09-05 | target/arm: Diagnose too few registers in list for LDM/STM | Richard Henderson | 1 | -8/+18 |
| 2019-09-05 | target/arm: Diagnose writeback register in list for LDM for v7 | Richard Henderson | 1 | -0/+9 |
| 2019-09-05 | target/arm: Convert LDM, STM | Richard Henderson | 3 | -198/+246 |
| 2019-09-05 | target/arm: Convert MOVW, MOVT | Richard Henderson | 3 | -56/+48 |
| 2019-09-05 | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson | 3 | -272/+258 |
| 2019-09-05 | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson | 3 | -310/+300 |
| 2019-09-05 | target/arm: Convert Parallel addition and subtraction | Richard Henderson | 3 | -117/+200 |
| 2019-09-05 | target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF | Richard Henderson | 3 | -96/+144 |
| 2019-09-05 | target/arm: Diagnose UNPREDICTABLE ldrex/strex cases | Richard Henderson | 1 | -2/+38 |
| 2019-09-05 | target/arm: Convert Synchronization primitives | Richard Henderson | 3 | -258/+412 |
| 2019-09-05 | target/arm: Convert load/store (register, immediate, literal) | Richard Henderson | 3 | -443/+623 |
| 2019-09-05 | target/arm: Convert T32 ADDW/SUBW | Richard Henderson | 3 | -11/+33 |
| 2019-09-05 | target/arm: Convert the rest of A32 Miscelaneous instructions | Richard Henderson | 3 | -82/+58 |
| 2019-09-05 | target/arm: Convert ERET | Richard Henderson | 3 | -39/+33 |
| 2019-09-05 | target/arm: Convert CLZ | Richard Henderson | 3 | -16/+24 |
| 2019-09-05 | target/arm: Convert BX, BXJ, BLX (register) | Richard Henderson | 3 | -40/+47 |
| 2019-09-05 | target/arm: Convert Cyclic Redundancy Check | Richard Henderson | 3 | -65/+72 |
| 2019-09-05 | target/arm: Convert MRS/MSR (banked, register) | Richard Henderson | 3 | -141/+145 |
| 2019-09-05 | target/arm: Convert MSR (immediate) and hints | Richard Henderson | 3 | -18/+84 |
| 2019-09-05 | target/arm: Simplify op_smlawx for SMLAW* | Richard Henderson | 1 | -8/+8 |
| 2019-09-05 | target/arm: Simplify op_smlaxxx for SMLAL* | Richard Henderson | 1 | -7/+8 |
| 2019-09-05 | target/arm: Convert Halfword multiply and multiply accumulate | Richard Henderson | 3 | -97/+170 |
| 2019-09-05 | target/arm: Convert Saturating addition and subtraction | Richard Henderson | 3 | -27/+67 |
| 2019-09-05 | target/arm: Simplify UMAAL | Richard Henderson | 1 | -22/+12 |
| 2019-09-05 | target/arm: Convert multiply and multiply accumulate | Richard Henderson | 3 | -107/+177 |
| 2019-09-05 | target/arm: Convert Data Processing (immediate) | Richard Henderson | 3 | -334/+186 |
| 2019-09-05 | target/arm: Convert Data Processing (reg-shifted-reg) | Richard Henderson | 3 | -20/+87 |
| 2019-09-05 | target/arm: Convert Data Processing (register) | Richard Henderson | 3 | -36/+271 |
| 2019-09-05 | target/arm: Add stubs for aa32 decodetree | Richard Henderson | 5 | -1/+114 |
| 2019-09-05 | target/arm: Use store_reg_from_load in thumb2 code | Richard Henderson | 1 | -9/+3 |
| 2019-09-05 | Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into staging | Peter Maydell | 10 | -224/+770 |
| 2019-09-04 | target/openrisc: Update cpu "any" to v1.3 | Richard Henderson | 1 | -1/+1 |
| 2019-09-04 | target/openrisc: Implement l.adrp | Richard Henderson | 3 | -0/+16 |
| 2019-09-04 | target/openrisc: Implement move to/from FPCSR | Richard Henderson | 5 | -5/+38 |
| 2019-09-04 | target/openrisc: Implement unordered fp comparisons | Richard Henderson | 5 | -0/+145 |
| 2019-09-04 | target/openrisc: Add support for ORFPX64A32 | Richard Henderson | 7 | -4/+333 |
| 2019-09-04 | target/openrisc: Check CPUCFG_OF32S for float insns | Richard Henderson | 2 | -50/+36 |
| 2019-09-04 | target/openrisc: Fix lf.ftoi.s | Richard Henderson | 1 | -1/+1 |
| 2019-09-04 | target/openrisc: Add VR2 and AVR special processor registers | Richard Henderson | 3 | -6/+19 |
| 2019-09-04 | target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init | Richard Henderson | 3 | -13/+22 |
| 2019-09-04 | target/openrisc: Make VR and PPC read-only | Richard Henderson | 2 | -12/+1 |
| 2019-09-04 | target/openrisc: Cache R0 in DisasContext | Richard Henderson | 1 | -7/+12 |
| 2019-09-04 | target/openrisc: Replace cpu register array with a function | Richard Henderson | 1 | -97/+116 |
| 2019-09-04 | target/openrisc: Add DisasContext parameter to check_r0_write | Richard Henderson | 1 | -47/+49 |
| 2019-09-04 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging | Peter Maydell | 10 | -24/+122 |
| 2019-09-04 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190903' into staging | Peter Maydell | 57 | -867/+920 |
