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2024-01-29linux-user: Allow gdbstub to ignore page protectionIlya Leoshkevich1-15/+63
gdbserver ignores page protection by virtue of using /proc/$pid/mem. Teach qemu gdbstub to do this too. This will not work if /proc is not mounted; accept this limitation. One alternative is to temporarily grant the missing PROT_* bit, but this is inherently racy. Another alternative is self-debugging with ptrace(POKE), which will break if QEMU itself is being debugged - a much more severe limitation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240129093410.3151-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/hw/core: Remove i386 conditional on fake_user_interruptAnton Johansson1-3/+2
Always include fake_user_interrupt in user-only build, despite only being used for i386. This will enable cpu-exec.c to be compiled only once. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-ID: <20240119144024.14289-18-anjo@rev.ng> [rth: Split out of a larger patch; remove TARGET_I386 conditional.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/hw/core: Move do_interrupt in TCGCPUOpsAnton Johansson1-5/+2
The ifdef out of which it is moved is not quite right: do_interrupt is only needed for system mode. Move it to the top of a different ifdef block, which preserves its position within the structure for that case. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-18-anjo@rev.ng> [rth: Split from a larger patch and simplified.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/exec: Move cpu_*()/cpu_env() to common headerAnton Johansson2-25/+26
Functions are target independent. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-17-anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/exec: Move PAGE_* macros to common headerAnton Johansson2-24/+30
These don't vary across targets and are used in soon-to-be common code (cputlb.c). Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-15-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/exec: typedef abi_ptr to vaddrAnton Johansson1-2/+2
Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-11-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/exec: Use vaddr in DisasContextBase for virtual addressesAnton Johansson5-12/+14
Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated DisasContextBase fields. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-10-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson22-22/+22
Makes gen_intermediate_code() signature target agnostic so the function can be called from accel/tcg/translate-all.c without target specifics. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-9-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29hw/core: Include vaddr.h from cpu.hAnton Johansson1-1/+1
cpu-common.h is only needed for vaddr Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-8-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/exec: Move vaddr defines to separate fileAnton Johansson2-12/+19
Needed to work around circular includes. vaddr is currently defined in cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need cpu.h to know the size of the CPUState. [Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to sort out the circular inclusion.] Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-7-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [rth: Add include of vaddr.h into cpu-common.h] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29cpu-exec: simplify jump cache managementPaolo Bonzini2-46/+28
Unless I'm missing something egregious, the jmp cache is only every populated with a valid entry by the same thread that reads the cache. Therefore, the contents of any valid entry are always consistent and there is no need for any acquire/release magic. Indeed ->tb has to be accessed with atomics, because concurrent invalidations would otherwise cause data races. But ->pc is only ever accessed by one thread, and accesses to ->tb and ->pc within tb_lookup can never race with another tb_lookup. While the TranslationBlock (especially the flags) could be modified by a concurrent invalidation, store-release and load-acquire operations on the cache entry would not add any additional ordering beyond what you get from performing the accesses within a single thread. Because of this, there is really nothing to win in splitting the CF_PCREL and !CF_PCREL paths. It is easier to just always use the ->pc field in the jump cache. I noticed this while working on splitting commit 8ed558ec0cb ("accel/tcg: Introduce TARGET_TB_PCREL", 2022-10-04) into multiple pieces, for the sake of finding a more fine-grained bisection result for https://gitlab.com/qemu-project/qemu/-/issues/2092. It does not (and does not intend to) fix that issue; therefore it may make sense to not commit it until the root cause of issue #2092 is found. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240122153409.351959-1-pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-26Merge tag 'pull-target-arm-20240126' of ↵Peter Maydell73-261/+597
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix VNCR fault detection logic * Fix A64 scalar SQSHRN and SQRSHRN * Fix incorrect aa64_tidcp1 feature check * hw/arm/virt.c: Remove newline from error_report() string * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler() * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board * arm: various include header cleanups * cleanups to allow some files to be built only once * fsl-imx6ul: Add various missing unimplemented devices * docs/system/arm/virt.rst: Add note on CPU features off by default * hw/char/imx_serial: Implement receive FIFO and ageing timer * target/xtensa: fix OOB TLB entry access * bswap.h: Fix const_le64() macro * hw/arm: add PCIe to Freescale i.MX6 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWzwpsZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oTVD/4jM7ttKlXxtWsJ/cKDL5Im # uMmDECPrdK2qaNpONfV/YC3WadM6bSgB8OQd2YlI67DLgl3Hfaa+GnQsZhEgZ3lC # VECOTg5OKwwJY+Ac86t1GJa483wDEQ6NL08oLN94n9Ub/9G0S3oWpmE4bgof7PzW # rbLDDpKP+W5NfkqMfA5piV7N6mFHvg9wqFX//quqySIiu8NesKV9LmlP/FyNDU/s # 8ZeSqo/tq/IHr9IeYUtOoxVwYUOPuNKwD+vwy1taiXgjvVtq2URrCrlc4+KCWJsj # VUBSXdY2boqK31KFZ9NP9kJhIS5gmzgnK8YrHX6sgSbh+IybZUv+y/4eSO/LDYIi # r2VQF6oTtkmcIxUqAI6ZAehzZUIrB22QItUN8rg0slKBM8e/xHYaEBY8APKCLcvE # h59DLq1rPZG3Aie/h3/RjTfT2kI83PiE1mDGbhKf9G8UfXHEH8Eabd0g66UWfzlK # 67o7bwwzwXgoGk2hgMY/yobB3pF5YCly/a3aN/aLEj387y8sNaT1ASR9LETj7TC3 # xOhn5f8G6OFKMVI3K8Sco8ILP15LELprAW2keL4jn+4y3Hfq5yC984yOSnlM0wug # wWRvEr7U1ZiEbDaOvoa0beuYpeq1sm4OZ5yGJxGy3IuQ8pZpkHVTrBxw/NCNQnos # fK5czVTGqvvmPXgPsQQm1A== # =vYTy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Jan 2024 14:32:59 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240126' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: add PCIe to Freescale i.MX6 target/arm: Fix incorrect aa64_tidcp1 feature check bswap.h: Fix const_le64() macro target/arm: Fix A64 scalar SQSHRN and SQRSHRN hw/char/imx_serial: Implement receive FIFO and ageing timer docs/system/arm/virt.rst: Add note on CPU features off by default fsl-imx6ul: Add various missing unimplemented devices hw/arm: Build various units only once target/arm: Move GTimer definitions to new 'gtimer.h' header target/arm: Move e2h_access() helper around target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header target/arm: Expose M-profile register bank index definitions hw/misc/xlnx-versal-crl: Build it only once hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' hw/cpu/a9mpcore: Build it only once target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header target/arm: Create arm_cpu_mp_affinity target/arm: Rename arm_cpu_mp_affinity ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingPeter Maydell59-1028/+1022
Block layer patches - virtio-blk: Multiqueue fixes and cleanups - blklogwrites: Fixes for write_zeroes and superblock update races - commit/stream: Allow users to request only format driver names in backing file format - monitor: only run coroutine commands in qemu_aio_context - Some iotest fixes # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmWzpOwRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9ZNzg//W1+C7HxLft4Jc4O1BcOoOLlGCg4Esupt # z0/XLZ9+xVQUtjQ82pFzf9XaWQs8CuNT3FBUKi+ngdwZ0JBThIv0aGiMZBcAeQjD # qshPFgDM1lGL4ICIaT73/qfUzQgO3oruZj9F+ShBBzoasNWVoRzqqVDR3pinLwTp # D4TU+3A6LkdhlYGT60SYfRq/UKNmCA1s2wysdjqXxS6KOEURNF2VBnz0Nu76qrVb # 3P/a55GPiJIn+VVsdQ0J4vyyzn23m7I7WZOJ7Sjm1EfSJ6SvcDbhWsZTUonaV2rU # qZ3WI/jggqxXRV8F2AaA4suS/Cc8RkX2KfcN8fB6wDC2eI5USSatjh6xfw5xH9Ll # NRKUO4vFFR3Lf8wN9apg0Bwxqi0GOm9kvBJT5QqjQ16R1dvqBLqbZqcx6ZXqWFXe # /Iy243Tz19mWTFVUj0EgCKQpNz9F4SyXxV83HtSR1lJ5mhthnLxkvUOe7jsFPE4d # 1Z3uBNWnx2mKFkhlwocMTKayYqxPuKQ+YjqrRoplLW1GZoBeoalKRGf8/RHa6kQx # gh4cguihlb71AH1AO1QuYpiZt9G4RJR2RZlIoCPJY5TaKJedcxMVn8H+8/F0PnQd # gPysZf7hTU1xCUV6TClDd+f2fuvqZYwXdwHJ9iiohNkbFq4HFQUp4nk4/eEPGSe/ # uv8oE813E30= # =KQJl # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Jan 2024 12:26:20 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: iotests/277: Use iotests.sock_dir for socket creation iotests/iothreads-stream: Use the right TimeoutError tests/unit: Bump test-replication timeout to 60 seconds iotests/264: Use iotests.sock_dir for socket creation block/blklogwrites: Protect mutable driver state with a mutex. virtio-blk: always set ioeventfd during startup virtio-blk: tolerate failure to set BlockBackend AioContext virtio-blk: restart s->rq reqs in vq AioContexts virtio-blk: rename dataplane to ioeventfd virtio-blk: rename dataplane create/destroy functions virtio-blk: move dataplane code into virtio-blk.c monitor: only run coroutine commands in qemu_aio_context iotests: port 141 to Python for reliable QMP testing iotests: add filter_qmp_generated_node_ids() stream: Allow users to request only format driver names in backing file format commit: Allow users to request only format driver names in backing file format string-output-visitor: Fix (pseudo) struct handling block/blklogwrites: Fix a bug when logging "write zeroes" operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm: add PCIe to Freescale i.MX6Nikita Ostrenkov3-21/+50
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com> Message-id: 20240108140325.1291-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Fix incorrect aa64_tidcp1 feature checkPeter Maydell1-1/+1
A typo in the implementation of isar_feature_aa64_tidcp1() means we were checking the field in the wrong ID register, so we might have provided the feature on CPUs that don't have it and not provided it on CPUs that should have it. Correct this bug. Cc: qemu-stable@nongnu.org Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240123160333.958841-1-peter.maydell@linaro.org
2024-01-26bswap.h: Fix const_le64() macroPeter Maydell1-8/+8
The const_le64() macro introduced in commit 845d80a8c7b187 turns out to have a bug which means that on big-endian systems the compiler complains if the argument isn't already a 64-bit type. This hasn't caused a problem yet, because there are no in-tree uses, but it means it's not possible for anybody to add one without it failing CI. This example is from an attempted use of it with the argument '0', from the s390 CI runner's gcc: ../block/blklogwrites.c: In function ‘blk_log_writes_co_do_log’: ../include/qemu/bswap.h:148:36: error: left shift count >= width of type [-Werror=shift-count-overflow] 148 | ((((_x) & 0x00000000000000ffU) << 56) | \ | ^~ ../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’ 409 | .nr_entries = const_le64(0), | ^~~~~~~~~~ ../include/qemu/bswap.h:149:36: error: left shift count >= width of type [-Werror=shift-count-overflow] 149 | (((_x) & 0x000000000000ff00U) << 40) | \ | ^~ ../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’ 409 | .nr_entries = const_le64(0), | ^~~~~~~~~~ cc1: all warnings being treated as errors Fix this by making all the constants in the macro have the ULL suffix. This will cause them all to be 64-bit integers, which means the result of the logical & will also be an unsigned 64-bit type, even if the input to the macro is a smaller type, and so the shifts will be in range. Fixes: 845d80a8c7b187 ("qemu/bswap: Add const_le64()") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Message-id: 20240122173735.472951-1-peter.maydell@linaro.org
2024-01-26target/arm: Fix A64 scalar SQSHRN and SQRSHRNPeter Maydell1-1/+1
In commit 1b7bc9b5c8bf374dd we changed handle_vec_simd_sqshrn() so that instead of starting with a 0 value and depositing in each new element from the narrowing operation, it instead started with the raw result of the narrowing operation of the first element. This is fine in the vector case, because the deposit operations for the second and subsequent elements will always overwrite any higher bits that might have been in the first element's result value in tcg_rd. However in the scalar case we only go through this loop once. The effect is that for a signed narrowing operation, if the result is negative then we will now return a value where the bits above the first element are incorrectly 1 (because the narrowfn returns a sign-extended result, not one that is truncated to the element size). Fix this by using an extract operation to get exactly the correct bits of the output of the narrowfn for element 1, instead of a plain move. Cc: qemu-stable@nongnu.org Fixes: 1b7bc9b5c8bf374dd3 ("target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2089 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240123153416.877308-1-peter.maydell@linaro.org
2024-01-26hw/char/imx_serial: Implement receive FIFO and ageing timerRayhan Faizel2-14/+108
This patch implements a 32 half word FIFO as per imx serial device specifications. If a non empty FIFO is below the trigger level, an ageing timer will tick for a duration of 8 characters. On expiry, AGTIM will be set triggering an interrupt. AGTIM timer resets when there is activity in the receive FIFO. Otherwise, RRDY is set when trigger level is exceeded. The receive trigger level is 8 in newer kernel versions and 1 in older ones. This change will break migration compatibility for the imx boards. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240125151931.83494-1-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: commit message tidyups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26docs/system/arm/virt.rst: Add note on CPU features off by defaultGustavo Romero1-0/+13
Add a note on CPU features that are off by default in `virt` machines. Some CPU features will remain off even if a CPU-capable CPU (e.g., `-cpu max`) is selected because they require support in both the CPU itself and in the wider system. Therefore, the user, besides selecting a CPU that supports such features, must also turn on the feature using a machine option. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20240122211215.95073-1-gustavo.romero@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26fsl-imx6ul: Add various missing unimplemented devicesGuenter Roeck2-0/+32
Add MMDC, OCOTP, SQPI, CAAM, and USBMISC as unimplemented devices. This allows operating systems such as Linux to run emulations such as mcimx6ul-evk. Before commit 0cd4926b85 ("Refactor i.MX6UL processor code"), the affected memory ranges were covered by the unimplemented DAP device. The commit reduced the DAP address range from 0x100000 to 4kB, and the emulation thus no longer covered the various unimplemented devices in the affected address range. Fixes: 0cd4926b85 ("Refactor i.MX6UL processor code") Cc: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240120005356.2599547-1-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm: Build various units only oncePhilippe Mathieu-Daudé17-27/+12
Various files in hw/arm/ don't require "cpu.h" anymore. Except virt-acpi-build.c, all of them don't require any ARM specific knowledge anymore and can be build once as target agnostic units. Update meson accordingly. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-21-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Move GTimer definitions to new 'gtimer.h' headerPhilippe Mathieu-Daudé15-7/+35
Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU internals can use them without having to include the huge "cpu.h". Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-20-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Move e2h_access() helper aroundPhilippe Mathieu-Daudé1-14/+15
e2h_access() was added in commit bb5972e439 ("target/arm: Add VHE timer register redirection and aliasing") close to the generic_timer_cp_reginfo[] array, but isn't used until vhe_reginfo[] definition. Move it closer to the other e2h helpers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-19-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' headerPhilippe Mathieu-Daudé31-6/+35
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file. File list to include the new header generated using: $ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-18-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic headerPhilippe Mathieu-Daudé2-1/+2
Now than we can access the M-profile bank index definitions from the target-agnostic "cpu-qom.h" header, we don't need the huge "cpu.h" anymore (except in hw/arm/armv7m.c). Reduce its inclusion to the source unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-17-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Expose M-profile register bank index definitionsPhilippe Mathieu-Daudé2-15/+15
The ARMv7M QDev container accesses the QDev SysTickState by its secure/non-secure bank index. In order to make the "hw/intc/armv7m_nvic.h" header target-agnostic in the next commit, first move the M-profile bank index definitions to "target/arm/cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-16-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/misc/xlnx-versal-crl: Build it only oncePhilippe Mathieu-Daudé2-2/+1
hw/misc/xlnx-versal-crl.c doesn't require "cpu.h" anymore. By removing it, the unit become target agnostic: we can build it once. Update meson. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-15-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'Philippe Mathieu-Daudé2-1/+2
"target/arm/cpu.h" is target specific, any file including it becomes target specific too, thus this is the same for any file including "hw/misc/xlnx-versal-crl.h". "hw/misc/xlnx-versal-crl.h" doesn't require any target specific definition however, only the target-agnostic QOM definitions from "target/arm/cpu-qom.h". Include the latter header to avoid tainting unnecessary objects as target-specific. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-14-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/cpu/a9mpcore: Build it only oncePhilippe Mathieu-Daudé2-2/+2
hw/cpu/a9mpcore.c doesn't require "cpu.h" anymore. By removing it, the unit become target agnostic: we can build it once. Update meson. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-13-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé2-2/+3
Missed in commit 2d56be5a29 ("target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See it for more details. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' headerPhilippe Mathieu-Daudé10-5/+29
Declare arm_cpu_mp_affinity() prototype in the new "target/arm/multiprocessing.h" header so units in hw/arm/ can use it without having to include the huge target-specific "cpu.h". File list to include the new header generated using: $ git grep -lw arm_cpu_mp_affinity Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Create arm_cpu_mp_affinityRichard Henderson8-11/+17
Wrapper to return the mp affinity bits from the cpu. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Rename arm_cpu_mp_affinityRichard Henderson5-7/+7
Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm/cpregs: Include missing 'kvm-consts.h' headerPhilippe Mathieu-Daudé1-0/+1
target/arm/cpregs.h uses the CP_REG_ARCH_* definitions from "target/arm/kvm-consts.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpregs.h:191:18: error: use of undeclared identifier 'CP_REG_ARCH_MASK' if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm/cpregs: Include missing 'hw/registerfields.h' headerPhilippe Mathieu-Daudé1-0/+2
target/arm/cpregs.h uses the FIELD() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpregs.h:347:30: error: expected identifier FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm/cpu-features: Include missing 'hw/registerfields.h' headerPhilippe Mathieu-Daudé1-0/+2
target/arm/cpu-features.h uses the FIELD_EX32() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpu-features.h:44:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/xlnx-versal: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
include/hw/arm/xlnx-versal.h uses the ARMCPU structure which is defined in the "target/arm/cpu.h" header. Include it in order to avoid when refactoring unrelated headers: In file included from hw/arm/xlnx-versal-virt.c:20: include/hw/arm/xlnx-versal.h:62:23: error: array has incomplete element type 'ARMCPU' (aka 'struct ArchCPU') ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/smmuv3: Include missing 'hw/registerfields.h' headerPhilippe Mathieu-Daudé1-0/+1
hw/arm/smmuv3-internal.h uses the REG32() and FIELD() macros defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: In file included from ../../hw/arm/smmuv3.c:34: hw/arm/smmuv3-internal.h:36:28: error: expected identifier REG32(IDR0, 0x0) ^ hw/arm/smmuv3-internal.h:37:5: error: expected function body after function declarator FIELD(IDR0, S2P, 0 , 1) ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' headerPhilippe Mathieu-Daudé1-0/+1
hw/arm/xilinx_zynq.c calls tswap32() which is declared in "exec/tswap.h". Include it in order to avoid when refactoring unrelated headers: hw/arm/xilinx_zynq.c:103:31: error: call to undeclared function 'tswap32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] board_setup_blob[n] = tswap32(board_setup_blob[n]); ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/exynos4210: Include missing 'exec/tswap.h' headerPhilippe Mathieu-Daudé1-0/+1
hw/arm/exynos4210.c calls tswap32() which is declared in "exec/tswap.h". Include it in order to avoid when refactoring unrelated headers: hw/arm/exynos4210.c:499:22: error: call to undeclared function 'tswap32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] smpboot[n] = tswap32(smpboot[n]); ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm: Add watchdog timer to Allwinner H40 and Bananapi boardGuenter Roeck4-1/+13
Add watchdog timer support to Allwinner-H40 and Bananapi. The watchdog timer is added as an overlay to the Timer module memory map. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20240115182757.1095012-4-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi boardGuenter Roeck4-1/+16
Allwinner R40 supports an AHCI compliant SATA controller. Add support for it. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20240115182757.1095012-3-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi boardGuenter Roeck4-3/+57
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. Add support for both of them. If machine USB support is not enabled, create unimplemented devices for the USB memory ranges to avoid crashes when booting Linux. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240115182757.1095012-2-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controllerPhilippe Mathieu-Daudé1-3/+1
The TUSB6010 USB controller is soldered on the N800 and N810 tablets, thus is always present. This is a migration compatibility break for the n800/n810 machines started with the '-usb none' option. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240119215106.45776-3-philmd@linaro.org [PMM: fixed commit message typo] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/allwinner-a10: Unconditionally map the USB Host controllersPhilippe Mathieu-Daudé1-31/+22
The USB Controllers are part of the chipset, thus are always present and mapped in memory. This is a migration compatibility break for the cubieboard machine started with the '-usb none' option. Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20240119215106.45776-2-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()Peter Maydell1-68/+59
Convert the musicpal key input device to use qemu_add_kbd_event_handler(). This lets us simplify it because we no longer need to track whether we're in the middle of a PS/2 multibyte key sequence. In the conversion we move the keyboard handler registration from init to realize, because devices shouldn't disturb the state of the simulation by doing things like registering input handlers until they're realized, so that device objects can be introspected safely. The behaviour where key-repeat is permitted for the arrow-keys only is intentional (added in commit 7c6ce4baedfcd0c), so we retain it, and add a comment to that effect. This is a migration compatibility break for musicpal. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20231103182750.855577-1-peter.maydell@linaro.org
2024-01-26hw/arm/virt.c: Remove newline from error_report() stringPeter Maydell1-2/+2
error_report() strings should not include trailing newlines; remove the newline from the error we print when devices won't fit into the address space of the CPU. This commit also fixes the accidental hardcoded tabs that were in this line, since we have to touch the line anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240118131649.2726375-1-peter.maydell@linaro.org
2024-01-26target/arm: Fix VNCR fault detection logicPeter Maydell1-1/+1
In arm_deliver_fault() we check for whether the fault is caused by a data abort due to an access to a FEAT_NV2 sysreg in the memory pointed to by the VNCR. Unfortunately part of the condition checks the wrong argument to the function, meaning that it would spuriously trigger, resulting in some instruction aborts being taken to the wrong EL and reported incorrectly. Use the right variable in the condition. Fixes: 674e5345275d425 ("target/arm: Report VNCR_EL2 based faults correctly") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-id: 20240116165605.2523055-1-peter.maydell@linaro.org
2024-01-26target/xtensa: fix OOB TLB entry accessMax Filippov1-12/+35
r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register by the guest. The host uses 3 bits of the index for ITLB indexing and 4 bits for DTLB, but there's only 7 entries in the ITLB array and 10 in the DTLB array, so a malicious guest may trigger out-of-bound access to these arrays. Change split_tlb_entry_spec return type to bool to indicate whether TLB way passed to it is valid. Change get_tlb_entry to return NULL in case invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that requested TLB way and entry indices are valid. Add checks to the [rwi]tlb helpers that requested TLB way is valid and return 0 or do nothing when it's not. Cc: qemu-stable@nongnu.org Fixes: b67ea0cd7441 ("target-xtensa: implement memory protection options") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20231215120307.545381-1-jcmvbkbc@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26iotests/277: Use iotests.sock_dir for socket creationAndrey Drobyshev1-1/+2
If socket path is too long (longer than 108 bytes), socket can't be opened. This might lead to failure when test dir path is long enough. Make sure socket is created in iotests.sock_dir to avoid such a case. This commit basically aligns iotests/277 with the rest of iotests. Signed-off-by: Andrey Drobyshev <andrey.drobyshev@virtuozzo.com> Message-ID: <20240124162257.168325-1-andrey.drobyshev@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
generated by cgit v1.1 at 2024-09-30 22:54:14 +0000