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2024-05-06Merge tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu into stagingRichard Henderson10-216/+265
qemu-sparc queue # -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmY4wZceHG1hcmsuY2F2 # ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIftQsH+wfIWymTdQMowfM6 # Ze/T8KODn+MqU5eg25VPSTojnmr7LFaCj2yK6zWX61RwIqtMc3NaxX0G7ksW12/g # 35ACqiEEd5WRDhAtVhj5Wp+WEDoR4AD3LWIaN7a/qjO3qb78l7Bujw3qXzGSq4lQ # hST6dTgMwn5LhJOyz+5dORVUK1UZSBuDxHeKRHgdoFi6yqGQ5bao5TpaDYOnGSbx # 8KPrAFfXG1T6xRS8Ih5HXAPE5VJztLFPiVtCTTrETDP/o8EzvOZj5y/nJVZXXC3N # 57g+QyJX9EdrRZvobef4LnNnoZyiqG+uQNugglqZqjiiLjl6AzYxI+ed0hU+cZR9 # pz76Hr8= # =i2cV # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 May 2024 04:40:07 AM PDT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] * tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu: target/sparc: Split out do_ms16b target/sparc: Fix FPMERGE target/sparc: Fix FMULD8*X16 target/sparc: Fix FMUL8x16A{U,L} target/sparc: Fix FMUL8x16 target/sparc: Fix FEXPAND linux-user/sparc: Add more hwcap bits for sparc64 hw/sparc64: set iommu_platform=on for virtio devices attached to the sun4u machine docs/about: Deprecate the old "UltraSparc" CPU names that contain a "+" docs/system/target-sparc: Improve the Sparc documentation target/sparc/cpu: Avoid spaces by default in the CPU names target/sparc/cpu: Rename the CPU models with a "+" in their names Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06Merge tag 'accel-20240506' of https://github.com/philmd/qemu into stagingRichard Henderson91-298/+419
Accelerator patches - Extract page-protection definitions to page-protection.h - Rework in accel/tcg in preparation of extracting TCG fields from CPUState - More uses of get_task_state() in user emulation - Xen refactors in preparation for adding multiple map caches (Juergen & Edgar) - MAINTAINERS updates (Aleksandar and Bin) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmY40CAACgkQ4+MsLN6t # wN5drxAA1oIsuUzpAJmlMIxZwlzbICiuexgn/HH9DwWNlrarKo7V1l4YB8jd9WOg # IKuj7c39kJKsDEB8BXApYwcly+l7DYdnAAI8Z7a+eN+ffKNl/0XBaLjsGf58RNwY # fb39/cXWI9ZxKxsHMSyjpiu68gOGvZ5JJqa30Fr+eOGuug9Fn/fOe1zC6l/dMagy # Dnym72stpD+hcsN5sVwohTBIk+7g9og1O/ctRx6Q3ZCOPz4p0+JNf8VUu43/reaR # 294yRK++JrSMhOVFRzP+FH1G25NxiOrVCFXZsUTYU+qPDtdiKtjH1keI/sk7rwZ7 # U573lesl7ewQFf1PvMdaVf0TrQyOe6kUGr9Mn2k8+KgjYRAjTAQk8V4Ric/+xXSU # 0rd7Cz7lyQ8jm0DoOElROv+lTDQs4dvm3BopF3Bojo4xHLHd3SFhROVPG4tvGQ3H # 72Q5UPR2Jr2QZKiImvPceUOg0z5XxoN6KRUkSEpMFOiTRkbwnrH59z/qPijUpe6v # 8l5IlI9GjwkL7pcRensp1VC6e9KC7F5Od1J/2RLDw3UQllMQXqVw2bxD3CEtDRJL # QSZoS4d1jUCW4iAYdqh/8+2cOIPiCJ4ai5u7lSdjrIJkRErm32FV/pQLZauoHlT5 # eTPUgzDoRXVgI1X1slTpVXlEEvRNbhZqSkYLkXr80MLn5hTafo0= # =3Qkg # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 May 2024 05:42:08 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'accel-20240506' of https://github.com/philmd/qemu: (28 commits) MAINTAINERS: Update my email address MAINTAINERS: Update Aleksandar Rikalo email system: Pass RAM MemoryRegion and is_write in xen_map_cache() xen: mapcache: Break out xen_map_cache_init_single() xen: mapcache: Break out xen_invalidate_map_cache_single() xen: mapcache: Refactor xen_invalidate_map_cache_entry_unlocked xen: mapcache: Refactor xen_replace_cache_entry_unlocked xen: mapcache: Break out xen_ram_addr_from_mapcache_single xen: mapcache: Refactor xen_remap_bucket for multi-instance xen: mapcache: Refactor xen_map_cache for multi-instance xen: mapcache: Refactor lock functions for multi-instance xen: let xen_ram_addr_from_mapcache() return -1 in case of not found entry system: let qemu_map_ram_ptr() use qemu_ram_ptr_length() user: Use get_task_state() helper user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h' user: Forward declare TaskState type definition accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetState accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCG accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG plugins accel/tcg: Update CPUNegativeOffsetState::can_do_io field documentation ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06Merge tag 'pull-qapi-2024-05-06' of https://repo.or.cz/qemu/armbru into stagingRichard Henderson9-148/+164
QAPI patches patches for 2024-05-06 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmY4uIASHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTCYoQAK8Y2SSPlRqwdyYWqQHcPuQe4ThvnT2l # y1Dzcy0MGKdeDQng+lyMh9x50U6vMd33TaWEDZ4PEprSLirWnRIIL9/qgrc+obYB # LfncQR7BRLEPYRA0cQwvSBNzSLgCiySoa9x98yCB1ZZGQsAMz4p1j8qDpJFAL2qa # VThXFcBaUOPRKFDwp03r8n8PFsaqaBVjI/2YX13EyJksaPNLNT6Z2xfcgREXFu2I # gWfFR21kJwkUAgkfc6LhmqlpKXBpKQ+bWCmV1G/+LZosid3B8jfKOfOx4s9q9g5G # N7HVRSHlqPyGQeJGaiiKgPZyoRh65L0YRa3OtYoJL9ngx1P7opAGxnxSsARduNg3 # yQbbFY4c99HuxgxfMLwRPWr6Xm3c5DEvdIwoVRWm1ajJynbLWNiTN/uQs+tIEFbr # 4usxqAQRo2G5WkY9JGuDuBJkZTp1/6pEM0xVrRgGYH9jr8LZrS2HPrnbcsa3eqAl # UqSfu8HAL8j1wiBAr83DQe+SuoyRfrnFaTNYAILFG4RUsWF2u44RvkceGroyq3s1 # mgHFZGF0+m8K7TXqeJvkSgg4wr2AnavXrb79Zz2JVut0X6K6S4AbueTBIn8zT2EX # uGHhm4ZW5JUq6Wz6bQtq6/IUa/k2pAlszVFHe3Yn50J3CUU5dR/nYry7Cx4Q6/KT # h4vzopMBjVv1 # =3Pxa # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 May 2024 04:01:20 AM PDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] * tag 'pull-qapi-2024-05-06' of https://repo.or.cz/qemu/armbru: qapi: Simplify QAPISchemaVariants @tag_member qapi: Move conditional code from QAPISchemaVariants to its subtypes qapi: Rename QAPISchemaAlternateType.variants to .alternatives qapi: Rename QAPISchemaObjectType.variants to .branches qapi: Rename visitor parameter @variants to @alternatives qapi: Rename visitor parameter @variants to @branches qapi: New QAPISchemaBranches, QAPISchemaAlternatives Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson84-280/+455
* target/i386: Introduce SapphireRapids-v3 to add missing features * switch boards to "default y" * allow building emulators without any board * configs: list "implied" device groups in the default configs * remove unnecessary declarations from typedefs.h * target/i386: Give IRQs a chance when resetting HF_INHIBIT_IRQ_MASK # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmY1ILsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNtIwf+MEehq2HudZvsK1M8FrvNmkB/AssO # x4tqL8DlTus23mQDBu9+rANTB93ManJdK9ybtf6NfjEwK+R8RJslLVnuy/qT+aQX # PD208L88fjZg17G8uyawwvD1VmqWzHFSN14ShmKzqB2yPXXo/1cJ30w78DbD50yC # 6rw/xbC5j195CwE2u8eBcIyY4Hh2PUYEE4uyHbYVr57cMjfmmA5Pg4I4FJrpLrF3 # eM2Avl/4pIbsW3zxXVB8QbAkgypxZErk3teDK1AkPJnlnBYM1jGKbt/GdKe7vcHR # V/o+7NlcbS3oHVItQ2gP3m91stjFq+NhixaZpa0VlmuqayBa3xNGl0G6OQ== # =ZbNW # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 May 2024 10:36:59 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (46 commits) qga/commands-posix: fix typo in qmp_guest_set_user_password migration: do not include coroutine_int.h kvm: move target-dependent interrupt routing out of kvm-all.c pci: remove some types from typedefs.h tcg: remove CPU* types from typedefs.h display: remove GraphicHwOps from typedefs.h qapi/machine: remove types from typedefs.h monitor: remove MonitorDef from typedefs.h migration: remove PostcopyDiscardState from typedefs.h lockable: remove QemuLockable from typedefs.h intc: remove PICCommonState from typedefs.h qemu-option: remove QemuOpt from typedefs.h net: remove AnnounceTimer from typedefs.h numa: remove types from typedefs.h qdev-core: remove DeviceListener from typedefs.h fw_cfg: remove useless declarations from typedefs.h build: do not build virtio-vga-gl if virgl/opengl not available bitmap: Use g_try_new0/g_new0/g_renew target/i386: Introduce SapphireRapids-v3 to add missing features docs: document new convention for Kconfig board symbols ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06Merge tag 'pull-hex-20240505' of https://github.com/quic/qemu into stagingRichard Henderson26-613/+377
Short-circuit for packets with r/w and no overlap # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmY4FR8ACgkQGlSvuOVk # bDLEfxAAup6v9J4n2/q88FXfLGgx1EfZrT01gOM/48mwngNNQJGJQySe2GLl0G8S # 1hx/Ym3jbikic8HL80v8FyCr4gNRshEY7xKpCfvY9lsgnCRbhEvoV/hZqucmLQAt # 1SIhFSsi5h8gyZDTvXhH75v3qGvYjQ7fQBhy2JbRsPjthdHBh9xi6Na60wlqfNZq # oGsVtY7sv1uHsvDKBi3JoXWckSK99R38BHY6zPoStarRZACkkLdX6KHxeX88TUt1 # whIUYUS/K0nRVxzekdq/+m8UJYrXnW/0cliM5mLFHDGlsV+qjdcIRrfaPWBO0eFN # kXeZU2BWLCdP2M52FHI4FllnIRpX5OGkxjR6x8Pc9r+EGciwGRU7xeAlqBxKQSZP # e3oXtV6oKxg69xBgHE5HcKbt6bX5EZR/sUcbAoGA41UssaiMyj3wbg1cy2UxXu2J # 7oJyywJUggWGSoCIIJJ95YgpUrIg73Yg6pOjfhKW1w/V2SuQPGG0XTXrwe7J6uGi # VAqyu55p2oiW8Gk4Lvl1SfWgxkVeZa/NcxTmXNEWFnT7vatqwez0O5pxIkxdSCFE # lRv7PuFT5nhQ/gg12zGqqRiOrMOMQitHFzJ9sUNu7J4Y7W5R4gzRW19ucojLt0lH # fT83Ra+Eex1Cu3DsuvWkokxFikxXP1Ll297Jr1JhOPewTtvlxvI= # =Q8/k # -----END PGP SIGNATURE----- # gpg: Signature made Sun 05 May 2024 04:24:15 PM PDT # gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32 # gpg: Good signature from "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown] # gpg: aka "Brian Cain <bcain@kernel.org>" [unknown] # gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown] # gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown] # gpg: aka "bcain" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47 # Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32 * tag 'pull-hex-20240505' of https://github.com/quic/qemu: Hexagon (target/hexagon) Remove hex_common.read_attribs_file Hexagon (target/hexagon) Remove gen_shortcode.py Hexagon (target/hexagon) Remove gen_op_regs.py Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair Hexagon (target/hexagon) Mark has_pred_dest in trans functions Hexagon (target/hexagon) Mark dest_idx in trans functions Hexagon (target/hexagon) Mark new_read_idx in trans functions Hexagon (target/hexagon) Add is_old/is_new to Register class Hexagon (target/hexagon) Only pass env to generated helper when needed Hexagon (target/hexagon) Pass SP explicitly to helpers that need it Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it Hexagon (target/hexagon) Enable more short-circuit packets (HVX) Hexagon (target/hexagon) Enable more short-circuit packets (scalar core) Hexagon (target/hexagon) Analyze reads before writes Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06MAINTAINERS: Update my email addressBin Meng1-4/+4
The old Wind River email address (bin.meng@windriver.com) is no longer available due to an internal infrastructure change within the company. While a new email address (bin.meng.cn@windriver.com) has been assigned to me, I am unable to find a way to send this patch directly from the new address. Presumably, the basic authentication with client submission (SMTP AUTH) [1] has been disabled by the company's IT. Switch to use my personal email address instead. Signed-off-by: Bin Meng <bin.meng.cn@windriver.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> [1] https://learn.microsoft.com/en-us/exchange/mail-flow-best-practices/how-to-set-up-a-multifunction-device-or-application-to-send-email-using-microsoft-365-or-office-365 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240505072312.2776074-1-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06MAINTAINERS: Update Aleksandar Rikalo emailAleksandar Rikalo1-5/+5
Syrmia LLC has been acquired recently and the syrmia.com domain will disappear soon, so updating my email in the MAINTAINERS file. Signed-off-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Message-ID: <20240209062147.62453-1-aleksandar.rikalo@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06system: Pass RAM MemoryRegion and is_write in xen_map_cache()Edgar E. Iglesias3-16/+36
Propagate MR and is_write to xen_map_cache(). This is in preparation for adding support for grant mappings. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <20240430164939.925307-14-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Break out xen_map_cache_init_single()Edgar E. Iglesias1-21/+32
Break out xen_map_cache_init_single() in preparation for adding multiple map caches. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240430164939.925307-11-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Break out xen_invalidate_map_cache_single()Edgar E. Iglesias1-10/+15
Break out xen_invalidate_map_cache_single(). No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-10-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_invalidate_map_cache_entry_unlockedEdgar E. Iglesias1-10/+11
Add MapCache argument to xen_invalidate_map_cache_entry_unlocked. This is in preparation for supporting multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-9-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_replace_cache_entry_unlockedEdgar E. Iglesias1-4/+6
Add MapCache argument to xen_replace_cache_entry_unlocked in preparation for supporting multiple map caches. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-8-edgar.iglesias@gmail.com> [PMD: Remove last global mapcache pointer, reported by sstabellini] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Break out xen_ram_addr_from_mapcache_singleEdgar E. Iglesias1-6/+11
Break out xen_ram_addr_from_mapcache_single(), a multi-cache aware version of xen_ram_addr_from_mapcache. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-7-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_remap_bucket for multi-instanceEdgar E. Iglesias1-4/+5
Add MapCache argument to xen_remap_bucket in preparation to support multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240430164939.925307-6-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor xen_map_cache for multi-instanceEdgar E. Iglesias1-17/+18
Make xen_map_cache take a MapCache as argument. This is in prepaparation to support multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240430164939.925307-5-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: mapcache: Refactor lock functions for multi-instanceEdgar E. Iglesias1-17/+17
Make the lock functions take MapCache * as argument. This is in preparation for supporting multiple caches. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240430164939.925307-4-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06xen: let xen_ram_addr_from_mapcache() return -1 in case of not found entryJuergen Gross1-7/+3
Today xen_ram_addr_from_mapcache() will either abort() or return 0 in case it can't find a matching entry for a pointer value. Both cases are bad, so change that to return an invalid address instead. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <20231005181629.4046-5-vikram.garhwal@amd.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240430164939.925307-3-edgar.iglesias@gmail.com> [PMD: Keep xen_ram_addr_from_mapcache_not_found trace event] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06system: let qemu_map_ram_ptr() use qemu_ram_ptr_length()Juergen Gross1-33/+23
qemu_map_ram_ptr() and qemu_ram_ptr_length() share quite some code, so modify qemu_ram_ptr_length() a little bit and use it for qemu_map_ram_ptr(), too. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227223501.28475-4-vikram.garhwal@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-ID: <20240430164939.925307-2-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06user: Use get_task_state() helperPhilippe Mathieu-Daudé3-5/+6
Get the TaskState pointer calling get_task_state(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-11-philmd@linaro.org>
2024-05-06user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h'Philippe Mathieu-Daudé3-10/+20
While each user emulation implentation defines its own TaskState structure, both use the same get_task_state() declaration, in particular in common code (such gdbstub). Declare the method once in "accel/tcg/vcpu-state.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-10-philmd@linaro.org>
2024-05-06user: Forward declare TaskState type definitionPhilippe Mathieu-Daudé3-4/+5
Forward declare TaskState in "qemu/typedefs.h" so we can use it in generic headers like "hw/cpu/core.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-9-philmd@linaro.org>
2024-05-06qapi: Simplify QAPISchemaVariants @tag_memberMarkus Armbruster1-26/+18
For union types, the tag member is known only after .check(). We used to code this in a simple way: QAPISchemaVariants attribute .tag_member was None for union types until .check(). Since this complicated typing, recent commit "qapi/schema: fix typing for QAPISchemaVariants.tag_member" hid it behind a property. The previous commit lets us treat .tag_member just like the other attributes that become known only in .check(): declare, but don't initialize it in .__init__(). Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06qapi: Move conditional code from QAPISchemaVariants to its subtypesMarkus Armbruster1-70/+70
QAPISchemaVariants.check()'s code is almost entirely conditional on union vs. alternate type. Move the conditional code to QAPISchemaBranches.check() and QAPISchemaAlternatives.check(), where the conditions are always satisfied. Attribute QAPISchemaVariants.tag_name is now only used by QAPISchemaBranches. Move it there. Refactor the three types' .__init__() to make them a bit simpler. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06qapi: Rename QAPISchemaAlternateType.variants to .alternativesMarkus Armbruster1-12/+13
A previous commit narrowed the type of QAPISchemaAlternateType.variants from QAPISchemaVariants to QAPISchemaAlternatives. Rename it to .alternatives. Same for .__init__() parameter @variants. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06qapi: Rename QAPISchemaObjectType.variants to .branchesMarkus Armbruster5-22/+22
A previous commit narrowed the type of QAPISchemaObjectType.variants from QAPISchemaVariants to QAPISchemaBranches. Rename it to .branches. Same for .__init__() parameter @variants. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06qapi: Rename visitor parameter @variants to @alternativesMarkus Armbruster6-12/+15
A previous commit narrowed the type of .visit_alternate_type() parameter @variants from QAPISchemaVariants to QAPISchemaAlternatives. Rename it to @alternatives. One of them passes @alternatives to helper function gen_visit_alternate(). Rename its @variants parameter to @alternatives as well. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06qapi: Rename visitor parameter @variants to @branchesMarkus Armbruster6-25/+25
The previous commit narrowed the type of .visit_object_type() parameter @variants from QAPISchemaVariants to QAPISchemaBranches. Rename it to @branches. Same for .visit_object_type_flat(). A few of these pass @branches to helper functions: QAPISchemaGenRSTVisitor.visit_object_type() to ._nodes_for_members() and ._nodes_for_variant_when(), and QAPISchemaGenVisitVisitor.visit_object_type() to gen_visit_object_members(). Rename the helpers' @variants parameters to @branches as well. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06qapi: New QAPISchemaBranches, QAPISchemaAlternativesMarkus Armbruster4-18/+38
QAPISchemaVariants represents either a union type's branches, or an alternate type's alternatives. Much of its code is conditional on which one it actually is. Create QAPISchemaBranches for branches, and QAPISchemaAlternatives for alternatives, both subtypes of QAPISchemaVariants. Replace QAPISchemaVariants by one of them where possible. Keep it only where we actually deal with either of them. QAPISchemaVariants.__init__() takes @tag_name and @tag_member, where exactly one must be None: @tag_name for alternatives, @tag_member for branches. Let QAPISchemaBranches.__init__() take just @tag_name, and QAPISchemaAlternatives.__init__() take just @tag_member. A later patch will move the conditional code to the subtypes. Signed-off-by: Markus Armbruster <armbru@redhat.com>
2024-05-06accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetStatePhilippe Mathieu-Daudé5-12/+13
@plugin_mem_cbs is accessed by tcg generated code, move it to CPUNegativeOffsetState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429213050.55177-4-philmd@linaro.org>
2024-05-06accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCGPhilippe Mathieu-Daudé2-17/+17
So far cpu_plugin_mem_cbs_enabled() is only called from TCG, so reduce it to accel/tcg/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <5f59c754-44e5-4743-a2dd-87ef8e13eadf@linaro.org>
2024-05-06accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG pluginsPhilippe Mathieu-Daudé1-0/+4
qemu_plugin_vcpu_exit_hook() is specific to TCG plugins, so must be restricted to it in cpu_common_unrealizefn(), similarly to how qemu_plugin_create_vcpu_state() is restricted in the cpu_common_realizefn() counterpart. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429213050.55177-2-philmd@linaro.org>
2024-05-06accel/tcg: Update CPUNegativeOffsetState::can_do_io field documentationPhilippe Mathieu-Daudé1-4/+4
The @can_do_io field got moved from CPUState to CPUNegativeOffsetState in commit 464dacf609 ("accel/tcg: Move can_do_io to CPUNegativeOffsetState"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-14-philmd@linaro.org>
2024-05-06accel/tcg: Move user definition of cpu_interrupt() to user-exec.cPhilippe Mathieu-Daudé2-9/+8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-4-philmd@linaro.org>
2024-05-06accel/tcg: Access tcg_cflags with getter / setterPhilippe Mathieu-Daudé23-29/+44
Access the CPUState::tcg_cflags via tcg_cflags_has() and tcg_cflags_set() helpers. Mechanical change using the following Coccinelle spatch script: @@ expression cpu; expression flags; @@ - cpu->tcg_cflags & flags + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - (tcg_cflags_has(cpu, flags)) + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - cpu->tcg_cflags |= flags; + tcg_cflags_set(cpu, flags); Then manually moving the declarations, and adding both tcg_cflags_has() and tcg_cflags_set() definitions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-15-philmd@linaro.org>
2024-05-06accel/tcg: Use cpu_loop_exit_requested() in cpu_loop_exec_tb()Philippe Mathieu-Daudé1-5/+2
Do not open-code cpu_loop_exit_requested(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428214915.10339-9-philmd@linaro.org>
2024-05-06exec/cpu: Extract page-protection definitions to page-protection.hPhilippe Mathieu-Daudé59-30/+100
Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-protection.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-05-06exec/cpu: Remove duplicated PAGE_PASSTHROUGH definitionPhilippe Mathieu-Daudé1-6/+0
Missed in commit 58771921af ("include/exec: Move PAGE_* macros to common header"), PAGE_PASSTHROUGH ended being defined twice. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-8-philmd@linaro.org>
2024-05-06exec/cpu: Remove obsolete PAGE_RESERVED definitionPhilippe Mathieu-Daudé1-4/+0
We stopped using the PAGE_RESERVED definition in commit 50d25c8aec ("accel/tcg: Drop PAGE_RESERVED for CONFIG_BSD"). This completes commit 2e9a5713f0 ("Remove PAGE_RESERVED"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-7-philmd@linaro.org>
2024-05-06exec/cpu: Rename PAGE_BITS macro to PAGE_RWXBALATON Zoltan7-10/+10
This macro can be used to abbreviate PAGE_READ | PAGE_WRITE | PAGE_EXEC for which PAGE_RWX is a better name and renaming it also shows it is not related to TARGET_PAGE_BITS. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240505121008.44A0D4E602D@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-06exec/cpu: Indent TARGET_PAGE_foo definitionsPhilippe Mathieu-Daudé1-12/+13
The TARGET_PAGE_foo definitions are defined with multiple level of #ifdef'ry. Indent it a bit for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-6-philmd@linaro.org>
2024-05-05Hexagon (target/hexagon) Remove hex_common.read_attribs_fileTaylor Simpson11-118/+52
The attribinfo data structure is not used Adjust the command-line arguments to the python scripts Add hex_common.read_common_files for TCG/helper generation scripts Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240307032327.4799-10-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Remove gen_shortcode.pyTaylor Simpson4-81/+0
This data structure is not used Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240307032327.4799-9-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Remove gen_op_regs.pyTaylor Simpson3-138/+2
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-8-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Remove uses of op_regs_generated.h.incTaylor Simpson4-110/+13
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-7-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pairTaylor Simpson1-1/+15
Make sure the decoding of HVX .new is correctly handling this case Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-6-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Mark has_pred_dest in trans functionsTaylor Simpson3-0/+9
Check that the value matches opcode_wregs Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-5-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Mark dest_idx in trans functionsTaylor Simpson4-0/+11
Check that the value matches opcode_reginfo/opcode_wregs Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-4-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Mark new_read_idx in trans functionsTaylor Simpson4-6/+16
Check that the value matches opcode_reginfo Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-3-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Add is_old/is_new to Register classTaylor Simpson1-0/+12
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-05-05Hexagon (target/hexagon) Only pass env to generated helper when neededTaylor Simpson3-8/+32
Currently, we pass env to every generated helper. When the semantics of the instruction only depend on the arguments, this is unnecessary and adds extra overhead to the helper call. We add the TCG_CALL_NO_RWG_SE flag to any non-HVX helpers that don't get the ptr to env. The A2_nop and SA1_setin1 instructions end up with no arguments. This results in a "old-style function definition" error from the compiler, so we write overrides for them. With this change, the number of helpers with env argument is idef-parser enabled: 329 total, 23 with env idef-parser disabled: 1543 total, 550 with env Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240214042726.19290-4-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
generated by cgit v1.1 at 2025-01-09 20:22:31 +0000