riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-06-25	docs/devel: Add a single top-level header to MTTCG's doc	Luis Pires	1	-2/+3
2021-06-25	tests/acceptance: tweak the tcg/kvm tests for virt	Alex Bennée	1	-12/+12
2021-06-25	Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210624-pull-request' i...	Peter Maydell	7	-30/+224
2021-06-24	target/mips: Merge msa32/msa64 decodetree definitions	Philippe Mathieu-Daudé	4	-32/+10
2021-06-24	target/mips: Remove pointless gen_msa()	Philippe Mathieu-Daudé	1	-6/+1
2021-06-24	target/mips: Optimize regnames[] arrays	Philippe Mathieu-Daudé	5	-7/+7
2021-06-24	target/mips: Constify host_to_mips_errno[]	Philippe Mathieu-Daudé	1	-1/+1
2021-06-24	target/mips: fix emulation of nanoMIPS BPOSGE32 instruction	Aleksandar Rikalo	1	-1/+1
2021-06-24	target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases	Philippe Mathieu-Daudé	1	-6/+0
2021-06-24	target/mips: Remove SmartMIPS / MDMX unuseful comments	Philippe Mathieu-Daudé	1	-8/+0
2021-06-24	target/mips: Restrict some system specific declarations to sysemu	Philippe Mathieu-Daudé	1	-3/+7
2021-06-24	target/mips: Move translate.h to tcg/ sub directory	Philippe Mathieu-Daudé	1	-0/+0
2021-06-24	target/mips: Move TCG trace events to tcg/ sub directory	Philippe Mathieu-Daudé	5	-3/+3
2021-06-24	target/mips: Do not abort on invalid instruction	Philippe Mathieu-Daudé	1	-2/+2
2021-06-24	target/mips: Raise exception when DINSV opcode used with DSP disabled	Philippe Mathieu-Daudé	1	-1/+2
2021-06-24	target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn	Philippe Mathieu-Daudé	1	-0/+4
2021-06-24	target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()	Philippe Mathieu-Daudé	1	-0/+2
2021-06-24	target/mips: Fix potential integer overflow (CID 1452921)	Philippe Mathieu-Daudé	1	-1/+2
2021-06-24	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210624'...	Peter Maydell	27	-629/+3578
2021-06-24	docs/system: arm: Add nRF boards description	Alexandre Iooss	3	-0/+53
2021-06-24	target/arm: Implement MTE3	Peter Collingbourne	3	-32/+53
2021-06-24	target/arm: Make VMOV scalar <-> gpreg beatwise for MVE	Peter Maydell	3	-8/+75
2021-06-24	target/arm: Implement MVE VADDV	Peter Maydell	4	-0/+76
2021-06-24	target/arm: Implement MVE VHCADD	Peter Maydell	4	-3/+19
2021-06-24	target/arm: Implement MVE VCADD	Peter Maydell	4	-2/+51
2021-06-24	target/arm: Implement MVE VADC, VSBC	Peter Maydell	4	-0/+99
2021-06-24	target/arm: Implement MVE VRHADD	Peter Maydell	4	-0/+19
2021-06-24	target/arm: Implement MVE VQDMULL (vector)	Peter Maydell	4	-0/+70
2021-06-24	target/arm: Implement MVE VQDMLSDH and VQRDMLSDH	Peter Maydell	4	-0/+69
2021-06-24	target/arm: Implement MVE VQDMLADH and VQRDMLADH	Peter Maydell	4	-0/+114
2021-06-24	target/arm: Implement MVE VRSHL	Peter Maydell	4	-0/+17
2021-06-24	target/arm: Implement MVE VSHL insn	Peter Maydell	4	-0/+19
2021-06-24	target/arm: Implement MVE VQRSHL	Peter Maydell	4	-0/+19
2021-06-24	target/arm: Implement MVE VQSHL (vector)	Peter Maydell	4	-0/+56
2021-06-24	target/arm: Implement MVE VQADD, VQSUB (vector)	Peter Maydell	4	-0/+39
2021-06-24	target/arm: Implement MVE VQDMULH, VQRDMULH (vector)	Peter Maydell	4	-0/+40
2021-06-24	target/arm: Implement MVE VQDMULL scalar	Peter Maydell	4	-4/+119
2021-06-24	target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)	Peter Maydell	4	-0/+38
2021-06-24	target/arm: Implement MVE VQADD and VQSUB	Peter Maydell	4	-0/+87
2021-06-24	target/arm: Implement MVE VPST	Peter Maydell	2	-0/+63
2021-06-24	target/arm: Implement MVE VBRSR	Peter Maydell	4	-0/+49
2021-06-24	target/arm: Implement MVE VHADD, VHSUB (scalar)	Peter Maydell	4	-0/+32
2021-06-24	target/arm: Implement MVE VSUB, VMUL (scalar)	Peter Maydell	4	-0/+14
2021-06-24	target/arm: Implement MVE VADD (scalar)	Peter Maydell	4	-0/+78
2021-06-24	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	Alistair Francis	2	-4/+15
2021-06-24	hw/timer: Initial commit of Ibex Timer	Alistair Francis	4	-4/+360
2021-06-24	hw/char/ibex_uart: Make the register layout private	Alistair Francis	2	-37/+37
2021-06-24	hw/char: QOMify sifive_uart	Lukas Jünger	2	-16/+109
2021-06-24	hw/char: Consistent function names for sifive_uart	Lukas Jünger	1	-22/+24
2021-06-24	target/riscv: gdbstub: Fix dynamic CSR XML generation	Bin Meng	1	-1/+1