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2023-06-14Merge tag 'pull-riscv-to-apply-20230614' of ↵Richard Henderson29-1102/+1442
https://github.com/alistair23/qemu into staging Second RISC-V PR for 8.1 * Skip Vector set tail when vta is zero * Move zc* out of the experimental properties * Mask the implicitly enabled extensions in isa_string based on priv version * Rework CPU extension validation and validate MISA changes * Fixup PMP TLB cacheing errors * Writing to pmpaddr and MML/MMWP correctly triggers TLB flushes * Fixup PMP bypass checks * Deny access if access is partially inside a PMP entry * Correct OpenTitanState parent type/size * Fix QEMU crash when NUMA nodes exceed available CPUs * Fix pointer mask transformation for vector address * Updates and improvements for Smstateen * Support disas for Zcm* extensions * Support disas for Z*inx extensions * Remove unused decomp_rv32/64 value for vector instructions * Enable PC-relative translation * Assume M-mode FW in pflash0 only when "-bios none" * Support using pflash via -blockdev option * Add vector registers to log * Clean up reference of Vector MTYPE * Remove the check for extra Vector tail elements * Smepmp: Return error when access permission not allowed in PMP * Fixes for smsiaddrcfg and smsiaddrcfgh in AIA # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSJFRoACgkQr3yVEwxT # gBMUkg/8Cuhqpx+zy7MeouVkyhEjUuhtCWyr0WVZBJzDkVEOrlY6TyR0hb5/o1Js # LZf6ZMF6JQDN78bmUct8yFBZBGafey5tyonDCsnD7CNQuLPf2NSjTHhu9n5hKFqF # F8Mpn9iFu6k1pr0iF7FbCccVWuDb3P4h2PaM0iFhmf4uz42BCMYdgJThhvv38xlt # jr6A3dcjTpp8yB+iRCuhL2IU2XVee0XBiDUECqRXd0gmtOtqJNST8L+l8YkLy1VO # WUMe8RCO6NMP7BLJ383WwCDeiFTo0mJebZQ0eR/G1xEhy7c8BBMh/CgQmq2F3wDZ # Q0biaeozADgAaCC7aOAHI+1sAoMhOm1v2WhIVmh+XXUqT9856cKwc7DUPBmzb9Sj # N5Zh+t9WCnZG7qpfxvkDF0Y/aRODMHZ1BW5L/ky9yBtyuRwXOJ6VycZTFyRkSwnN # Gd/s9IClDOP1IP5s4TSMGGdelk4lH97x7fZE/2hxn59lp761JtMxbaEceBtqaBh8 # zNMTNN/KHs8LeiIBI2ZZ+nQav452Y6XYBivQ7OdsI8xkjnjG9gfgXXjvX1TIh0ow # Hy5ZxtAtjXty49Gmjkx5VcBx4auJcnRDlLTzoZjTxq1te+gEWpw6O1EsEKasVLZe # uN6PxTOxS3nHvRvPgQc1xNUdhDRqBaYsju6b9YmMxz1uefAjGM0= # =fOTc # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Jun 2023 03:17:14 AM CEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu: (60 commits) hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. target/riscv: Smepmp: Return error when access permission not allowed in PMP target/riscv/vector_helper.c: Remove the check for extra tail elements target/riscv/vector_helper.c: clean up reference of MTYPE target/riscv: Fix initialized value for cur_pmmask util/log: Add vector registers to log docs/system: riscv: Add pflash usage details riscv/virt: Support using pflash via -blockdev option hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" target/riscv: Remove pc_succ_insn from DisasContext target/riscv: Enable PC-relative translation target/riscv: Use true diff for gen_pc_plus_diff target/riscv: Change gen_set_pc_imm to gen_update_pc target/riscv: Change gen_goto_tb to work on displacements target/riscv: Introduce cur_insn_len into DisasContext target/riscv: Fix target address to update badaddr disas/riscv.c: Remove redundant parentheses disas/riscv.c: Fix lines with over 80 characters disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions disas/riscv.c: Support disas for Z*inx extensions ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-14Merge tag 'misc-20230613' of https://github.com/philmd/qemu into stagingRichard Henderson37-91/+186
Misc patches queue - user emulation: Preserve environment variable order - macos/darwin/hvf: Fix build warnings, slighly optimize DCache flush - target/i386: Minor cleanups, rename template headers with '.inc' suffix - target/hppa: Avoid building int_helper.o on user emulation - hw: Add 'name' property to pca954x, export ISAParallelState, silent warnings - hw/vfio: Trace number of bitmap dirty pages - exec/memory: Introduce RAM_NAMED_FILE to distinct block without named backing store # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmSINukACgkQ4+MsLN6t # wN5fEQ/+PEC2CoBtl5aIODSowEyaFVmNTHZWQFmRAUlBoPR2rU7NEpnh3j4BJWSS # aKc6MV4GDExKvMS5GujXiruS3kYMyWUHSG+nGUqrkBmbWn/2tZdWfIa0uT20CTr/ # nxu8TWM/EO+uzvYdyTNrXdkBOkU5eKfAqFGcWP7uLtRkjXpvu2YcPxrKswQUFpTh # XH5sCh6esaBkMZLfsl0I4ZQLxtBWpM3EmaDvlDxftMt4OZ3kwbzC55xhN1uk6KxY # iarkROM54vqU7ZC+vWH6fT18teLvKWXo+9F1iD/Qio88xRCH/kuQRWBM8+XR9IDe # CKuaRrJ1nOmPojG3Xngd99eM7FPjh1FR6bR+L62cm8/PzuzbQi5VBIdJvxXfvoTL # OjiXA3stOVB/jZg37IAeZB2X644d1GJXcjpExpU+mk7qdkaZC16HVOTRYYQF/wFF # QBUntZ9Oz0+XRtt4PC8ckynq0p0uEA/mZ14jMm04AJ3W8XtnOk2xp5rFTn/f4tsI # fJhqHxNhfet2sU17UI/pRw/h3Ulg0TmAdmMZnz3jUQ13/6E0//+a6dqQED/5HeG5 # 6UvUEUdGfvHuyE8l1UT4p93pBcyshMuaVFfutxKP9qYGPLhYeiCvms8KfdOWhTkA # NC1JlOScwdEqkn1hyMCeJHEUpnuZHZeiOtn4VV4J/SwyxkzVRS8= # =sUgM # -----END PGP SIGNATURE----- # gpg: Signature made Tue 13 Jun 2023 11:29:13 AM CEST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'misc-20230613' of https://github.com/philmd/qemu: exec/memory: Introduce RAM_NAMED_FILE flag hw/vfio: Add number of dirty pages to vfio_get_dirty_bitmap tracepoint exec/ram_addr: Return number of dirty pages in cpu_physical_memory_set_dirty_lebitmap() hw/char/parallel-isa: Export struct ISAParallelState hw/char/parallel: Export struct ParallelState hw/scsi/megasas: Silent GCC duplicated-cond warning hw/ide/ahci: Remove stray backslash hw/i2c: Enable an id for the pca954x devices target/i386: Rename helper template headers as '.h.inc' target/i386/helper: Shuffle do_cpu_init() target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulation target/hppa/meson: Only build int_helper.o with system emulation accel/hvf: Report HV_DENIED error util/cacheflush: Avoid possible redundant dcache flush on Darwin util/cacheflush: Use declarations from <OSCacheControl.h> on Darwin cocoa: Fix warnings about invalid prototype declarations linux-user, bsd-user: Preserve incoming order of environment variables in the target Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-14hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.Tommy Wu1-2/+2
According to the `The RISC-V Advanced Interrupt Architecture` document, if register `mmsiaddrcfgh` of the domain has bit L set to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`. Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-Id: <20230609055936.3925438-1-tommy.wu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13exec/memory: Introduce RAM_NAMED_FILE flagSteve Sistare6-4/+15
migrate_ignore_shared() is an optimization that avoids copying memory that is visible and can be mapped on the target. However, a memory-backend-ram or a memory-backend-memfd block with the RAM_SHARED flag set is not migrated when migrate_ignore_shared() is true. This is wrong, because the block has no named backing store, and its contents will be lost. To fix, ignore shared memory iff it is a named file. Define a new flag RAM_NAMED_FILE to distinguish this case. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <1686151116-253260-1-git-send-email-steven.sistare@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13hw/vfio: Add number of dirty pages to vfio_get_dirty_bitmap tracepointJoao Martins2-4/+5
Include the number of dirty pages on the vfio_get_dirty_bitmap tracepoint. These are fetched from the newly added return value in cpu_physical_memory_set_dirty_lebitmap(). Signed-off-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alex Williamson <alex.williamson@redhat.com> Message-Id: <20230530180556.24441-3-joao.m.martins@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13exec/ram_addr: Return number of dirty pages in ↵Joao Martins1-6/+22
cpu_physical_memory_set_dirty_lebitmap() In preparation for including the number of dirty pages in the vfio_get_dirty_bitmap() tracepoint, return the number of dirty pages in cpu_physical_memory_set_dirty_lebitmap() similar to cpu_physical_memory_sync_dirty_bitmap(). To avoid counting twice when GLOBAL_DIRTY_RATE is enabled, stash the number of bits set per bitmap quad in a variable (@nbits) and reuse it there. Signed-off-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230530180556.24441-2-joao.m.martins@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13hw/char/parallel-isa: Export struct ISAParallelStateBernhard Beschow9-17/+37
Allows the struct to be embedded directly into device models without additional allocation. Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230612081238.1742-3-shentey@gmail.com> [PMD: Update MAINTAINERS entry and use SPDX license identifier] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13hw/char/parallel: Export struct ParallelStateBernhard Beschow2-20/+21
Exporting ParallelState is a precondition for exporing TYPE_ISA_PARALLEL to be performed in the next patch. Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230612081238.1742-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13hw/scsi/megasas: Silent GCC duplicated-cond warningPhilippe Mathieu-Daudé1-6/+10
GCC9 is confused when building with CFLAG -O3: hw/scsi/megasas.c: In function ‘megasas_scsi_realize’: hw/scsi/megasas.c:2387:26: error: duplicated ‘if’ condition [-Werror=duplicated-cond] 2387 | } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) { hw/scsi/megasas.c:2385:19: note: previously used here 2385 | if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) { cc1: all warnings being treated as errors When this device was introduced in commit e8f943c3bcc, the author cared about modularity, using a definition for the firmware limit. However if the firmware limit isn't changed (MEGASAS_MAX_SGE = 128), the code ends doing the same check twice. Per the maintainer [*]: > The original code assumed that one could change MFI_PASS_FRAME_SIZE, > but it turned out not to be possible as it's being hardcoded in the > drivers themselves (even though the interface provides mechanisms to > query it). So we can remove the duplicate lines. Add the 'MEGASAS_MIN_SGE' definition for the '64' magic value, slightly rewrite the condition check to simplify a bit the logic and remove the unnecessary / duplicated check. [*] https://lore.kernel.org/qemu-devel/e0029fc5-882f-1d63-15e3-1c3dbe9b6a2c@suse.de/ Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Hannes Reinecke <hare@suse.de> Message-Id: <20230328210126.16282-1-philmd@linaro.org>
2023-06-13hw/ide/ahci: Remove stray backslashNiklas Cassel1-1/+1
This backslash obviously does not belong here, so remove it. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: John Snow <jsnow@redhat.com> Message-Id: <20230601134434.519805-2-nks@flawful.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13hw/i2c: Enable an id for the pca954x devicesPatrick Venture1-0/+22
This allows the devices to be more readily found and specified. Without setting the name field, they can only be found by device type name, which doesn't let you specify the second of the same device type behind a bus. Tested: Verified that by default the device was findable with the name 'pca954x[77]', for an instance attached at that address. Signed-off-by: Patrick Venture <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-Id: <20230322172136.48010-1-venture@google.com> [PMD: Fix typo in property name] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13target/i386: Rename helper template headers as '.h.inc'Philippe Mathieu-Daudé6-11/+11
Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore move the included templates in the tcg/ directory and rename as '.h.inc'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230608133108.72655-5-philmd@linaro.org>
2023-06-13target/i386/helper: Shuffle do_cpu_init()Philippe Mathieu-Daudé1-8/+4
Move the #ifdef'ry inside do_cpu_init() instead of declaring an empty stub for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230602224628.59546-3-philmd@linaro.org>
2023-06-13target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulationPhilippe Mathieu-Daudé2-4/+2
Since commit 604664726f ("target/i386: Restrict cpu_exec_interrupt() handler to sysemu"), do_cpu_sipi() isn't called anymore on user emulation. Remove the now pointless stub. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230602224628.59546-2-philmd@linaro.org>
2023-06-13target/hppa/meson: Only build int_helper.o with system emulationPhilippe Mathieu-Daudé2-4/+1
int_helper.c only contains system emulation code: remove the #ifdef'ry and move the file to the meson softmmu source set. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230602223016.58647-1-philmd@linaro.org>
2023-06-13accel/hvf: Report HV_DENIED errorAntonio Caggiano1-0/+6
On MacOS 11 and subsequent versions, in case the resulting binary is not signed with the proper entitlement, handle and report the HV_DENIED error. Signed-off-by: Antonio Caggiano <quic_acaggian@quicinc.com> Message-Id: <20230608123014.28715-1-quic_acaggian@quicinc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13util/cacheflush: Avoid possible redundant dcache flush on DarwinPhilippe Mathieu-Daudé1-1/+8
<libkern/OSCacheControl.h> describes sys_icache_invalidate() as "equivalent to sys_cache_control(kCacheFunctionPrepareForExecution)", having kCacheFunctionPrepareForExecution defined as: /* Prepare memory for execution. This should be called * after writing machine instructions to memory, before * executing them. It syncs the dcache and icache. [...] */ Since the dcache is also sync'd, we can avoid the sys_dcache_flush() call when both rx/rw pointers are equal. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230605195911.96033-1-philmd@linaro.org>
2023-06-13util/cacheflush: Use declarations from <OSCacheControl.h> on DarwinPhilippe Mathieu-Daudé1-2/+2
Per the cache(3) man page, sys_icache_invalidate() and sys_dcache_flush() are declared in <libkern/OSCacheControl.h>. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230605175647.88395-2-philmd@linaro.org>
2023-06-13cocoa: Fix warnings about invalid prototype declarationsPhilippe Mathieu-Daudé2-2/+2
Fix the following Cocoa trivial warnings: C compiler for the host machine: cc (clang 14.0.0 "Apple clang version 14.0.0 (clang-1400.0.29.202)") Objective-C compiler for the host machine: clang (clang 14.0.0) [100/334] Compiling Objective-C object libcommon.fa.p/net_vmnet-bridged.m.o net/vmnet-bridged.m:40:31: warning: a function declaration without a prototype is deprecated in all versions of C [-Wstrict-prototypes] static char* get_valid_ifnames() ^ void [742/1436] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o ui/cocoa.m:1937:22: warning: a function declaration without a prototype is deprecated in all versions of C [-Wstrict-prototypes] static int cocoa_main() ^ void Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230425192820.34063-1-philmd@linaro.org>
2023-06-13linux-user, bsd-user: Preserve incoming order of environment variables in ↵Andreas Schwab2-2/+18
the target Do not reverse the order of environment variables in the target environ array relative to the incoming environ order. Some testsuites depend on a specific order, even though it is not defined by any standard. Signed-off-by: Andreas Schwab <schwab@suse.de> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <mvmlejfsivd.fsf@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-13target/riscv: Smepmp: Return error when access permission not allowed in PMPHimanshu Chauhan1-8/+2
On an address match, skip checking for default permissions and return error based on access defined in PMP configuration. v3 Changes: o Removed explicit return of boolean value from comparision of priv/allowed_priv v2 Changes: o Removed goto to return in place when address matches o Call pmp_hart_has_privs_default at the end of the loop Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when address matches") Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230605164548.715336-1-hchauhan@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/vector_helper.c: Remove the check for extra tail elementsXiao Wang1-16/+6
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") added an extra check for LMUL fragmentation, intended for setting the "rest tail elements" in the last register for a segment load insn. Actually, the max_elements derived in vext_ld*() won't be a fraction of vector register size, since the lmul encoded in desc is emul, which has already been adjusted to 1 for LMUL fragmentation case by vext_get_emul() in trans_rvv.c.inc, for ld_stride(), ld_us(), ld_index() and ldff(). Besides, vext_get_emul() has also taken EEW/SEW into consideration, so no need to call vext_get_total_elems() which would base on the emul to derive another emul, the second emul would be incorrect when esz differs from sew. Thus this patch removes the check for extra tail elements. Fixes: 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230607091646.4049428-1-xiao.w.wang@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/vector_helper.c: clean up reference of MTYPEXiao Wang1-5/+1
There's no code using MTYPE, which was a concept used in older vector implementation. Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230608053517.4102648-1-xiao.w.wang@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Fix initialized value for cur_pmmaskWeiwei Li1-2/+2
We initialize cur_pmmask as -1(UINT32_MAX/UINT64_MAX) and regard it as if pointer mask is disabled in current implementation. However, the addresses for vector load/store will be adjusted to zero in this case and -1(UINT32_MAX/UINT64_MAX) is valid value for pmmask when pointer mask is enabled. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230610094651.43786-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13util/log: Add vector registers to logIvan Klokov4-0/+8
Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230410124451.15929-2-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13docs/system: riscv: Add pflash usage detailsSunil V L1-0/+31
pflash devices can be used in virt machine for different purposes like for ROM code or S-mode FW payload. Add a section in the documentation on how to use pflash devices for different purposes. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230601045910.18646-4-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13riscv/virt: Support using pflash via -blockdev optionSunil V L1-3/+5
Currently, pflash devices can be configured only via -pflash or -drive options. This is the legacy way and the better way is to use -blockdev as in other architectures. libvirt also has moved to use -blockdev method. To support -blockdev option, pflash devices need to be created in instance_init itself. So, update the code to move the virt_flash_create() to instance_init. Also, use standard interfaces to detect whether pflash0 is configured or not. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reported-by: Andrea Bolognani <abologna@redhat.com> Tested-by: Andrea Bolognani <abologna@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230601045910.18646-3-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"Sunil V L1-32/+21
Currently, virt machine supports two pflash instances each with 32MB size. However, the first pflash is always assumed to contain M-mode firmware and reset vector is set to this if enabled. Hence, for S-mode payloads like EDK2, only one pflash instance is available for use. This means both code and NV variables of EDK2 will need to use the same pflash. The OS distros keep the EDK2 FW code as readonly. When non-volatile variables also need to share the same pflash, it is not possible to keep it as readonly since variables need write access. To resolve this issue, the code and NV variables need to be separated. But in that case we need an extra flash. Hence, modify the convention for non-KVM guests such that, pflash0 will contain the M-mode FW only when "-bios none" option is used. Otherwise, pflash0 will contain the S-mode payload FW. This enables both pflash instances available for EDK2 use. When KVM is enabled, pflash0 is always assumed to contain the S-mode payload firmware only. Example usage: 1) pflash0 containing M-mode FW qemu-system-riscv64 -bios none -pflash <mmode_fw> -machine virt or qemu-system-riscv64 -bios none \ -drive file=<mmode_fw>,if=pflash,format=raw,unit=0 -machine virt 2) pflash0 containing S-mode payload like EDK2 qemu-system-riscv64 -pflash <smode_fw_code> -pflash <smode_vars> -machine virt or qemu-system-riscv64 -bios <opensbi_fw> \ -pflash <smode_fw_code> \ -pflash <smode_vars> \ -machine virt or qemu-system-riscv64 -bios <opensbi_fw> \ -drive file=<smode_fw_code>,if=pflash,format=raw,unit=0,readonly=on \ -drive file=<smode_fw_vars>,if=pflash,format=raw,unit=1 \ -machine virt Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Andrea Bolognani <abologna@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230601045910.18646-2-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Remove pc_succ_insn from DisasContextWeiwei Li1-6/+1
pc_succ_insn is no longer useful after the introduce of cur_insn_len and all pc related value use diff value instead of absolute value. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li4-20/+74
Add a base pc_save for PC-relative translation(CF_PCREL). Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb. Use gen_pc_plus_diff to get the pc-relative address. Enable CF_PCREL in System mode. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li3-12/+9
Reduce reliance on absolute values by using true pc difference for gen_pc_plus_diff() to prepare for PC-relative translation. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li6-13/+13
Reduce reliance on absolute values(by passing pc difference) to prepare for PC-relative translation. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li2-5/+7
Reduce reliance on absolute value to prepare for PC-relative translation. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li1-1/+3
Use cur_insn_len to store the length of the current instruction to prepare for PC-relative translation. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li3-20/+28
Compute the target address before storing it into badaddr when mis-aligned exception is triggered. Use a target_pc temp to store the target address to avoid the confusing operation that udpate target address into cpu_pc before misalign check, then update it into badaddr and restore cpu_pc to current pc if exception is triggered. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Remove redundant parenthesesWeiwei Li1-109/+110
Remove redundant parenthese and fix multi-line comments. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Fix lines with over 80 charactersWeiwei Li1-61/+140
Fix lines with over 80 characters. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li1-370/+370
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector instructions are the same op index as their own. And they have no functional decomp_data. So they have no functional difference from just leaving them as zero. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li1-4/+12
Support disas for Z*inx instructions only when Zfinx extension is supported. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li1-1/+7
Support disas for Zcmt* instructions only when related extensions are supported. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li2-3/+8
Pass RISCVCPUConfig as disassemble_info.target_info to support disas of conflict instructions related to specific extensions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li2-113/+137
Split RISCVCPUConfig declarations to prepare for passing it to disas. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230523093539.203909-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas: Change type of disassemble_info.target_info to pointerWeiwei Li1-1/+1
Use pointer to pass more information of target to disasembler, such as pass cpu.cfg related information in following commits. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: smstateen knobsMayuresh Chitale1-1/+2
Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230518175058.2772506-4-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale2-3/+10
When misa.F is 0 tb->flags.FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230518175058.2772506-3-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale1-0/+15
Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec and check for it when accessing the fcsr register and its fields. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230518175058.2772506-2-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li1-1/+8
write_mstatus() can only change current xl when in debug mode. And we need update cur_pmmask/base in this case. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230524015933.17349-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Fix pointer mask transformation for vector addressWeiwei Li1-1/+1
actual_address = (requested_address & ~mpmmask) | mpmbase. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230524015933.17349-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13hw/riscv: qemu crash when NUMA nodes exceed available CPUsYin Wang1-0/+6
Command "qemu-system-riscv64 -machine virt -m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G" would trigger this problem.Backtrace with: #0 0x0000555555b5b1a4 in riscv_numa_get_default_cpu_node_id at ../hw/riscv/numa.c:211 #1 0x00005555558ce510 in machine_numa_finish_cpu_init at ../hw/core/machine.c:1230 #2 0x00005555558ce9d3 in machine_run_board_init at ../hw/core/machine.c:1346 #3 0x0000555555aaedc3 in qemu_init_board at ../softmmu/vl.c:2513 #4 0x0000555555aaf064 in qmp_x_exit_preconfig at ../softmmu/vl.c:2609 #5 0x0000555555ab1916 in qemu_init at ../softmmu/vl.c:3617 #6 0x000055555585463b in main at ../softmmu/main.c:47 This commit fixes the issue by adding parameter checks. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Yin Wang <yin.wang@intel.com> Message-Id: <20230519023758.1759434-1-yin.wang@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé2-2/+4
OpenTitanState is the 'machine' (or 'board') state: it isn't a SysBus device, but inherits from the MachineState type. Correct the instance size. Doing so we avoid leaking an OpenTitanState pointer in opentitan_machine_init(). Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230520054510.68822-6-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2025-01-31 20:33:35 +0000