aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng3-3/+15
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-2/+5
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the compatible strings for the SiFive test device node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-3/+3
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the clock name for the ethernet controller node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-07Merge remote-tracking branch ↵Peter Maydell11-14/+203
'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging A few testing and configure updates: - add the multiarch signals stress test - fix display of multi-word compiler stanzas in meson - fix quoting of multi-word compiler stazas in configure.sh - tag some acceptance tests as TCG only - make checkpatch test work harder to find clean diffs - split gprof/gconv job to avoid timeouts - fix centos8 VM build by adding --source-path - make checkpatch aware of .h.inc and .c.inc paths # gpg: Signature made Mon 07 Jun 2021 14:51:12 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-updates-070621-2: scripts/checkpatch.pl: process .c.inc and .h.inc files as C source tests/vm: expose --source-path to scripts to find extra files gitlab-ci: Split gprof-gcov job gitlab: work harder to avoid false positives in checkpatch tests/acceptance: tag various arm tests as TCG only tests/tcg/configure.sh: tweak quoting of target_compiler meson.build: fix cosmetics of compiler display tests/tcg: add a multiarch signals test to stress test signal delivery Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-07scripts/checkpatch.pl: process .c.inc and .h.inc files as C sourceMatheus Ferst1-2/+2
Change the regex used to determine whether a file should be processed as C source to include .c.inc and .h.inc extensions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210520195142.941261-1-matheus.ferst@eldorado.org.br> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-06-07tests/vm: expose --source-path to scripts to find extra filesAlex Bennée3-1/+6
Currently the centos8 image expects to run an in-src build to find the kick starter file. Fix this. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210602103527.32021-1-alex.bennee@linaro.org>
2021-06-07gitlab-ci: Split gprof-gcov jobPhilippe Mathieu-Daudé1-3/+14
This job is hitting the 70min limit, so split it in 2 tasks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210525082556.4011380-7-f4bug@amsat.org>
2021-06-07gitlab: work harder to avoid false positives in checkpatchAlex Bennée1-1/+5
This copies the behaviour of patchew's configuration to make the diff algorithm generate a minimal diff. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210602153247.27651-1-alex.bennee@linaro.org>
2021-06-07tests/acceptance: tag various arm tests as TCG onlyAlex Bennée1-0/+18
We should never be trying to run most of these models under a KVM environment. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210527160319.19834-7-alex.bennee@linaro.org>
2021-06-07tests/tcg/configure.sh: tweak quoting of target_compilerAlex Bennée1-3/+3
If you configure the host compiler with a multi-command stanza like: --cc="ccache gcc" then the configure.sh machinery falls over with confusion. Work around this by ensuring we correctly quote so where we need a complete evaluation we get it. Of course the has() check needs single variable so we need to unquote that. This does mean it essentially checks that just the ccache command exits but if we got past that step we still check the compiler actually does something. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Message-Id: <20210527160319.19834-4-alex.bennee@linaro.org>
2021-06-07meson.build: fix cosmetics of compiler displayAlex Bennée1-4/+4
If you specify something like --cc="ccache gcc" on your configure line the summary output misses the rest of the cmd_array. Do some string joining to make it complete. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527160319.19834-3-alex.bennee@linaro.org>
2021-06-07tests/tcg: add a multiarch signals test to stress test signal deliveryAlex Bennée2-0/+151
This adds a simple signal test that combines the POSIX timer_create with signal delivery across multiple threads. The aim is to provide a bit more of a stress test to flush out signal handling issues for easily than the occasional random crash we sometimes see in linux-test or threadcount. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527160319.19834-2-alex.bennee@linaro.org>
2021-06-05Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' ↵Peter Maydell14-79/+1001
into staging Host vector support for arm neon. # gpg: Signature made Fri 04 Jun 2021 19:56:59 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210604: tcg/arm: Implement TCG_TARGET_HAS_rotv_vec tcg/arm: Implement TCG_TARGET_HAS_roti_vec tcg/arm: Implement TCG_TARGET_HAS_shv_vec tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec tcg/arm: Implement TCG_TARGET_HAS_minmax_vec tcg/arm: Implement TCG_TARGET_HAS_sat_vec tcg/arm: Implement TCG_TARGET_HAS_mul_vec tcg/arm: Implement TCG_TARGET_HAS_shi_vec tcg/arm: Implement andc, orc, abs, neg, not vector operations tcg/arm: Implement minimal vector operations tcg/arm: Implement tcg_out_dup*_vec tcg/arm: Implement tcg_out_mov for vector types tcg/arm: Implement tcg_out_ld/st for vector types tcg/arm: Add host vector framework tcg: Change parameters for tcg_target_const_match Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_rotv_vecRichard Henderson1-1/+34
Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_roti_vecRichard Henderson3-0/+17
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_shv_vecRichard Henderson2-1/+63
The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson3-3/+22
NEON has 3 instructions implementing this 4 argument operation, with each insn overlapping a different logical input onto the destination register. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2-1/+25
This is minimum and maximum, signed and unsigned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2-1/+25
This is saturating add and subtract, signed and unsigned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2-1/+7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_shi_vecRichard Henderson2-1/+28
This consists of the three immediate shifts: shli, shri, sari. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement andc, orc, abs, neg, not vector operationsRichard Henderson3-5/+44
These logical and arithmetic operations are optional, but are trivial to accomplish with the existing infrastructure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement minimal vector operationsRichard Henderson4-6/+202
Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement tcg_out_dup*_vecRichard Henderson1-8/+275
Most of dupi is copied from tcg/aarch64, which has the same encoding for AdvSimdExpandImm. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement tcg_out_mov for vector typesRichard Henderson1-6/+46
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement tcg_out_ld/st for vector typesRichard Henderson1-6/+64
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Add host vector frameworkRichard Henderson5-24/+158
Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg: Change parameters for tcg_target_const_matchRichard Henderson10-36/+12
Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector constants. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell13-134/+298
staging * OpenBSD cleanup (Brad) * fixes for the i386 accel/cpu refactoring (Claudio) * unmap test for emulated SCSI (Kit) * fix for iscsi module (myself) * fix for -readconfig of objects (myself) * fixes for x86 16-bit task switching (myself) * fix for x86 MOV from/to CR8 (Richard) # gpg: Signature made Fri 04 Jun 2021 12:53:32 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: vl: plug -object back into -readconfig vl: plumb keyval-based options into -readconfig qemu-config: parse configuration files to a QDict i386: run accel_cpu_instance_init as post_init i386: reorder call to cpu_exec_realizefn tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks test target/i386: Fix decode of cr8 target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa target/i386: tcg: fix loading of registers from 16-bit TSS target/i386: tcg: fix segment register offsets for 16-bit TSS oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure iscsi: link libm into the module meson: allow optional dependencies for block modules Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell27-4/+1607
staging # gpg: Signature made Fri 04 Jun 2021 08:26:16 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: MAINTAINERS: Added eBPF maintainers information. docs: Added eBPF documentation. virtio-net: Added eBPF RSS to virtio-net. ebpf: Added eBPF RSS loader. ebpf: Added eBPF RSS program. net: Added SetSteeringEBPF method for NetClientState. net/tap: Added TUNSETSTEERINGEBPF code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04vl: plug -object back into -readconfigPaolo Bonzini1-6/+18
Commit bc2f4fcb1d ("qom: move user_creatable_add_opts logic to vl.c and QAPIfy it", 2021-03-19) switched the creation of objects from qemu_opts_foreach to a bespoke QTAILQ in preparation for supporting JSON syntax in -object. Unfortunately in doing so it lost support for [object] stanzas in configuration files and also for "-set object.ID.KEY=VAL". The latter is hard to re-establish and probably best solved by deprecating -set. This patch uses the infrastructure introduced by the previous two patches in order to parse QOM objects correctly from configuration files. Cc: Markus Armbruster <armbru@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210524105752.3318299-4-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04vl: plumb keyval-based options into -readconfigPaolo Bonzini3-26/+62
Let -readconfig support parsing command line options into QDict or QemuOpts. This will be used to add back support for objects in -readconfig. Cc: Markus Armbruster <armbru@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210524105752.3318299-3-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04qemu-config: parse configuration files to a QDictPaolo Bonzini3-33/+76
Change the parser to put the values into a QDict and pass them to a callback. qemu_config_parse's QemuOpts creation is itself turned into a callback function. This is useful for -readconfig to support keyval-based options; getting a QDict from the parser removes a roundtrip from QDict to QemuOpts and then back to QDict. Unfortunately there is a disadvantage in that semantic errors will point to the last line of the group, because the entries of the QDict do not have a location attached. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210524105752.3318299-2-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04i386: run accel_cpu_instance_init as post_initClaudio Fontana1-3/+7
This fixes host and max cpu initialization, by running the accel cpu initialization only after all instance init functions are called for all X86 cpu subclasses. The bug this is fixing is related to the "max" and "host" i386 cpu subclasses, which set cpu->max_features, which is then used at cpu realization time. In order to properly split the accel-specific max features code that needs to be executed at cpu instance initialization time, we cannot call the accel cpu initialization at the end of the x86 base class initialization, or we will have no way to specialize "max features" cpu behavior, overriding the "max" cpu class defaults, and checking for the "max features" flag itself. This patch moves the accel-specific cpu instance initialization to after all x86 cpu instance code has been executed, including subclasses, so that proper initialization of cpu "host" and "max" can be restored. Fixes: f5cc5a5c ("i386: split cpu accelerators from cpu.c,"...) Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210603123001.17843-3-cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04i386: reorder call to cpu_exec_realizefnClaudio Fontana2-30/+61
i386 realizefn code is sensitive to ordering, and recent commits aimed at refactoring it, splitting accelerator-specific code, broke assumptions which need to be fixed. We need to: * process hyper-v enlightements first, as they assume features not to be expanded * only then, expand features * after expanding features, attempt to check them and modify them in the accel-specific realizefn code called by cpu_exec_realizefn(). * after the framework has been called via cpu_exec_realizefn, the code can check for what has or hasn't been set by accel-specific code, or extend its results, ie: - check and evenually set code_urev default - modify cpu->mwait after potentially being set from host CPUID. - finally check for phys_bits assuming all user and accel-specific adjustments have already been taken into account. Fixes: f5cc5a5c ("i386: split cpu accelerators from cpu.c"...) Fixes: 30565f10 ("cpu: call AccelCPUClass::cpu_realizefn in"...) Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210603123001.17843-2-cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks testKit Westneat1-0/+51
Add test for issue #345 Signed-off-by: Kit Westneat <kit.westneat@gmail.com> Message-Id: <20210603142022.676395-1-kit.westneat@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04target/i386: Fix decode of cr8Richard Henderson1-0/+1
A recent cleanup did not recognize that there are two ways to encode cr8: one via the LOCK and the other via REX. Fixes: 7eff2e7c Resolves: https://gitlab.com/qemu-project/qemu/-/issues/380 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210602035511.96834-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versaPaolo Bonzini1-1/+1
The format of the task state segment is governed by bit 3 in the descriptor type field. On a task switch, the format for saving is given by the current value of TR's type field, while the format for loading is given by the new descriptor. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04target/i386: tcg: fix loading of registers from 16-bit TSSPaolo Bonzini1-14/+11
According to the manual, the high 16-bit of the registers are preserved when switching to a 16-bit task. Implement this in switch_tss_ra. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04target/i386: tcg: fix segment register offsets for 16-bit TSSPaolo Bonzini1-2/+2
The TSS offsets in the manuals have only 2-byte slots for the segment registers. QEMU incorrectly uses 4-byte slots, so that SS overlaps the LDT selector. Resolves: #382 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, ↵Brad Smith1-11/+0
O_NONBLOCK) failure OpenBSD prior to 6.3 required a workaround to utilize fcntl(F_SETFL) on memory devices. Since modern verions of OpenBSD that are only officialy supported and buildable on do not have this issue I am garbage collecting this workaround. Signed-off-by: Brad Smith <brad@comstyle.com> Message-Id: <YGYECGXQhdamEJgC@humpty.home.comstyle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04iscsi: link libm into the modulePaolo Bonzini2-3/+3
Depending on the configuration of QEMU, some binaries might not need libm at all. In that case libiscsi, which uses exp(), will fail to load. Link it in the module explicitly. Reported-by: Yi Sun <yisun@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04meson: allow optional dependencies for block modulesPaolo Bonzini1-9/+9
Right now all dependencies for block modules are passed to module_ss.add(when: ...), so they are mandatory. In the next patch we will need to add a libm dependency to a module, but libm does not exist on all systems. So, modify the creation of module_ss and modsrc so that dependencies can also be passed to module_ss.add(if_true: ...). While touching the array, remove the useless dependency of the curl module on glib. glib is always linked in QEMU and in fact all other block modules also need it, but they don't have to specify it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fpu-20210603' ↵Peter Maydell15-3814/+2165
into staging Finish conversion of float128 and floatx80 to FloatParts. Implement float128_muladd and float128_{min,max}*. Optimize int-to-float conversion with hard-float. # gpg: Signature made Thu 03 Jun 2021 22:13:10 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-fpu-20210603: (29 commits) softfloat: Use hard-float for {u}int64_to_float{32,64} tests/fp: Enable more tests softfloat: Convert modrem operations to FloatParts softfloat: Move floatN_log2 to softfloat-parts.c.inc softfloat: Convert float32_exp2 to FloatParts softfloat: Convert floatx80 compare to FloatParts softfloat: Convert floatx80_scalbn to FloatParts softfloat: Convert floatx80 to integer to FloatParts softfloat: Convert floatx80 float conversions to FloatParts softfloat: Convert integer to floatx80 to FloatParts softfloat: Convert floatx80_round_to_int to FloatParts softfloat: Convert floatx80_round to FloatParts softfloat: Convert floatx80_sqrt to FloatParts softfloat: Convert floatx80_div to FloatParts softfloat: Convert floatx80_mul to FloatParts softfloat: Convert floatx80_add/sub to FloatParts tests/fp/fp-test: Reverse order of floatx80 precision tests softfloat: Adjust parts_uncanon_normal for floatx80 softfloat: Introduce Floatx80RoundPrec softfloat: Reduce FloatFmt ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04MAINTAINERS: Added eBPF maintainers information.Andrew Melnychenko1-0/+8
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2021-06-04docs: Added eBPF documentation.Andrew Melnychenko2-0/+126
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2021-06-04virtio-net: Added eBPF RSS to virtio-net.Andrew Melnychenko4-3/+122
When RSS is enabled the device tries to load the eBPF program to select RX virtqueue in the TUN. If eBPF can be loaded the RSS will function also with vhost (works with kernel 5.8 and later). Software RSS is used as a fallback with vhost=off when eBPF can't be loaded or when hash population requested by the guest. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2021-06-04ebpf: Added eBPF RSS loader.Andrew Melnychenko10-1/+718
Added function that loads RSS eBPF program. Added stub functions for RSS eBPF loader. Added meson and configuration options. By default, eBPF feature enabled if libbpf is present in the build system. libbpf checked in configuration shell script and meson script. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2021-06-04ebpf: Added eBPF RSS program.Andrew Melnychenko2-0/+592
RSS program and Makefile to build it. The bpftool used to generate '.h' file. The data in that file may be loaded by libbpf. EBPF compilation is not required for building qemu. You can use Makefile if you need to regenerate rss.bpf.skeleton.h. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2021-06-04net: Added SetSteeringEBPF method for NetClientState.Andrew Melnychenko7-0/+40
For now, that method supported only by Linux TAP. Linux TAP uses TUNSETSTEERINGEBPF ioctl. Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
generated by cgit v1.1 at 2025-01-08 04:15:34 +0000