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2019-09-20ipmi: Add a UUID device propertyCorey Minyard2-11/+21
2019-09-20qdev: Add a no default uuid propertyCorey Minyard1-0/+7
2019-09-20tests:ipmi: Fix IPMI BT testsCorey Minyard2-4/+5
2019-09-20ipmi: Generate an interrupt on watchdog pretimeout expiryCorey Minyard1-1/+3
2019-09-20ipmi: Fix the get watchdog commandCorey Minyard1-0/+2
2019-09-20ipmi: Fix watchdog NMI handlingCorey Minyard2-4/+4
2019-09-19Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190919-pull-request' i...Peter Maydell13-169/+1409
2019-09-19Merge remote-tracking branch 'remotes/kraxel/tags/ati-20190919-pull-request' ...Peter Maydell4-35/+60
2019-09-19Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...Peter Maydell10-12/+23
2019-09-19Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3...Peter Maydell41-444/+1366
2019-09-19ati: use vga_read_byte in ati_cursor_defineGerd Hoffmann1-9/+10
2019-09-19vga: move access helpers to separate include fileGerd Hoffmann3-26/+50
2019-09-18trace: Forbid event format ending with newline characterPhilippe Mathieu-Daudé2-0/+5
2019-09-18trace: Remove trailing newline in eventsPhilippe Mathieu-Daudé5-12/+12
2019-09-18loader: Trace loaded imagesAlexey Kardashevskiy3-0/+6
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic1-2/+4
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis1-1/+1
2019-09-17target/riscv: Fix mstatus dirty maskAlistair Francis1-1/+1
2019-09-17target/riscv: Use both register name and ABI nameAtish Patra1-8/+11
2019-09-17riscv: sifive_u: Update model and compatible strings in device treeBin Meng1-2/+3
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2-25/+2
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng3-5/+23
2019-09-17riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2-0/+12
2019-09-17riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng3-0/+272
2019-09-17riscv: roms: Update default bios for sifive_u machineBin Meng2-2/+2
2019-09-17riscv: sifive_u: Change UART node name in device treeBin Meng1-1/+1
2019-09-17riscv: sifive_u: Update UART base addresses and IRQsBin Meng2-4/+4
2019-09-17riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2-3/+14
2019-09-17riscv: sifive_u: Add PRCI block to the SoCBin Meng2-1/+26
2019-09-17riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2-0/+25
2019-09-17riscv: sifive: Implement PRCI model for FU540Bin Meng3-0/+251
2019-09-17riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng1-3/+4
2019-09-17riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2-26/+72
2019-09-17riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2-1/+6
2019-09-17riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2-1/+3
2019-09-17riscv: hart: Extract hart realize to a separate routineBin Meng1-13/+20
2019-09-17riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng3-12/+33
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2-15/+9
2019-09-17riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2-1/+3
2019-09-17riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng1-1/+1
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng5-114/+111
2019-09-17riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng1-1/+0
2019-09-17riscv: roms: Remove executable attribute of opensbi imagesBin Meng3-0/+0
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng3-3/+0
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng3-9/+13
2019-09-17riscv: hw: Change create_fdt() to return voidBin Meng2-14/+8
2019-09-17riscv: hw: Remove not needed PLIC properties in device treeBin Meng2-4/+0
2019-09-17riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2-21/+21
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng3-8/+0
2019-09-17riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng2-2/+0