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2023-01-17tcg/arm: Implement direct branch for goto_tbRichard Henderson1-15/+37
Now that tcg can handle direct and indirect goto_tb simultaneously, we can optimistically leave space for a direct branch and fall back to loading the pointer from the TB for an indirect branch. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/sparc64: Reorg goto_tb implementationRichard Henderson1-50/+37
The old sparc64 implementation may replace two insns, which leaves a race condition in which a thread could be stopped at a PC in the middle of the sequence, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between a direct branch and a direct call. The TCG_REG_TB register is loaded from tb->jmp_target_addr[] in the delay slot. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/sparc64: Remove USE_REG_TBRichard Henderson1-41/+21
This is always true for sparc64, so this is dead since 3a5f6805c7ca. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/ppc: Reorg goto_tb implementationRichard Henderson2-114/+41
The old ppc64 implementation replaces 2 or 4 insns, which leaves a race condition in which a thread could be stopped at a PC in the middle of the sequence, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between b <dest> and mtctr r31 falling through to a general-case indirect branch. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/aarch64: Reorg goto_tb implementationRichard Henderson2-39/+29
The old implementation replaces two insns, swapping between b <dest> nop br x30 and adrp x30, <dest> addi x30, x30, lo12:<dest> br x30 There is a race condition in which a thread could be stopped at the PC of the second insn, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between b <dest> br tmp and ldr tmp, <jmp_addr> br tmp Reported-by: hev <r@hev.cc> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Remove TCG_TARGET_HAS_direct_jumpRichard Henderson17-27/+14
We now have the option to generate direct or indirect goto_tb depending on the dynamic displacement, thus the define is no longer necessary or completely accurate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Always define tb_target_set_jmp_targetRichard Henderson4-0/+24
Install empty versions for !TCG_TARGET_HAS_direct_jump hosts. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Move tb_target_set_jmp_target declaration to tcg.hRichard Henderson11-40/+3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Change tb_target_set_jmp_target argumentsRichard Henderson17-36/+61
Replace 'tc_ptr' and 'addr' with 'tb' and 'n'. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Add TranslationBlock.jmp_insn_offsetRichard Henderson3-6/+8
Stop overloading jmp_target_arg for both offset and address, depending on TCG_TARGET_HAS_direct_jump. Instead, add a new field to hold the jump insn offset and always set the target address in jmp_target_addr[]. This will allow a tcg backend to use either direct or indirect depending on displacement. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Add gen_tb to TCGContextRichard Henderson4-27/+14
This can replace four other variables that are references into the TranslationBlock structure. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Rename TB_JMP_RESET_OFFSET_INVALID to TB_JMP_OFFSET_INVALIDRichard Henderson3-7/+7
This will shortly be used for more than reset. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Split out tcg_out_goto_tbRichard Henderson11-171/+197
The INDEX_op_goto_tb opcode needs no register allocation. Split out a dedicated helper function for it. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Introduce get_jmp_target_addrRichard Henderson5-4/+13
Similar to the existing set_jmp_reset_offset. Include the rw->rx address space conversion done by arm and s390x, and forgotten by mips and riscv. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Introduce set_jmp_insn_offsetRichard Henderson7-14/+19
Similar to the existing set_jmp_reset_offset. Move any assert for TCG_TARGET_HAS_direct_jump into the new function (which now cannot be build-time). Will be unused if TCG_TARGET_HAS_direct_jump is constant 0, but we can't test for constant in the preprocessor, so just mark it G_GNUC_UNUSED. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Replace asserts on tcg_jmp_insn_offsetRichard Henderson6-6/+6
Test TCG_TARGET_HAS_direct_jump instead of testing an implementation pointer. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/sparc64: Remove unused goto_tb code for indirect jumpRichard Henderson1-29/+12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/ppc: Remove unused goto_tb code for indirect jumpRichard Henderson1-19/+13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg/i386: Remove unused goto_tb code for indirect jumpRichard Henderson1-9/+5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17tcg: Split out tcg_out_exit_tbRichard Henderson11-97/+121
The INDEX_op_exit_tb opcode needs no register allocation. Split out a dedicated helper function for it. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-17Merge tag 'pull-tcg-20230116' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell19-101/+763
- Reorg cpu_tb_exec around setjmp. - Use __attribute__((target)) for buffer_is_zero. - Add perfmap and jitdump for perf support. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPFtXgdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+62Af/YLdd77+IO8wcPN1n # 2esKNlrrYQ2/x40Hede6L4pp+Qz6M810YgNbhMchBS3u8YGIFzmVLaiz5N4nBGTq # ricOit6Jj2KonlxWaxgma1BW36ydBIwphC20WjrLTVgdNGvxmy4JKbfklTd4oIZ+ # +Kf1VTN1bbt7vfDntd454ck2rhtVZBEvYTynikA3LJ1W7EVN5etDUnrN3VwbaTTK # 0aY8MbDfGUASyrDzmaRcF5F90K+V2STuEUs1whgOuTBusZ6n3+FSDhW8CuDhsy/l # rXtPkQba3rtUWfJ1+o7bx3Gg4nbfn/9lxIfGwhQ79ywD9InjqLqu9etwVyhijx+n # k+tvPw== # =xFfF # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 Jan 2023 20:37:12 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230116' of https://gitlab.com/rth7680/qemu: accel/tcg: Split out cpu_exec_{setjmp,loop} util/bufferiszero: Use __attribute__((target)) for avx2/avx512 tcg: add perfmap and jitdump accel/tcg: Add debuginfo support linux-user: Clean up when exiting due to a signal Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16accel/tcg: Split out cpu_exec_{setjmp,loop}Richard Henderson1-57/+54
Recently the g_assert(cpu == current_cpu) test has been intermittently failing with gcc. Reorg the code around the setjmp to minimize the lifetime of the cpu variable affected by the setjmp. This appears to fix the existing issue with clang as well. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1147 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16util/bufferiszero: Use __attribute__((target)) for avx2/avx512Richard Henderson2-41/+8
Use the attribute, which is supported by clang, instead of the #pragma, which is not supported and, for some reason, also not detected by the meson probe, so we fail by -Werror. Include only <immintrin.h> as that is the outermost "official" header for these intrinsics -- emmintrin.h and smmintrin -- are older SSE2 and SSE4 specific headers, while the immintrin.h includes all of the Intel intrinsics. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16tcg: add perfmap and jitdumpIlya Leoshkevich10-0/+505
Add ability to dump /tmp/perf-<pid>.map and jit-<pid>.dump. The first one allows the perf tool to map samples to each individual translation block. The second one adds the ability to resolve symbol names, line numbers and inspect JITed code. Example of use: perf record qemu-x86_64 -perfmap ./a.out perf report or perf record -k 1 qemu-x86_64 -jitdump ./a.out DEBUGINFOD_URLS= perf inject -j -i perf.data -o perf.data.jitted perf report -i perf.data.jitted Co-developed-by: Vanderson M. do Rosario <vandersonmr2@gmail.com> Co-developed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230112152013.125680-4-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16accel/tcg: Add debuginfo supportIlya Leoshkevich7-0/+191
Add libdw-based functions for loading and querying debuginfo. Load debuginfo from the system and the linux-user loaders. This is useful for the upcoming perf support, which can then put human-readable guest symbols instead of raw guest PCs into perfmap and jitdump files. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230112152013.125680-3-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16linux-user: Clean up when exiting due to a signalIlya Leoshkevich1-3/+5
When exiting due to an exit() syscall, qemu-user calls preexit_cleanup(), but this is currently not the case when exiting due to a signal. This leads to various buffers not being flushed (e.g., for gprof, for gcov, and for the upcoming perf support). Add the missing call. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230112152013.125680-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16Merge tag 'm68k-next-pull-request' of https://github.com/vivier/qemu-m68k ↵Peter Maydell1-18/+31
into staging M68K pull request 20230116 fix FPSR quotient byte # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmPFFmsSHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748Dk4P+QH1tlWGWzOiuKZOSUjdJ3NDEw+xpGhH # oS7I7swiz30RCJUJx9R2nL7u5lBN7kcP0duNDp58gwkmReuotrx5HYeN4WwTh/94 # 78CWDKMMT59ag0dA+41WxhXE2sQ6uVgDTtSXTH/1c4rCEm1NuXa+LGBD8oh0IxxW # K0/OHfySQvK3mLRrZtx8h6Ug77Hj5AjYKJZ1tONAe0SkcTe/qXkA4npluVnJl+TQ # /M31uzAD98Td0tSd6YxACkpV++JqEF6Uenbe0iT4A1izRa6GJb56xp+ENeUCavpD # vh5MmJeqTfe/jvdzjWqLv0v88Z+U/TQ8VvvBAUn7aThVo5f/Njclkaxx/i581zpE # pT6jCMxZYKCFdXH+QFqX6B9YBa0fTUxwynWQovIs9bwuWfRYA9IvHLCSWUZHZITi # GQSPbioPcIi4Hc/EJMeRhnZl/9TcGE0tnc+Agib/WI5QaE8Hmj26b7+5v3vxgqQV # vZ3HWOFSZ4sK3MoIsYoKqoRhFX8DtMqXsf70xKBWn5Yx1kol7vz34UYisLaQFJPZ # NBKtVPbyAbMP37h7OMzToiGWw0pitgAERHoj7Qq0juT7U9mjfV/xacdniLMPbSUq # UKzEYgEBNU1728A2TKJUZiXwrdQOx/nZQwJljYMG5RE9ePkhPJ3UvRWMRdxopT+f # 3Lvgvj+qZ8Aq # =VVZK # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 Jan 2023 09:18:35 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'm68k-next-pull-request' of https://github.com/vivier/qemu-m68k: target/m68k: fix FPSR quotient byte for frem instruction target/m68k: fix FPSR quotient byte for fmod instruction target/m68k: pass sign directly into make_quotient() target/m68k: pass quotient directly into make_quotient() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16tests/qtest/qom-test: Do not print tested properties by defaultThomas Huth1-1/+11
We're still running into the problem that some logs are cut in the gitlab-CI since they got too big. The biggest part of the log is still the output of the qom-test. Let's stop printing the properties by default to get to a saner size here. The full output can still be enabled by setting V=2 (or higher) in the environment. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221215153036.422362-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16Merge tag 'mips-20230113' of https://github.com/philmd/qemu into stagingPeter Maydell62-622/+690
MIPS patches queue A bunch of cleanups from various people. - Improved GT64120 on big-endian hosts - GT64120 north bridge and MC146818 RTC devices are now target independent - Bonito64 north bridge converted to 3-phase reset API - PCI refactors around PIIX devices - Support for nanoMIPS in bootloader generator API - New YAMON Malta Avocado test - Removal of 'trap and emulate' KVM support - System-specific QMP commands restricted to system emulation # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmPBekAACgkQ4+MsLN6t # wN4wjxAAtYxyt6WUBpiYfV/LnbQFpAsacues1Vhy9MPYEg5a/iuXWKvWtgRYvGww # qR0GVQH8rH7tgnCZK+ioq9jX+hvfBskP6CnKhxmb5zDGm7vP7jhhu8UFWY/EtBgq # 0zpNeLMXtnRJ6PBqo/nWFCVtcpDRZ6IkSbpGWkVkciRFc5n/2VCnlIj8k2I1oMvL # 11cp2xFQnaPReFXIpMjJHuHv1NObykdlvVg6wQo/A/4qIb8EvJQEPmePjG9Sf0i0 # v2dhnnxG9mze7+uq0dIC16x8Azko3N7dmtNlBU/aGb9OELwx35aux2M4dNDVogwn # DqL/Wsk54TFewECOfS48t/a/TqV8j/ISW1d/JvovBrN2KovmIAbtqHuMUqKVk5l0 # 23ZOIIPIYwmScZwIlkCIGUuIzFig1zhEmQcoEQaFe/B0oLB2eN/x0Bk9Yklo+i2A # WNiyiAj7k5492qEdndOySEEDVt6886F/+CdQ6QYF5Z1L/ELck7XHBH3mGDznWpPn # 6IURyVquPJx7ul62jSGI+Gc+qakNoahIhPo5O7hklOM9GwWNOWXHveyb7xjs7j+O # eWyVcet+o7hoHkCzmfbyTPySI4qCpF9fA42jqPhATwQPwmGXpbr+4BxUq3KtE43y # w9tEigwd4voN3dWLItVh6QE4in70osz3XHp93byvo8bHlS0huVY= # =oXX+ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 15:35:28 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-20230113' of https://github.com/philmd/qemu: (46 commits) scripts/git.orderfile: Display MAINTAINERS changes first target/mips: Restrict 'qapi-commands-machine.h' to system emulation hw/mips/boston: Rename MachineState 'mc' pointer to 'ms' hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code hw/pci-host/bonito: Convert to 3-phase reset softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818 hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent hw/core/qdev-properties-system: Allow the 'slew' policy only on x86 hw/intc: Extract the IRQ counting functions into a separate file hw/intc/i8259: Make using the isa_pic singleton more type-safe hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() hw/pci/pci_host: Trace config accesses on unexisting functions mips: Always include nanomips disassembler mips: Remove support for trap and emulate KVM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16target/m68k: fix FPSR quotient byte for frem instructionMark Cave-Ayland1-10/+19
The FPSR quotient byte should be set to the value of the quotient and not the result. Manually calculate the quotient in the frem helper in round to nearest even mode (note this is different from the quotient calculated internally for fmod), and use it to set the quotient byte accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1314 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114232959.118224-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-16target/m68k: fix FPSR quotient byte for fmod instructionMark Cave-Ayland1-5/+4
The FPSR quotient byte should be set to the value of the quotient and not the result. Switch from using floatx80_mod() to floatx80_modrem() which returns the quotient as a uint64_t which can be used for the quotient byte. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114232959.118224-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-16target/m68k: pass sign directly into make_quotient()Mark Cave-Ayland1-10/+13
This enables the quotient parameter to be changed from int32_t to uint32_t and also allows the extra sign logic in make_quotient() to be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230114232959.118224-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-16target/m68k: pass quotient directly into make_quotient()Mark Cave-Ayland1-9/+11
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114232959.118224-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-13scripts/git.orderfile: Display MAINTAINERS changes firstPhilippe Mathieu-Daudé1-0/+2
If we get custom to see MAINTAINERS changes first, we might catch missing MAINTAINERS updates easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221216225505.26052-1-philmd@linaro.org>
2023-01-13target/mips: Restrict 'qapi-commands-machine.h' to system emulationPhilippe Mathieu-Daudé3-29/+40
Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Extract the QMP functions from cpu.c (which is always compiled) to the new 'sysemu/mips-qmp-cmds.c' unit (which is only compiled when system emulation is selected). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221219211034.70491-4-philmd@linaro.org>
2023-01-13hw/mips/boston: Rename MachineState 'mc' pointer to 'ms'Daniel Henrique Barboza1-2/+2
Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instance in create_fdt() where we're calling it 'mc'. Cc: Paul Burton <paulburton@kernel.org> Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20230111172133.334735-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in headerPhilippe Mathieu-Daudé3-3/+20
Declare the TYPE_BONITO_PCI_HOST_BRIDGE QOM type in a header to be able to access it from board code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-8-philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 codePhilippe Mathieu-Daudé1-6/+6
To make it easier to differentiate between the Host Bridge object and its PCI function #0, rename bonito* as bonito_pci*. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-4-philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge codePhilippe Mathieu-Daudé1-6/+6
To make it easier to differentiate between the Host Bridge object and its PCI function #0, rename bonito_pcihost* as bonito_host*. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-3-philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Convert to 3-phase resetPhilippe Mathieu-Daudé1-5/+4
Convert the TYPE_PCI_BONITO class to use 3-phase reset. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-2-philmd@linaro.org>
2023-01-13softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818Thomas Huth1-1/+5
The 'slew' lost tick policy is only available on systems with a mc146818 RTC. On other systems, "-rtc driftfix=slew" is currently silently ignored. Let's emit at least a warning in this case to make the users aware that there is something wrong in their command line settings. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230110095351.611724-5-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/rtc/mc146818rtc: Make the mc146818 RTC device target independentThomas Huth3-16/+2
The only reason for this code being target dependent was the IRQ-counting related code in rtc_policy_slew_deliver_irq(). Since these functions have been moved into a new, separate file (kvm_irqcount.c) which is now always compiled and linked if necessary, we can get rid of the #ifdef TARGET_I386 switches in mc146818rtc.c and declare it in the softmmu_ss instead of specific_ss, so that the code only gets compiled once for all targets. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230110095351.611724-4-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/core/qdev-properties-system: Allow the 'slew' policy only on x86Thomas Huth1-1/+27
The 'slew' tick policy is currently enforced to be only available on x86 via some "#ifdef TARGET_I386" statements in mc146818rtc.c. We want to get rid of those #ifdefs, so we need a different way of checking whether the policy is allowed or not. Using the setter function in hw/core/qdev-properties-system.c seems to be a good place, so let's add a check here. Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20230110095351.611724-3-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/intc: Extract the IRQ counting functions into a separate fileThomas Huth11-43/+81
These IRQ counting functions will soon be required in binaries that do not include the APIC code, too, so let's extract them into a separate file that can be linked independently of the APIC code. While we're at it, change the apic_* prefix into kvm_* since the functions are used from the i8259 PIC (i.e. not the APIC), too. Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230110095351.611724-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/intc/i8259: Make using the isa_pic singleton more type-safeBernhard Beschow3-10/+8
This even spares some casts in hot code paths along the way. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-10-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/usb/hcd-uhci: Introduce TYPE_ defines for device modelsBernhard Beschow5-16/+22
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221204190553.3274-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/mips/Kconfig: Track Malta's PIIX dependencies via KconfigBernhard Beschow2-2/+1
Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230109172347.1830-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specificBernhard Beschow2-26/+27
pci_map_irq_fn's in general seem to be board-specific, and PIIX4's pci_slot_get_pirq() in particular seems very Malta-specific. So move the latter to malta.c to 1/ keep the board logic in one place and 2/ avoid PIIX4 to make assumptions about its board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specificBernhard Beschow2-13/+15
pci_map_irq_fn's in general seem to be board-specific. So move PIIX3's pci_slot_get_pirq() to board code to not have PIIX3 make assuptions about its board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()Bernhard Beschow9-16/+27
pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and pci_map_irq_fn to a PCI bus. This coupling gets in the way when the pci_map_irq_fn is board-specific while the pci_set_irq_fn is device- specific. For example, both of QEMU's PIIX south bridge models have different pci_map_irq_fn implementations which are board-specific rather than device-specific. These implementations should therefore reside in board code. The pci_set_irq_fn's, however, should stay in the device models because they access memory internal to the model. Factoring out pci_bus_map_irqs() from pci_bus_irqs() allows the assignments to be decoupled, resolving the problem described above. Note also how pci_vpb_realize() which gets touched in this commit assigns different pci_map_irq_fn's depending on the board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-5-shentey@gmail.com> [PMD: Factor out in vfu_object_set_bus_irq()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
generated by cgit v1.1 at 2025-01-01 18:10:46 +0000