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2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
5
-166
/
+59
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
4
-51
/
+25
2020-11-09
target/riscv: Set the virtualised MMU mode when doing hyp accesses
Alistair Francis
1
-13
/
+17
2020-11-09
target/riscv: Add a virtualised MMU Mode
Alistair Francis
3
-3
/
+14
2020-11-04
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201104-pull-request' i...
Peter Maydell
6
-17
/
+45
2020-11-04
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20201104-pull-request' ...
Peter Maydell
2
-131
/
+216
2020-11-04
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-fixes-20201103'...
Peter Maydell
30
-373
/
+32
2020-11-04
console: make QMP/HMP screendump run in coroutine
Marc-André Lureau
4
-5
/
+34
2020-11-04
console: modify ppm_save to take a pixman image ref
Marc-André Lureau
2
-8
/
+9
2020-11-04
coroutine: let CoQueue wake up outside a coroutine
Marc-André Lureau
1
-4
/
+2
2020-11-04
dev-serial: store flow control and xon/xoff characters
Mark Cave-Ayland
2
-3
/
+37
2020-11-04
dev-serial: add support for setting data_bits in QEMUSerialSetParams
Mark Cave-Ayland
2
-0
/
+18
2020-11-04
dev-serial: add always-plugged property to ensure USB device is always attached
Mark Cave-Ayland
1
-3
/
+6
2020-11-04
dev-serial: replace DeviceOutVendor/DeviceInVendor with equivalent macros fro...
Mark Cave-Ayland
1
-15
/
+10
2020-11-04
dev-serial: add trace-events for baud rate and data parameters
Mark Cave-Ayland
2
-0
/
+5
2020-11-04
dev-serial: convert from DPRINTF to trace-events
Mark Cave-Ayland
2
-14
/
+22
2020-11-04
dev-serial: use USB_SERIAL QOM macro for USBSerialState assignments
Mark Cave-Ayland
1
-3
/
+3
2020-11-04
dev-serial: style changes to improve readability and checkpatch fixes
Mark Cave-Ayland
1
-104
/
+126
2020-11-03
Update version for v5.2.0-rc0 release
v5.2.0-rc0
Peter Maydell
1
-1
/
+1
2020-11-03
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201...
Peter Maydell
27
-127
/
+1180
2020-11-03
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Peter Maydell
5
-11
/
+25
2020-11-03
target/mips: Add unaligned access support for MIPS64R6 and Loongson-3
Huacai Chen
1
-2
/
+2
2020-11-03
target/mips: Fix Lesser GPL version number
Chetan Pant
11
-11
/
+11
2020-11-03
hw/intc/loongson: Fix incorrect 'core' calculation in liointc_read/write
AlexChen
1
-2
/
+2
2020-11-03
hw/mips/boston: Fix Lesser GPL version number
Chetan Pant
4
-4
/
+4
2020-11-03
hw/mips: Fix Lesser GPL version number
Chetan Pant
6
-6
/
+6
2020-11-03
hw/mips: Remove the 'r4k' machine
Philippe Mathieu-Daudé
8
-348
/
+7
2020-11-03
block/vvfat: Fix bad printf format specifiers
AlexChen
1
-5
/
+7
2020-11-03
iotests: Use Python 3 style super()
Kevin Wolf
1
-4
/
+4
2020-11-03
iotests: Disable unsubscriptable-object in pylint
Kevin Wolf
1
-0
/
+2
2020-11-03
iotests.py: Fix type check errors in wait_migration()
Kevin Wolf
1
-0
/
+4
2020-11-03
qemu-img convert: Free @sn_opts in all error cases
Tuguoyi
1
-1
/
+1
2020-11-03
qmp: fix aio_poll() assertion failure on Windows
Volker Rümelin
1
-1
/
+7
2020-11-03
target/riscv/csr.c : add space before the open parenthesis '('
Xinhao Zhang
1
-1
/
+1
2020-11-03
hw/riscv: microchip_pfsoc: Hook the I2C1 controller
Bin Meng
2
-0
/
+7
2020-11-03
hw/riscv: microchip_pfsoc: Correct DDR memory map
Bin Meng
2
-7
/
+48
2020-11-03
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
Bin Meng
2
-1
/
+11
2020-11-03
hw/riscv: microchip_pfsoc: Connect the SYSREG module
Bin Meng
3
-3
/
+9
2020-11-03
hw/misc: Add Microchip PolarFire SoC SYSREG module support
Bin Meng
5
-0
/
+144
2020-11-03
hw/riscv: microchip_pfsoc: Connect the IOSCB module
Bin Meng
3
-6
/
+12
2020-11-03
hw/misc: Add Microchip PolarFire SoC IOSCB module support
Bin Meng
5
-0
/
+298
2020-11-03
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
Bin Meng
3
-0
/
+24
2020-11-03
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
Bin Meng
5
-0
/
+278
2020-11-03
hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
Bin Meng
1
-0
/
+18
2020-11-03
target/riscv: Add sifive_plic vmstate
Yifei Jiang
2
-1
/
+26
2020-11-03
target/riscv: Add V extension state description
Yifei Jiang
1
-0
/
+25
2020-11-03
target/riscv: Add H extension state description
Yifei Jiang
1
-0
/
+47
2020-11-03
target/riscv: Add PMP state description
Yifei Jiang
3
-11
/
+70
2020-11-03
target/riscv: Add basic vmstate description of CPU
Yifei Jiang
4
-8
/
+81
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
6
-74
/
+41
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