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2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis5-166/+59
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis4-51/+25
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis1-13/+17
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis3-3/+14
2020-11-04Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201104-pull-request' i...Peter Maydell6-17/+45
2020-11-04Merge remote-tracking branch 'remotes/kraxel/tags/usb-20201104-pull-request' ...Peter Maydell2-131/+216
2020-11-04Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-fixes-20201103'...Peter Maydell30-373/+32
2020-11-04console: make QMP/HMP screendump run in coroutineMarc-André Lureau4-5/+34
2020-11-04console: modify ppm_save to take a pixman image refMarc-André Lureau2-8/+9
2020-11-04coroutine: let CoQueue wake up outside a coroutineMarc-André Lureau1-4/+2
2020-11-04dev-serial: store flow control and xon/xoff charactersMark Cave-Ayland2-3/+37
2020-11-04dev-serial: add support for setting data_bits in QEMUSerialSetParamsMark Cave-Ayland2-0/+18
2020-11-04dev-serial: add always-plugged property to ensure USB device is always attachedMark Cave-Ayland1-3/+6
2020-11-04dev-serial: replace DeviceOutVendor/DeviceInVendor with equivalent macros fro...Mark Cave-Ayland1-15/+10
2020-11-04dev-serial: add trace-events for baud rate and data parametersMark Cave-Ayland2-0/+5
2020-11-04dev-serial: convert from DPRINTF to trace-eventsMark Cave-Ayland2-14/+22
2020-11-04dev-serial: use USB_SERIAL QOM macro for USBSerialState assignmentsMark Cave-Ayland1-3/+3
2020-11-04dev-serial: style changes to improve readability and checkpatch fixesMark Cave-Ayland1-104/+126
2020-11-03Update version for v5.2.0-rc0 releasev5.2.0-rc0Peter Maydell1-1/+1
2020-11-03Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201...Peter Maydell27-127/+1180
2020-11-03Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell5-11/+25
2020-11-03target/mips: Add unaligned access support for MIPS64R6 and Loongson-3Huacai Chen1-2/+2
2020-11-03target/mips: Fix Lesser GPL version numberChetan Pant11-11/+11
2020-11-03hw/intc/loongson: Fix incorrect 'core' calculation in liointc_read/writeAlexChen1-2/+2
2020-11-03hw/mips/boston: Fix Lesser GPL version numberChetan Pant4-4/+4
2020-11-03hw/mips: Fix Lesser GPL version numberChetan Pant6-6/+6
2020-11-03hw/mips: Remove the 'r4k' machinePhilippe Mathieu-Daudé8-348/+7
2020-11-03block/vvfat: Fix bad printf format specifiersAlexChen1-5/+7
2020-11-03iotests: Use Python 3 style super()Kevin Wolf1-4/+4
2020-11-03iotests: Disable unsubscriptable-object in pylintKevin Wolf1-0/+2
2020-11-03iotests.py: Fix type check errors in wait_migration()Kevin Wolf1-0/+4
2020-11-03qemu-img convert: Free @sn_opts in all error casesTuguoyi1-1/+1
2020-11-03qmp: fix aio_poll() assertion failure on WindowsVolker Rümelin1-1/+7
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang1-1/+1
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2-0/+7
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2-7/+48
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2-1/+11
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng3-3/+9
2020-11-03hw/misc: Add Microchip PolarFire SoC SYSREG module supportBin Meng5-0/+144
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng3-6/+12
2020-11-03hw/misc: Add Microchip PolarFire SoC IOSCB module supportBin Meng5-0/+298
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng3-0/+24
2020-11-03hw/misc: Add Microchip PolarFire SoC DDR Memory Controller supportBin Meng5-0/+278
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng1-0/+18
2020-11-03target/riscv: Add sifive_plic vmstateYifei Jiang2-1/+26
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang1-0/+25
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang1-0/+47
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang3-11/+70
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang4-8/+81
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang6-74/+41
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