riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-11-03	Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into staging	Richard Henderson	13	-35/+258
2021-11-02	Merge remote-tracking branch 'remotes/XanClic/tags/pull-block-2021-11-02' int...	Richard Henderson	10	-34/+56
2021-11-02	bsd-user: Add stubs for new signal routines	Warner Losh	1	-0/+21
2021-11-02	Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging	Richard Henderson	24	-109/+239
2021-11-02	Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging	Richard Henderson	9	-2106/+897
2021-11-02	Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211102' into staging	Richard Henderson	103	-1433/+1266
2021-11-02	block/nvme: Extract nvme_free_queue() from nvme_free_queue_pair()	Philippe Mathieu-Daudé	1	-2/+7
2021-11-02	block/nvme: Display CQ/SQ pointer in nvme_free_queue_pair()	Philippe Mathieu-Daudé	2	-2/+2
2021-11-02	block/nvme: Automatically free qemu_memalign() with QEMU_AUTO_VFREE	Philippe Mathieu-Daudé	1	-7/+4
2021-11-02	Merge remote-tracking branch 'remotes/juanquintela/tags/migration-20211031-pu...	Richard Henderson	23	-172/+909
2021-11-02	Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"	Philippe Mathieu-Daudé	1	-2/+0
2021-11-02	hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts	BALATON Zoltan	1	-0/+13
2021-11-02	usb/uhci: Replace pci_set_irq with qemu_set_irq	BALATON Zoltan	2	-2/+4
2021-11-02	usb/uhci: Disallow user creating a vt82c686-uhci-pci device	BALATON Zoltan	3	-0/+6
2021-11-02	usb/uhci: Misc clean up	BALATON Zoltan	1	-5/+2
2021-11-02	target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU	Philippe Mathieu-Daudé	1	-1/+0
2021-11-02	target/mips: Fix Loongson-3A4000 MSAIR config register	Philippe Mathieu-Daudé	1	-0/+1
2021-11-02	target/mips: Remove one MSA unnecessary decodetree overlap group	Philippe Mathieu-Daudé	1	-182/+180
2021-11-02	target/mips: Remove generic MSA opcode	Philippe Mathieu-Daudé	2	-9/+0
2021-11-02	target/mips: Convert CTCMSA opcode to decodetree	Philippe Mathieu-Daudé	2	-58/+16
2021-11-02	target/mips: Convert CFCMSA opcode to decodetree	Philippe Mathieu-Daudé	2	-9/+23
2021-11-02	target/mips: Convert MSA MOVE.V opcode to decodetree	Philippe Mathieu-Daudé	2	-6/+20
2021-11-02	target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree	Philippe Mathieu-Daudé	2	-88/+19
2021-11-02	target/mips: Convert MSA COPY_U opcode to decodetree	Philippe Mathieu-Daudé	2	-26/+41
2021-11-02	target/mips: Convert MSA ELM instruction format to decodetree	Philippe Mathieu-Daudé	2	-13/+52
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)	Philippe Mathieu-Daudé	2	-863/+106
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)	Philippe Mathieu-Daudé	2	-34/+9
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)	Philippe Mathieu-Daudé	2	-158/+35
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)	Philippe Mathieu-Daudé	2	-12/+11
2021-11-02	target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)	Philippe Mathieu-Daudé	2	-176/+76
2021-11-02	target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)	Philippe Mathieu-Daudé	2	-39/+38
2021-11-02	target/mips: Convert MSA VEC instruction format to decodetree	Philippe Mathieu-Daudé	2	-75/+31
2021-11-02	target/mips: Convert MSA 2R instruction format to decodetree	Philippe Mathieu-Daudé	2	-75/+19
2021-11-02	target/mips: Convert MSA FILL opcode to decodetree	Philippe Mathieu-Daudé	2	-12/+21
2021-11-02	target/mips: Convert MSA 2RF instruction format to decodetree	Philippe Mathieu-Daudé	2	-85/+53
2021-11-02	target/mips: Convert MSA load/store instruction format to decodetree	Philippe Mathieu-Daudé	2	-59/+36
2021-11-02	target/mips: Convert MSA I8 instruction format to decodetree	Philippe Mathieu-Daudé	2	-56/+27
2021-11-02	target/mips: Convert MSA SHF opcode to decodetree	Philippe Mathieu-Daudé	2	-17/+22
2021-11-02	target/mips: Convert MSA BIT instruction format to decodetree	Philippe Mathieu-Daudé	2	-97/+101
2021-11-02	target/mips: Convert MSA I5 instruction format to decodetree	Philippe Mathieu-Daudé	2	-77/+41
2021-11-02	target/mips: Convert MSA LDI opcode to decodetree	Philippe Mathieu-Daudé	2	-9/+21
2021-11-02	target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v	Philippe Mathieu-Daudé	2	-18/+17
2021-11-02	target/mips: Use enum definitions from CPUMIPSMSADataFormat enum	Philippe Mathieu-Daudé	1	-3/+3
2021-11-02	target/mips: Have check_msa_access() return a boolean	Philippe Mathieu-Daudé	1	-7/+18
2021-11-02	target/mips: Use dup_const() to simplify	Philippe Mathieu-Daudé	1	-20/+3
2021-11-02	target/mips: Adjust style in msa_translate_init()	Philippe Mathieu-Daudé	1	-1/+3
2021-11-02	target/mips: Fix MSA MSUBV.B opcode	Philippe Mathieu-Daudé	1	-16/+16
2021-11-02	target/mips: Fix MSA MADDV.B opcode	Philippe Mathieu-Daudé	1	-16/+16
2021-11-02	MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware	Philippe Mathieu-Daudé	1	-3/+7
2021-11-02	MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware	Philippe Mathieu-Daudé	1	-6/+14