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2020-02-03docs/sphinx: Add new hxtool Sphinx extensionPeter Maydell2-1/+212
Some of our documentation includes sections which are created by assembling fragments of texinfo from a .hx source file into a .texi file, which is then included from qemu-doc.texi or qemu-img.texi. For Sphinx, rather than creating a file to include, the most natural way to handle this is to have a small custom Sphinx extension which reads the .hx file and process it. So instead of: * makefile produces foo.texi from foo.hx * qemu-doc.texi says '@include foo.texi' we have: * qemu-doc.rst says 'hxtool-doc:: foo.hx' * the Sphinx extension for hxtool has code that runs to handle that Sphinx directive which reads the .hx file and emits the appropriate documentation contents This is pretty much the same way the kerneldoc extension works right now. It also has the advantage that it should work for third-party services like readthedocs that expect to build the docs directly with sphinx rather than by invoking our makefiles. In this commit we implement the hxtool extension. Note that syntax errors in the rST fragments will be correctly reported to the user with the filename and line number within the hx file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200124162606.8787-4-peter.maydell@linaro.org
2020-02-03hxtool: Support SRST/ERST directivesPeter Maydell1-1/+32
We want to add support for including rST document fragments in our .hx files, in the same way we currently have texinfo fragments. These will be delimited by SRST and ERST directives, in the same way the texinfo is delimited by STEXI/ETEXI. The rST fragments will not be extracted by the hxtool script, but by a different mechanism, so all we need to do in hxtool is have it ignore all the text inside a SRST/ERST section, with suitable error-checking for mismatched rST-vs-texi fragment delimiters. The resulting effective state machine has only three states: * flag = 0, rstflag = 0 : reading section for C output * flag = 1, rstflag = 0 : reading texi fragment * flag = 0, rstflag = 1 : reading rST fragment and flag = 1, rstflag = 1 is not possible. Using two variables makes the parallel between the rST handling and the texi handling clearer; in any case all this code will be deleted once we've converted entirely to rST. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200124162606.8787-3-peter.maydell@linaro.org
2020-02-03Makefile: Ensure we don't run Sphinx in parallel for manpagesPeter Maydell2-7/+46
Sphinx will corrupt its doctree cache if we run two copies of it in parallel. In commit 6bda415c10d966c8d3 we worked around this by having separate doctrees for 'html' vs 'manpage' runs. However now that we have more than one manpage produced from a single manual we can run into this again when trying to produce the two manpages. Use the trick described in 'Atomic Rules in GNU Make' https://www.cmcrossroads.com/article/atomic-rules-gnu-make to ensure that we only run the Sphinx manpage builder once for each manual, even if we're producing several manpages. This fixes doctree corruption in parallel builds and also avoids pointlessly running Sphinx more often than we need to. (In GNU Make 4.3 there is builtin support for this, via the "&:" syntax, but we can't wait for that to be available in all the distros we support...) The generic "one invocation for multiple output files" machinery is provided as a macro named 'atomic' in rules.mak; we then wrap this in a more specific macro for defining the rule and dependencies for the manpages in a Sphinx manual, to avoid excessive repetition. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200124162606.8787-2-peter.maydell@linaro.org
2020-02-03Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200203' ↵Peter Maydell76-1017/+7565
into staging ppc patch queue 2020-02093 This pull request supersedes ppc-for-5.0-20200131. The only changes are one extra patch to suppress some irritating warnings during tests under TCG, and an extra Tested-by in one of the other patches. Here's the next batch of patches for ppc and associated machine types. Highlights includes: * Remove the deprecated "prep" machine type and its OpenHackware firmware * Add TCG emulation of the msgsndp etc. supervisor privileged doorbell instructions * Allow "pnv" machine type to run Hostboot style firmwares * Add a virtual TPM device for spapr machines * Implement devices for POWER8 PHB3 and POWER9 PHB4 host bridges for the pnv machine type * Use faster Spectre mitigation by default for POWER9 DD2.3 machines * Introduce Firmware Assisted NMI dump facility for spapr machines * Fix a performance regression with load/store multiple instructions in TCG as well as some other assorted cleanups and fixes. # gpg: Signature made Mon 03 Feb 2020 03:30:24 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.0-20200203: (35 commits) tests: Silence various warnings with pseries target/ppc: Use probe_write for DCBZ target/ppc: Remove redundant mask in DCBZ target/ppc: Use probe_access for LMW, STMW target/ppc: Use probe_access for LSW, STSW ppc: spapr: Activate the FWNMI functionality migration: Include migration support for machine check handling ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls target/ppc: Build rtas error log upon an MCE target/ppc: Handle NMI guest exit ppc: spapr: Introduce FWNMI capability Wrapper function to wait on condition for the main loop mutex target/ppc/cpu.h: Put macro parameter in parentheses spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine ppc/pnv: change the PowerNV machine devices to be non user creatable ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge docs/specs/tpm: reST-ify TPM documentation hw/ppc/Kconfig: Enable TPM_SPAPR as part of PSERIES config tpm_spapr: Support suspend and resume ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-03tests: Silence various warnings with pseriesGreg Kurz4-5/+16
Some default features of the pseries machine are only available with KVM. Warnings are printed when the pseries machine is used with another accelerator: qemu-system-ppc64: warning: TCG doesn't support requested feature, cap-ccf-assist=on qemu-system-ppc64: warning: Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported in TCG qemu-system-ppc64: warning: TCG doesn't support requested feature, cap-ccf-assist=on qemu-system-ppc64: warning: Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported in TCG qemu-system-ppc64: warning: TCG doesn't support requested feature, cap-ccf-assist=on qemu-system-ppc64: warning: Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported in TCG This is annoying for CI since it usually runs without KVM. We already disable features that emit similar warnings thanks to properties of the pseries machine, but this is open-coded in various places. Consolidate the set of properties in a single place. Extend it to silence the above warnings. And use it in the various tests that start pseries machines. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <158059697130.1820292.7823434132030453110.stgit@bahia.lan> Reviewed-by: Thomas Huth <thuth@redhat.com> [dwg: Correct minor grammatical error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc: Use probe_write for DCBZRichard Henderson1-1/+1
Using probe_write instead of tlb_vaddr_to_host means that we process watchpoints and notdirty pages more efficiently. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200129235040.24022-5-richard.henderson@linaro.org> Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc: Remove redundant mask in DCBZRichard Henderson1-1/+1
The value of addr has already been masked, just above. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200129235040.24022-4-richard.henderson@linaro.org> Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc: Use probe_access for LMW, STMWRichard Henderson1-13/+32
Use a minimum number of mmu lookups for the contiguous bytes that are accessed. If the lookup succeeds, we can finish the operation with host addresses only. Reported-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200129235040.24022-3-richard.henderson@linaro.org> Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc: Use probe_access for LSW, STSWRichard Henderson1-20/+128
Use a minimum number of mmu lookups for the contiguous bytes that are accessed. If the lookup succeeds, we can finish the operation with host addresses only. Reported-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200129235040.24022-2-richard.henderson@linaro.org> Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03ppc: spapr: Activate the FWNMI functionalityAravinda Prasad1-1/+2
This patch sets the default value of SPAPR_CAP_FWNMI_MCE to SPAPR_CAP_ON for machine type 5.0. Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Message-Id: <20200130184423.20519-8-ganeshgr@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03migration: Include migration support for machine check handlingAravinda Prasad4-1/+66
This patch includes migration support for machine check handling. Especially this patch blocks VM migration requests until the machine check error handling is complete as these errors are specific to the source hardware and is irrelevant on the target hardware. Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> [Do not set FWNMI cap in post_load, now its done in .apply hook] Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Message-Id: <20200130184423.20519-7-ganeshgr@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS callsAravinda Prasad3-1/+72
This patch adds support in QEMU to handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls. The machine check notification address is saved when the OS issues "ibm,nmi-register" RTAS call. This patch also handles the case when multiple processors experience machine check at or about the same time by handling "ibm,nmi-interlock" call. In such cases, as per PAPR, subsequent processors serialize waiting for the first processor to issue the "ibm,nmi-interlock" call. The second processor that also received a machine check error waits till the first processor is done reading the error log. The first processor issues "ibm,nmi-interlock" call when the error log is consumed. Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> [Register fwnmi RTAS calls in core_rtas_register_types() where other RTAS calls are registered] Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Message-Id: <20200130184423.20519-6-ganeshgr@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc: Build rtas error log upon an MCEAravinda Prasad4-3/+253
Upon a machine check exception (MCE) in a guest address space, KVM causes a guest exit to enable QEMU to build and pass the error to the guest in the PAPR defined rtas error log format. This patch builds the rtas error log, copies it to the rtas_addr and then invokes the guest registered machine check handler. The handler in the guest takes suitable action(s) depending on the type and criticality of the error. For example, if an error is unrecoverable memory corruption in an application inside the guest, then the guest kernel sends a SIGBUS to the application. For recoverable errors, the guest performs recovery actions and logs the error. Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> [Assume SLOF has allocated enough room for rtas error log] Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200130184423.20519-5-ganeshgr@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc: Handle NMI guest exitAravinda Prasad6-0/+76
Memory error such as bit flips that cannot be corrected by hardware are passed on to the kernel for handling. If the memory address in error belongs to guest then the guest kernel is responsible for taking suitable action. Patch [1] enhances KVM to exit guest with exit reason set to KVM_EXIT_NMI in such cases. This patch handles KVM_EXIT_NMI exit. [1] https://www.spinics.net/lists/kvm-ppc/msg12637.html (e20bbd3d and related commits) Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20200130184423.20519-4-ganeshgr@linux.ibm.com> [dwg: #ifdefs to fix compile for 32-bit target] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03ppc: spapr: Introduce FWNMI capabilityAravinda Prasad5-1/+38
Introduce fwnmi an spapr capability and add a helper function which tries to enable it, which would be used by following patch of the series. This patch by itself does not change the existing behavior. Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> [eliminate cap_ppc_fwnmi, add fwnmi cap to migration state and reprhase the commit message] Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200130184423.20519-3-ganeshgr@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03Wrapper function to wait on condition for the main loop mutexAravinda Prasad2-0/+13
Introduce a wrapper function to wait on condition for the main loop mutex. This function atomically releases the main loop mutex and causes the calling thread to block on the condition. This wrapper is required because qemu_global_mutex is a static variable. Signed-off-by: Aravinda Prasad <arawinda.p@gmail.com> Signed-off-by: Ganesh Goudar <ganeshgr@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20200130184423.20519-2-ganeshgr@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03target/ppc/cpu.h: Put macro parameter in parenthesesBALATON Zoltan1-1/+1
Fix PPC_INPUT macro to work with more complex expressions by protecting its argument with parentheses. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20200130021619.65FAB747871@zero.eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-03spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machineDavid Gibson2-5/+21
For POWER9 DD2.2 cpus, the best current Spectre v2 indirect branch mitigation is "count cache disabled", which is configured with: -machine cap-ibs=fixed-ccd However, this option isn't available on DD2.3 CPUs with KVM, because they don't have the count cache disabled. For POWER9 DD2.3 cpus, it is "count cache flush with assist", configured with: -machine cap-ibs=workaround,cap-ccf-assist=on However this option isn't available on DD2.2 CPUs with KVM, because they don't have the special CCF assist instruction this relies on. On current machine types, we default to "count cache flush w/o assist", that is: -machine cap-ibs=workaround,cap-ccf-assist=off This runs, with mitigation on both DD2.2 and DD2.3 host cpus, but has a fairly significant performance impact. It turns out we can do better. The special instruction that CCF assist uses to trigger a count cache flush is a no-op on earlier CPUs, rather than trapping or causing other badness. It doesn't, of itself, implement the mitigation, but *if* we have count-cache-disabled, then the count cache flush is unnecessary, and so using the count cache flush mitigation is harmless. Therefore for the new pseries-5.0 machine type, enable cap-ccf-assist by default. Along with that, suppress throwing an error if cap-ccf-assist is selected but KVM doesn't support it, as long as KVM *is* giving us count-cache-disabled. To allow TCG to work out of the box, even though it doesn't implement the ccf flush assist, downgrade the error in that case to a warning. This matches several Spectre mitigations where we allow TCG to operate for debugging, since we don't really make guarantees about TCG security properties anyway. While we're there, make the TCG warning for this case match that for other mitigations. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Tested-by: Michael Ellerman <mpe@ellerman.id.au>
2020-02-02ppc/pnv: change the PowerNV machine devices to be non user creatableCédric Le Goater8-1/+12
The PowerNV machine emulates an OpenPOWER system and the PowerNV chip devices are models of the internal logic of the POWER processor. They can not be instantiated by the user on the QEMU command line. The PHB3/PHB4 devices could be an exception in the future after some rework on how the device tree is built. For the moment, exclude them also. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200129113720.7404-1-clg@kaod.org> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridgeCédric Le Goater11-3/+2614
This is a model of the PCIe Host Bridge (PHB3) found on a POWER8 processor. It includes the PowerBus logic interface (PBCQ), IOMMU support, a single PCIe Gen.3 Root Complex, and support for MSI and LSI interrupt sources as found on a POWER8 system using the XICS interrupt controller. The POWER8 processor comes in different flavors: Venice, Murano, Naple, each having a different number of PHBs. To make things simpler, the models provides 3 PHB3 per chip. Some platforms, like the Firestone, can also couple PHBs on the first chip to provide more bandwidth but this is too specific to model in QEMU. XICS requires some adjustment to support the PHB3 MSI. The changes are provided here but they could be decoupled in prereq patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144506.11132-3-clg@kaod.org> [dwg: Use device_class_set_props()] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridgeBenjamin Herrenschmidt10-0/+2943
These changes introduces models for the PCIe Host Bridge (PHB4) of the POWER9 processor. It includes the PowerBus logic interface (PBCQ), IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI and LSI interrupt sources as found on a POWER9 system using the XIVE interrupt controller. POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and each PEC can have several PHBs. By default, * PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5) Each PEC has a set "global" registers and some "per-stack" (per-PHB) registers. Those are organized in two XSCOM ranges, the "Nest" range and the "PCI" range, each range contains both some "PEC" registers and some "per-stack" registers. No default device layout is provided and PCI devices can be added on any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip) with address 0x0 as the firwware (skiboot) only accepts a single device per root port. To run a simple system with a network and a storage adapters, use a command line options such as : -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0 -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0 -device megasas,id=scsi0,bus=pcie.1,addr=0x0 -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2 If more are needed, include a bridge. Multi chip is supported, each chip adding its set of PHB4 controllers and its PCI busses. The model doesn't emulate the EEH error handling. This model is not ready for hotplug yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [ clg: - numerous cleanups - commit log - fix for broken LSI support - PHB pic printinfo - large QOM rework ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144506.11132-2-clg@kaod.org> [dwg: Use device_class_set_props()] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02docs/specs/tpm: reST-ify TPM documentationMarc-André Lureau3-445/+504
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Message-Id: <20200121152935.649898-7-stefanb@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02hw/ppc/Kconfig: Enable TPM_SPAPR as part of PSERIES configStefan Berger1-1/+1
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200121152935.649898-6-stefanb@linux.ibm.com> [dwg: Use default in Kconfig rather than select to avoid breaking Windows host build] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02tpm_spapr: Support suspend and resumeStefan Berger2-1/+53
Extend the tpm_spapr frontend with VM suspend and resume support. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Message-Id: <20200121152935.649898-5-stefanb@linux.ibm.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02tpm_spapr: Support TPM for ppc64 using CRQ based interfaceStefan Berger7-4/+423
Implement support for TPM on ppc64 by implementing the vTPM CRQ interface as a frontend. It can use the tpm_emulator driver backend with the external swtpm. The Linux vTPM driver for ppc64 works with this emulation. This TPM emulator also handles the TPM 2 case. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200121152935.649898-4-stefanb@linux.ibm.com> [dwg: Use device_class_set_props(), tweak Kconfig] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02spapr: Implement get_dt_compatible() callbackStefan Berger2-2/+10
For devices that cannot be statically initialized, implement a get_dt_compatible() callback that allows us to ask the device for the 'compatible' value. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200121152935.649898-3-stefanb@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02tpm: Move tpm_tis_show_buffer to tpm_util.cStefan Berger4-29/+33
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200121152935.649898-2-stefanb@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: Add support for "hostboot" modeCédric Le Goater5-2/+37
When the "hb-mode" option is activated on the powernv machine, the firmware is mapped at 0x8000000 and the HRMOR of the HW threads are set to the same address. The PNOR mapping on the FW address space of the LPC bus is left enabled to let the firmware load any other images required to boot the host. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144154.10170-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: remove useless "core-pir" property alias.Cédric Le Goater1-15/+13
Commit 158e17a65e1a ("ppc/pnv: Link "chip" property to PnvCore::chip pointer") introduced some cleanups of the PnvCore realize handler. Let's continue by reworking a bit the interface of the PnvCore handlers for the CPU threads. These changes make the "core-pir" property alias unused. Remove it. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144154.10170-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: Add support for HRMOR on Radix hostCédric Le Goater1-0/+6
When in HV mode, if EA[0] is 0, the Hypervisor Offset Real Mode Register controls the access. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144154.10170-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02spapr: Don't allow multiple active vCPUs at CASGreg Kurz1-0/+12
According to the description of "ibm,client-architecture-support" that can found in LoPAPR "B.6.2.3 Root Node Methods": If multiple partition processors or threads are active at the time of the ibm,client-architecture-support method call, or an error is detected in the format of the ibm,architecture.vec structure, the err? boolean shall be TRUE; else FALSE. We certainly don't want to temper with the platform or with the PCR of the other vCPUs if they happen to be active. Ensure we have only one active vCPU and fail CAS otherwise. This is just for conformance and robustness, it doesn't fix any known bugs. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157969867170.571404.12117797348882189656.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02target/ppc: add support for Hypervisor Facility Unavailable ExceptionCédric Le Goater3-0/+46
The privileged message send and clear instructions (msgsndp & msgclrp) are privileged, but will generate a hypervisor facility unavailable exception if not enabled in the HFSCR and executed in privileged non-hypervisor state. Add checks when accessing the DPDES register and when using the msgsndp and msgclrp isntructions. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200120104935.24449-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02target/ppc: Add privileged message send facilitiesCédric Le Goater5-20/+132
The Processor Control facility for POWER8 processors and later provides a mechanism for the hypervisor to send messages to other threads in the system (msgsnd instruction) and cause hypervisor-level exceptions. Privileged non-hypervisor programs can also send messages (msgsndp instruction) but are restricted to the threads of the same subprocessor and cause privileged-level exceptions. The Directed Privileged Doorbell Exception State (DPDES) register reflects the state of pending privileged doorbell exceptions and can be used to modify that state. The register can be used to read and modify the state of privileged doorbell exceptions for all threads of a subprocessor and thus is a shared facility for that subprocessor. The register can be read/written by the hypervisor and read by the supervisor if enabled in the HFSCR, otherwise a hypervisor facility unavailable exception is generated. The privileged message send and clear instructions (msgsndp & msgclrp) are used to generate and clear the presence of a directed privileged doorbell exception, respectively. The msgsndp instruction can be used to target any thread of the current subprocessor, msgclrp acts on the thread issuing the instruction. These instructions are privileged, but will generate a hypervisor facility unavailable exception if not enabled in the HFSCR and executed in privileged non-hypervisor state. The HV facility unavailable exception will be addressed in other patch. Add and implement this register and instructions by reading or modifying the pending interrupt state of the cpu. Note that TCG only supports one thread per core and so we only need to worry about the cpu making the access. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200120104935.24449-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02spapr: Fail CAS if option vector table cannot be parsedGreg Kurz1-0/+8
Most of the option vector helpers have assertions to check their arguments aren't null. The guest can provide an arbitrary address for the CAS structure that would result in such null arguments. Fail CAS with H_PARAMETER and print a warning instead of aborting QEMU. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <157925255250.397143.10855183619366882459.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02target/ppc: Clarify the meaning of return values in kvm_handle_debugFabiano Rosas1-6/+9
The kvm_handle_debug function can return 0 to go back into the guest or return 1 to notify the gdbstub thread and pass control to GDB. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20200110151344.278471-2-farosas@linux.ibm.com> Tested-by: Leonardo Bras <leonardo@ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOSThomas Huth15-455/+10
It's been deprecated since QEMU v3.1. The 40p machine should be used nowadays instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200114114617.28854-1-thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc:virtex_ml507: remove unused argumentsIgor Mammedov1-5/+2
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1579100861-73692-71-git-send-email-imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: improve error logging when a PNOR update failsCédric Le Goater1-1/+2
Print out the offset at which the error occured. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200108090348.21224-3-clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-02ppc/pnv: use QEMU unit definition MiBCédric Le Goater1-1/+2
Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200108090348.21224-2-clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-31Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell7-33/+30
into staging Pull request # gpg: Signature made Thu 30 Jan 2020 21:38:06 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: qemu_set_log_filename: filename argument may be NULL hw/display/qxl.c: Use trace_event_get_state_backends() memory.c: Use trace_event_get_state_backends() docs/devel/tracing.txt: Recommend only trace_event_get_state_backends() Makefile: Keep trace-events-subdirs ordered Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-31target/arm: fix TCG leak for fcvt half->doubleAlex Bennée1-2/+2
When support for the AHP flag was added we inexplicably only freed the new temps in one of the two legs. Move those tcg_temp_free to the same level as the allocation to fix that leak. Fixes: 486624fcd3eac Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200131153439.26027-1-alex.bennee@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-31Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell37-172/+878
staging Pull request # gpg: Signature made Thu 30 Jan 2020 21:31:02 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: tests/qemu-iotests: use AIOMODE with various tests tests/qemu-iotests: enable testing with aio options qemu-nbd: adds option for aio engines qemu-img: adds option to use aio engine for benchmarking qemu-io: adds option to use aio engine block/io_uring: adds userspace completion polling block: add trace events for io_uring block/file-posix.c: extend to use io_uring blockdev: adds bdrv_parse_aio to use io_uring util/async: add aio interfaces for io_uring stubs: add stubs for io_uring interface block/io_uring: implements interfaces for io_uring block/block: add BDRV flag for io_uring qapi/block-core: add option for io_uring configure: permit use of io_uring block/io: take bs->reqs_lock in bdrv_mark_request_serialising block/io: wait for serialising requests when a request becomes serialising block: eliminate BDRV_REQ_NO_SERIALISING Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-30qemu_set_log_filename: filename argument may be NULLSalvador Fandino3-19/+18
NULL is a valid log filename used to indicate we want to use stderr but qemu_set_log_filename (which is called by bsd-user/main.c) was not handling it correctly. That also made redundant a couple of NULL checks in calling code which have been removed. Signed-off-by: Salvador Fandino <salvador@qindel.com> Message-Id: <20200123193626.19956-1-salvador@qindel.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30hw/display/qxl.c: Use trace_event_get_state_backends()Peter Maydell1-1/+1
The preferred way to test whether a trace event is enabled is to use trace_event_get_state_backends(), because this will give the correct answer (allowing expensive computations to be skipped) whether the trace event is compile-time or run-time disabled. Convert the old-style direct use of TRACE_FOO_ENABLED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200120151142.18954-4-peter.maydell@linaro.org Message-Id: <20200120151142.18954-4-peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30memory.c: Use trace_event_get_state_backends()Peter Maydell1-4/+4
The preferred way to test whether a trace event is enabled is to use trace_event_get_state_backends(), because this will give the correct answer (allowing expensive computations to be skipped) whether the trace event is compile-time or run-time disabled. Convert the four old-style direct uses of TRACE_FOO_ENABLED in memory.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200120151142.18954-3-peter.maydell@linaro.org Message-Id: <20200120151142.18954-3-peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30docs/devel/tracing.txt: Recommend only trace_event_get_state_backends()Peter Maydell1-7/+5
Instead of recommending checking the TRACE_FOO_ENABLED macro to skip expensive computations needed only for tracing, recommend only using trace_event_get_state_backends(). This works for both compile-time and run-time disabling of events, and has no extra performance impact if the event is compile-time disabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200120151142.18954-2-peter.maydell@linaro.org Message-Id: <20200120151142.18954-2-peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30Makefile: Keep trace-events-subdirs orderedPhilippe Mathieu-Daudé1-2/+2
Adding the same directory multiple times to trace-events-subdirs might trigger build failures, in particular when using the LTTng Userspace Tracer library as backend. For example when using two times the hw/core/ directory: $ ./configure --enable-trace-backends=ust && make [...] CC trace-ust-all.o In file included from trace-ust-all.h:13, from trace-ust-all.c:13: trace-ust-all.h:35151:1: error: redefinition of ‘__tracepoint_cb_qemu___loader_write_rom’ 35151 | TRACEPOINT_EVENT( | ^~~~~~~~~~~~~~~~ trace-ust-all.h:31791:1: note: previous definition of ‘__tracepoint_cb_qemu___loader_write_rom’ was here 31791 | TRACEPOINT_EVENT( | ^~~~~~~~~~~~~~~~ To ease review and reduce likelihood of merge failures (see [*]), keep trace-events-subdirs ordered when possible, following eb7ccb3c0. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg671007.html Duplicate trace-events-subdirs entries generates duplicated symbols when using the LTTng Userspace Tracer library. Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200116114339.30670-1-philmd@redhat.com Message-Id: <20200116114339.30670-1-philmd@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30tests/qemu-iotests: use AIOMODE with various testsAarushi Mehta11-25/+26
Signed-off-by: Aarushi Mehta <mehta.aaru20@gmail.com> Acked-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20200120141858.587874-16-stefanha@redhat.com Message-Id: <20200120141858.587874-16-stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30tests/qemu-iotests: enable testing with aio optionsAarushi Mehta3-3/+38
Signed-off-by: Aarushi Mehta <mehta.aaru20@gmail.com> Acked-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20200120141858.587874-15-stefanha@redhat.com Message-Id: <20200120141858.587874-15-stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-01-30qemu-nbd: adds option for aio enginesAarushi Mehta2-10/+6
Signed-off-by: Aarushi Mehta <mehta.aaru20@gmail.com> Acked-by: Eric Blake <eblake@redhat.com> Acked-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20200120141858.587874-14-stefanha@redhat.com Message-Id: <20200120141858.587874-14-stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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