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2025-01-27hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific ImplementationsJamin Lin2-16/+41
The register set have a significant change in AST2700. The TMC00-TMC3C are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional, TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1, respectively. Besides, each TIMER has their own control and interrupt status register. In other words, users are able to set control and interrupt status for TIMER0 in one register. Both aspeed_timer_read and aspeed_timer_write callback functions are not compatible AST2700. Introduce common read and write functions for ASPEED timers. Modify the aspeed_timer_read and aspeed_timer_write functions to delegate to SoC-specific callbacks first. Update the AST2400, AST2500, AST2600 and AST1030 specific read and write functions to call the common implementations for common register accesses. This refactoring improves the organization of call delegation and prepares the codebase for future SoC-specific specializations, such as the AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250113064455.1660564-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVBJamin Lin2-0/+8
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_inverted" property in ASPEED MACHINE State and set it true for AST2600 EVB and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27hw/sd/sdhci: Introduce a new Write Protected pin inverted propertyJamin Lin2-0/+11
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable the bit 19 should be 0 and write protected the bit 19 should be 1 at the Present State Register (0x24). To support it, introduces a new "wp-inverted" property and set it false by default. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27hw/arm/aspeed: fix connect_serial_hds_to_uartsKenneth Jia1-2/+2
In the loop, we need ignore the index increase when uart == uart_chosen We should increase the index only after we allocate a serial. Signed-off-by: Kenneth Jia <kenneth_jia@asus.com> Fixes: d2b3eaefb4d7 ("aspeed: Refactor UART init for multi-SoC machines") Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/5f9b0c53f1644922ba85522046e92f4c@asus.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-24hw/hppa: Fix booting Linux kernel with initrdHelge Deller2-29/+23
Commit 20f7b890173b ("hw/hppa: Reset vCPUs calling resettable_reset()") broke booting the Linux kernel with initrd which may have been provided on the command line. The problem is, that the mentioned commit zeroes out initial registers which were preset with addresses for the Linux kernel and initrd. Fix it by adding proper variables which are set shortly before starting the firmware. Signed-off-by: Helge Deller <deller@gmx.de> Fixes: 20f7b890173b ("hw/hppa: Reset vCPUs calling resettable_reset()") Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-24hw/hppa: Support up to 256 GiB RAM on 64-bit machinesHelge Deller2-7/+21
Allow up to 256 GB RAM, which is the maximum a rp8440 machine (the very last 64-bit PA-RISC machine) physically supports. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-24Merge tag 'linux-user-fix-gupnp-pull-request' of ↵Stefan Hajnoczi3-17/+192
https://github.com/hdeller/qemu-hppa into staging linux-user: Add support for various missing netlink sockopt entries Add missing sockopt calls and thus fix building the debian gupnp package in a chroot. This fixes debian bug report: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1044651 Signed-off-by: Helge Deller <deller@gmx.de> # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZ5OPdwAKCRD3ErUQojoP # X9EWAP0ZvoDehmNzgWMlUpWT+d4O06kMsrDsi+tRddUUSJgp4wEAuuycr4go4b9b # 6xLDLr81C7MFEGsztGcRVhPwVdDJxAU= # =Lw8U # -----END PGP SIGNATURE----- # gpg: Signature made Fri 24 Jan 2025 08:02:47 EST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'linux-user-fix-gupnp-pull-request' of https://github.com/hdeller/qemu-hppa: linux-user: netlink: Add missing QEMU_IFLA entries linux-user: netlink: add netlink neighbour emulation linux-user: netlink: Add emulation of IP_MULTICAST_IF linux-user: netlink: Add IP_PKTINFO cmsg parsing linux-user: Use unique error messages for cmsg parsing linux-user: netlink: Add missing IFA_PROTO to host_to_target_data_addr_rtattr() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-24Merge tag 'pull-loongarch-20250124' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi7-139/+294
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ5M4AwAKCRAfewwSUazn # 0aJAAP45/9qfbGSYiMCrBXpRFlyvtRN+GEXHEsERfk9Q1V+tQgEA/mMiUEcyc/xc # Z1Z27cDoqUFRhPmxbd6/KyTGHzo2+As= # =Zanw # -----END PGP SIGNATURE----- # gpg: Signature made Fri 24 Jan 2025 01:49:39 EST # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250124' of https://gitlab.com/bibo-mao/qemu: target/loongarch: Dump all generic CSR registers target/loongarch: Set unused flag with CSR registers target/loongarch: Add common source file for CSR register target/loongarch: Add common header file for CSR registers target/loongarch: Add generic csr function type target/loongarch: Remove static CSR function setting target/loongarch: Add dynamic function access with CSR register Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-24linux-user: netlink: Add missing QEMU_IFLA entriesHelge Deller1-1/+35
This fixes the following qemu warnings when building debian gupnp package: Unknown host QEMU_IFLA type: 61 Unknown host QEMU_IFLA type: 58 Unknown host QEMU_IFLA type: 59 Unknown host QEMU_IFLA type: 60 Unknown host QEMU_IFLA type: 32820 QEMU_IFLA type 32820 is actually NLA_NESTED | QEMU_IFLA_PROP_LIST (a nested entry), which is why rta_type needs to be masked with NLA_TYPE_MASK. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2025-01-24linux-user: netlink: add netlink neighbour emulationHelge Deller1-0/+100
Fixes various warnings in the testsuite while building gupnp: gssdp-net-DEBUG: Failed to send netlink message: Operation not supported gupnp-context-DEBUG: Mismatch between host header and host IP (example.com, expected: 127.0.0.1) gupnp-context-DEBUG: Mismatch between host header and host port (80, expected 4711) gupnp-context-DEBUG: Mismatch between host header and host IP (192.168.1.2, expected: 127.0.0.1) gupnp-context-DEBUG: Mismatch between host header and host IP (fe80::01, expected: 127.0.0.1) gupnp-context-DEBUG: Mismatch between host header and host port (80, expected 4711) gupnp-context-DEBUG: Failed to parse HOST header from request: Invalid IPv6 address ?[fe80::01%1]? in URI gupnp-context-DEBUG: Failed to parse HOST header from request: Invalid IPv6 address ?[fe80::01%eth0]? in URI gupnp-context-DEBUG: Failed to parse HOST header from request: Could not parse port ?:1? in URI gupnp-context-DEBUG: Mismatch between host header and host IP (example.com, expected: ::1) gupnp-context-DEBUG: Mismatch between host header and host port (80, expected 4711) gupnp-context-DEBUG: Mismatch between host header and host IP (example.com, expected: ::1) gupnp-context-DEBUG: Mismatch between host header and host port (80, expected 4711) gupnp-context-DEBUG: Mismatch between host header and host IP (example.com, expected: ::1) Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2025-01-24linux-user: netlink: Add emulation of IP_MULTICAST_IFHelge Deller1-6/+14
Add IP_MULTICAST_IF and share the code with IP_ADD_MEMBERSHIP / IP_DROP_MEMBERSHIP. Sharing the code makes sense, because the manpage of ip(7) says: IP_MULTICAST_IF (since Linux 1.2) Set the local device for a multicast socket. The argument for setsockopt(2) is an ip_mreqn or (since Linux 3.5) ip_mreq structure similar to IP_ADD_MEMBERSHIP, or an in_addr structure. (The kernel determines which structure is being passed based on the size passed in optlen.) For getsockopt(2), the argument is an in_addr structure. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2025-01-24linux-user: netlink: Add IP_PKTINFO cmsg parsingHelge Deller2-0/+16
Fixes those warnings: Unsupported host ancillary data: 0/8 Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2025-01-24linux-user: Use unique error messages for cmsg parsingHelge Deller1-2/+2
Avoid using the same error message for two different code paths as it complicates determining the one which actually triggered. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2025-01-24linux-user: netlink: Add missing IFA_PROTO to host_to_target_data_addr_rtattr()Helge Deller1-8/+25
Fix this warning: Unknown host IFA type: 11 While adding IFA_PROTO, convert all IFA_XXX values over to QEMU_IFA_XXX values to avoid a build failure on Ubuntu 22.04 (kernel v5.18 which does not know IFA_PROTO yet). Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2025-01-24target/loongarch: Dump all generic CSR registersBibo Mao3-16/+53
CSR registers is import system control registers, it had better dump all CSR registers when VM is running in system mode. Here is dump output example of CSR registers: CSR000: CRMD b4 PRMD 4 EUEN 0 MISC 0 CSR004: ECFG 71c1c ESTAT 0 ERA 9000000002c31300 BADV 12022c0e0 CSR008: BADI 2b0000 CSR012: EENTRY 90000000046b0000 CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000 TLBELO0 400000016f19001f TLBELO1 400000016f1a401f CSR024: ASID a0004 PGDL 90000001016f0000 PGDH 9000000004680000 PGD 0 CSR028: PWCL 5e56e PWCH 2e4 STLBPS e RVACFG 0 CSR032: CPUID 0 PRCFG1 72f8 PRCFG2 3ffff000 PRCFG3 8073f2 CSR048: SAVE0 0 SAVE1 af9c SAVE2 12010d6a8 SAVE3 8300000 CSR052: SAVE4 0 SAVE5 0 SAVE6 0 SAVE7 0 CSR064: TID 0 TCFG 8f0ca15 TVAL 4cefd8b CNTC fffffffffe688aaa CSR068: TICLR 0 CSR096: LLBCTL 1 CSR136: TLBRENTRY 46ba000 TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0 CSR140: TLBRELO0 1fe00043 TLBRELO1 40 TLBREHI ffff8000130d800e TLBRPRMD 0 CSR384: DMW0 8000000000000001 DMW1 9000000000000011 DMW2 0 DMW3 0 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-24target/loongarch: Set unused flag with CSR registersBibo Mao3-1/+44
On LA464, some CSR registers are not used such as CSR_SAVE8 - CSR_SAVE15, also CSR registers relative with MCE is not used now. Flag CSRFL_UNUSED is added for these registers, so that it will not dumped. In order to keep compatiblity, these CSR registers are not removed since it is used in vmstate already. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-24target/loongarch: Add common source file for CSR registerBibo Mao4-107/+116
Common source file csr.c is added here, it can be used by both TCG mode and kvm mode. The common code is removed from file tcg/insn_trans/trans_privileged.c.inc to csrc.c Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-24target/loongarch: Add common header file for CSR registersBibo Mao2-15/+26
Common header file csr.h is added here, it can be used by both TCG mode and kvm mode. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-24target/loongarch: Add generic csr function typeBibo Mao1-10/+17
Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite is not used in non-TCG mode. Generic csr function type is added here with parameter void type, so that it passes to compile with non-TCG mode. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-24target/loongarch: Remove static CSR function settingBibo Mao1-8/+8
Since CSR function setting is done dynamically in TCG mode, remove static CSR function setting here. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-24target/loongarch: Add dynamic function access with CSR registerBibo Mao3-3/+51
With CSR register, dynamic function access is used for CSR register access in TCG mode, so that csr info can be used by other modules. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-01-23rust: pl011: hide unnecessarily "pub" items from outside pl011::devicePaolo Bonzini3-7/+10
The only public interfaces for pl011 are TYPE_PL011 and pl011_create. Remove pub from everything else. Note: the "allow(dead_code)" is removed later. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: pl011: remove unnecessary "extern crate"Paolo Bonzini1-4/+0
Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: prefer NonNull::new to assertionsPaolo Bonzini5-47/+35
Do not use new_unchecked; the effect is the same, but the code is easier to read and unsafe regions become smaller. Likewise, NonNull::new can be used instead of assertion and followed by as_ref() or as_mut() instead of dereferencing the pointer. Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: make order of parameters consistent in vmstate_clockPaolo Bonzini2-2/+2
Place struct_name before field_name, similar to offset_of. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: remove translation of C vmstate macrosPaolo Bonzini1-251/+23
Keep vmstate_clock!; because it uses a field of type VMStateDescription, it cannot be converted to the VMState trait without access to the const_refs_static feature. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: pl011: switch vmstate to new-style macrosPaolo Bonzini3-19/+26
Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: qemu_api: add vmstate_structPaolo Bonzini1-0/+33
It is not type safe, but it's the best that can be done without const_refs_static. It can also be used with BqlCell and BqlRefCell. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: add public utility macros to implement VMStatePaolo Bonzini1-3/+58
Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: implement VMState for scalar typesPaolo Bonzini1-2/+126
Scalar types are those that have their own VMStateInfo. This poses a problem in that references to VMStateInfo can only be included in associated consts starting with Rust 1.83.0, when the const_refs_static was stabilized. Removing the requirement is done by placing a limited list of VMStateInfos in an enum, and going from enum to &VMStateInfo only when building the VMStateField. The same thing cannot be done with VMS_STRUCT because the set of VMStateDescriptions extends to structs defined by the devices. Therefore, structs and cells cannot yet use vmstate_of!. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: implement Zeroable for VMStateFieldPaolo Bonzini2-15/+34
This shortens a bit the constants. Do not bother using it in the vmstate macros since most of them will go away soon. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: add varray support to vmstate_of!Paolo Bonzini1-2/+40
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: implement VMState for non-leaf typesPaolo Bonzini1-1/+78
Arrays, pointers and cells use a VMStateField that is based on that for the inner type. The implementation therefore delegates to the VMState implementation of the inner type. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust: vmstate: add new type safe implementationPaolo Bonzini2-6/+109
The existing translation of the C macros for vmstate does not make any attempt to type-check vmstate declarations against the struct, so introduce a new system that computes VMStateField based on the actual struct declaration. Macros do not have full access to the type system, therefore a full implementation of this scheme requires a helper trait to analyze the type and produce a VMStateField from it; a macro "vmstate_of!" accepts arguments similar to "offset_of!" and tricks the compiler into looking up the trait for the right type. The patch introduces not just vmstate_of!, but also the slightly too clever enabling macro call_func_with_field!. The particular trick used here was proposed on the users.rust-lang.org forum, so I take no merit and all the blame. Introduce the trait and some functions to access it; the actual implementation comes later. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23memattrs: Check the size of MemTxAttrsZhao Liu1-0/+2
Make sure MemTxAttrs is packed into 8 bytes and does not exceed 8 bytes. Suggested-by: Philippe Mathieu-Daudà <philmd@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121151322.171832-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23memattrs: Convert unspecified member to boolZhao Liu1-7/+12
Convert `unspecified` member of MemTxAttrs from bit field to bool, so that bindgen could generate more ergonomic Rust binding with bool type. As a result, MemTxAttrs needs to be expanded from 4 bytes to 8 bytes. Therefore, move `unspecified` to after the bit fields and add reserved members to ensure that the whole structure is packed into 8 bytes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust/pl011: Avoid bindings::*Zhao Liu1-3/+10
List all the necessary bindings to better identify gaps in rust/qapi. And include the bindings wrapped by rust/qapi instead mapping the raw bindings directly. Inspired-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121140457.84631-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23rust/qdev: Make REALIZE safeZhao Liu2-6/+6
A safe REALIZE accepts immutable reference. Since current PL011's realize() only calls a char binding function ( qemu_chr_fe_set_handlers), it is possible to convert mutable reference (&mut self) to immutable reference (&self), which only needs to convert the pointers passed to C to mutable pointers. Thus, make REALIZE accept immutable reference. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121140457.84631-2-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23stub: Fix build failure with --enable-user --disable-system --enable-toolsZhao Liu1-2/+2
Configuring "--enable-user --disable-system --enable-tools" causes the build failure with the following information: /usr/bin/ld: libhwcore.a.p/hw_core_qdev.c.o: in function `device_finalize': /qemu/build/../hw/core/qdev.c:688: undefined reference to `qapi_event_send_device_deleted' collect2: error: ld returned 1 exit status To fix the above issue, add qdev.c stub when build with `have_tools`. With this fix, QEMU could be successfully built in the following cases: --enable-user --disable-system --enable-tools --enable-user --disable-system --disable-tools --enable-user --disable-system Cc: qemu-stable@nongnu.org Fixes: 388b849fb6c3 ("stubs: avoid duplicate symbols in libqemuutil.a") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2766 Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121154318.214680-1-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23docs: Add GNR, SRF and CWF CPU modelsTao Su1-4/+46
Update GraniteRapids, SierraForest and ClearwaterForest CPU models in section "Preferred CPU models for Intel x86 hosts". Also introduce bhi-no, gds-no and rfds-no in doc. Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121020650.1899618-5-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: Add new CPU model ClearwaterForestTao Su2-6/+162
According to table 1-2 in Intel Architecture Instruction Set Extensions and Future Features (rev 056) [1], ClearwaterForest has the following new features which have already been virtualized: - AVX-VNNI-INT16 CPUID.(EAX=7,ECX=1):EDX[bit 10] - SHA512 CPUID.(EAX=7,ECX=1):EAX[bit 0] - SM3 CPUID.(EAX=7,ECX=1):EAX[bit 1] - SM4 CPUID.(EAX=7,ECX=1):EAX[bit 2] Add above features to new CPU model ClearwaterForest. Comparing with SierraForest, ClearwaterForest bare-metal contains all features of SierraForest-v2 CPU model and adds: - PREFETCHI CPUID.(EAX=7,ECX=1):EDX[bit 14] - DDPD_U CPUID.(EAX=7,ECX=2):EDX[bit 3] - BHI_NO IA32_ARCH_CAPABILITIES[bit 20] Add above and all features of SierraForest-v2 CPU model to new CPU model ClearwaterForest. [1] https://cdrdv2.intel.com/v1/dl/getContent/671368 Tested-by: Xuelian Guo <xuelian.guo@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121020650.1899618-4-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: Export BHI_NO bit to guestsTao Su1-1/+1
Branch History Injection (BHI) is a CPU side-channel vulnerability, where an attacker may manipulate branch history before transitioning from user to supervisor mode or from VMX non-root/guest to root mode. CPUs that set BHI_NO bit in MSR IA32_ARCH_CAPABILITIES to indicate no additional mitigation is required to prevent BHI. Make BHI_NO bit available to guests. Tested-by: Xuelian Guo <xuelian.guo@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121020650.1899618-3-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: Introduce SierraForest-v2 modelTao Su1-0/+19
Update SierraForest CPU model to add LAM, 4 bits indicating certain bits of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl, bhi-ctrl) and the missing features(ss, tsc-adjust, cldemote, movdiri, movdir64b) Also add GDS-NO and RFDS-NO to indicate the related vulnerabilities are mitigated in stepping 3. Tested-by: Xuelian Guo <xuelian.guo@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250121020650.1899618-2-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: avoid using s->tmp0 for add to implicit registersPaolo Bonzini1-7/+14
For updates to implicit registers (RCX in LOOP instructions, RSI or RDI in string instructions, or the stack pointer) do the add directly using the registers (with no temporary) if 32-bit or 64-bit, or use a temporary created for the occasion if 16-bit. This is more efficient and removes move instructions for the MO_TL case. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Link: https://lore.kernel.org/r/20241215090613.89588-14-pbonzini@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: extract common bits of gen_repz/gen_repz_nzPaolo Bonzini1-20/+14
Now that everything has been cleaned up, look at DF and prefixes in a single function, and call that one from gen_repz and gen_repz_nz. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: pull computation of string update value out of loopPaolo Bonzini1-28/+26
This is a common operation that is executed many times in rep movs or rep stos loops. It can improve performance by several percentage points. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20241215090613.89588-13-pbonzini@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: execute multiple REP/REPZ iterations without leaving TBPaolo Bonzini1-6/+49
Use a TCG loop so that it is not necessary to go through the setup steps of REP and through the I/O check on every iteration. Interestingly, this is not a particularly effective optimization on its own, though it avoids the cost of correct RF emulation that was added in the previous patch. The main benefit lies in allowing the hoisting of loop invariants outside the loop, which will happen separately. The loop exits when the low 16 bits of CX/ECX/RCX are zero (so generally speaking the string operation runs in 65536 iteration batches) to give the main loop an opportunity to pick up interrupts. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Link: https://lore.kernel.org/r/20241215090613.89588-12-pbonzini@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: optimize CX handling in repeated string operationsPaolo Bonzini1-1/+14
In a repeated string operation, CX/ECX will be decremented until it is 0 but never underflow. Use this observation to avoid a deposit or zero-extend operation if the address size of the operation is smaller than MO_TL. As in the previous patch, the patch is structured to include some preparatory work for subsequent changes. In particular, introducing cx_next prepares for when ECX will be decremented *before* calling fn(s, ot), and therefore cannot yet be written back to cpu_regs. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Link: https://lore.kernel.org/r/20241215090613.89588-11-pbonzini@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: do not use gen_op_jz_ecx for repeated string operationsPaolo Bonzini1-1/+2
Explicitly generate a TSTEQ branch (which is optimized to NE x,0 if possible). This does not make much sense yet, but later we will add more checks and some will use a temporary to check on the decremented value of CX/ECX/RCX; it will be clearer for all checks to share the same logic using TSTEQ(reg, cx_mask). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Link: https://lore.kernel.org/r/20241215090613.89588-10-pbonzini@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-23target/i386: make cc_op handling more explicit for repeated string instructions.Paolo Bonzini1-3/+21
Since the cost of gen_update_cc_op() must be paid anyway, it's easier to place them manually and not rely on spilling that is buried under multiple levels of function calls. While at it, clarify the circumstances in which the gen_update_cc_op() is needed, and why it is not for REPxx SCAS and REPxx CMPS. And since cc_op will have been spilled at the point of a fault, just make the whole insn CC_OP_DYNAMIC. Once repz_opt is reintroduced, a fault could happen either before or after the first execution of CMPS/SCAS, and CC_OP_DYNAMIC sidesteps the complicated matter of what x86_restore_state_to_opc would do. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20241215090613.89588-9-pbonzini@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-09-20 21:14:17 +0000