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2025-01-28target/arm: Use FPST_A64_F16 in A64 decoderPeter Maydell2-49/+49
In the A32 decoder, use FPST_A64_F16 rather than FPST_FPCR_F16. By doing an automated conversion of the whole file we avoid possibly using more than one fpst value in a set_rmode/op/restore_rmode sequence. Patch created with perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A64_F16/g' target/arm/tcg/translate-{a64,sve,sme}.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-18-peter.maydell@linaro.org
2025-01-28target/arm: Use FPST_A32_F16 in A32 decoderPeter Maydell1-12/+12
In the A32 decoder, use FPST_A32_F16 rather than FPST_FPCR_F16. By doing an automated conversion of the whole file we avoid possibly using more than one fpst value in a set_rmode/op/restore_rmode sequence. Patch created with perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A32_F16/g' target/arm/tcg/translate-vfp.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-17-peter.maydell@linaro.org
2025-01-28target/arm: Use fp_status_f16_a64 in AArch64-only helpersPeter Maydell2-6/+6
We directly use fp_status_f16 in a handful of helpers that are AArch64-specific; switch to fp_status_f16_a64 for these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-16-peter.maydell@linaro.org
2025-01-28target/arm: Use fp_status_f16_a32 in AArch32-only helpersPeter Maydell2-3/+3
We directly use fp_status_f16 in a handful of helpers that are AArch32-specific; switch to fp_status_f16_a32 for these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-15-peter.maydell@linaro.org
2025-01-28target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64Peter Maydell4-0/+32
As the first part of splitting the existing fp_status_f16 into separate float_status fields for AArch32 and AArch64 (so that we can make FEAT_AFP control bits apply only for AArch64), define the two new fp_status_f16_a32 and fp_status_f16_a64 fields, but don't use them yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-14-peter.maydell@linaro.org
2025-01-28target/arm: Remove now-unused vfp.fp_status and FPST_FPCRPeter Maydell4-16/+1
Now we have moved all the uses of vfp.fp_status and FPST_FPCR to either the A32 or A64 fields, we can remove these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-13-peter.maydell@linaro.org
2025-01-28target/arm: Use FPST_A64 in A64 decoderPeter Maydell3-90/+90
In the A64 decoder, use FPST_A64 rather than FPST_FPCR. By doing an automated conversion of the whole file we avoid possibly using more than one fpst value in a set_rmode/op/restore_rmode sequence. Patch created with perl -p -i -e 's/FPST_FPCR(?!_)/FPST_A64/g' target/arm/tcg/translate-{a64,sve,sme}.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-12-peter.maydell@linaro.org
2025-01-28target/arm: Use FPST_A32 in A32 decoderPeter Maydell1-27/+27
In the A32 decoder, use FPST_A32 rather than FPST_FPCR. By doing an automated conversion of the whole file we avoid possibly using more than one fpst value in a set_rmode/op/restore_rmode sequence. Patch created with perl -p -i -e 's/FPST_FPCR(?!_)/FPST_A32/g' target/arm/tcg/translate-vfp.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-11-peter.maydell@linaro.org
2025-01-28target/arm: Use fp_status_a32 in vfp_cmp helpersPeter Maydell1-2/+2
The helpers vfp_cmps, vfp_cmpes, vfp_cmpd, vfp_cmped are used only from the A32 decoder; the A64 decoder uses separate vfp_cmps_a64 etc helpers (because for A64 we update the main NZCV flags and for A32 we update the FPSCR NZCV flags). So we can make these helpers use the fp_status_a32 field instead of fp_status. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-10-peter.maydell@linaro.org
2025-01-28target/arm: Use fp_status_a32 in vjvct helperPeter Maydell1-1/+1
Use fp_status_a32 in the vjcvt helper function; this is called only from the A32/T32 decoder and is not used inside a set_rmode/restore_rmode sequence. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-9-peter.maydell@linaro.org
2025-01-28target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf()Peter Maydell1-1/+1
In is_ebf(), we might be called for A64 or A32, but we have the CPUARMState* so we can select fp_status_a64 or fp_status_a32 accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-28target/arm: Use vfp.fp_status_a64 in A64-only helper functionsPeter Maydell2-5/+5
Switch from vfp.fp_status to vfp.fp_status_a64 for helpers which: * directly reference an fp_status field * are called only from the A64 decoder * are not called inside a set_rmode/restore_rmode sequence Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250124162836.2332150-8-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-28target/arm: Define new fp_status_a32 and fp_status_a64Peter Maydell4-0/+30
We want to split the existing fp_status in the Arm CPUState into separate float_status fields for AArch32 and AArch64. (This is because new control bits defined by FEAT_AFP only have an effect for AArch64, not AArch32.) To make this split we will: * define new fp_status_a32 and fp_status_a64 which have identical behaviour to the existing fp_status * move existing uses of fp_status to fp_status_a32 or fp_status_a64 as appropriate * delete the old fp_status when it has no uses left In this patch we add the new float_status fields. We will also need to split fp_status_f16, but we will do that as a separate series of patches. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-7-peter.maydell@linaro.org
2025-01-28target/arm: Use uint32_t in vfp_exceptbits_from_host()Peter Maydell1-2/+2
In vfp_exceptbits_from_host(), we accumulate the FPSR flags in an "int", and our return type is also "int". However, the only callsite returns the same information as a uint32_t, and more generally we handle FPSR values in the code as uint32_t, not int. Bring this function in to line with that convention. There is no behaviour change because none of the FPSR bits we set in this function are bit 31. The input argument to the function remains 'int' because that is the return type of the softfloat get_float_exception_flags(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-6-peter.maydell@linaro.org
2025-01-28target/arm: Use FPSR_ constants in vfp_exceptbits_from_host()Peter Maydell1-6/+6
Use the FPSR_ named constants in vfp_exceptbits_from_host(), rather than hardcoded magic numbers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-5-peter.maydell@linaro.org
2025-01-28target/arm: arm_reset_sve_state() should set FPSR, not FPCRPeter Maydell1-1/+1
The pseudocode ResetSVEState() does: FPSR = ZeroExtend(0x0800009f<31:0>, 64); but QEMU's arm_reset_sve_state() called vfp_set_fpcr() by accident. Before the advent of FEAT_AFP, this was only setting a collection of RES0 bits, which vfp_set_fpsr() would then ignore, so the only effect was that we didn't actually set the FPSR the way we are supposed to do. Once FEAT_AFP is implemented, setting the bottom bits of FPSR will change the floating point behaviour. Call vfp_set_fpsr(), as we ought to. (Note for stable backports: commit 7f2a01e7368f9 moved this function from sme_helper.c to helper.c, but it had the same bug before the move too.) Cc: qemu-stable@nongnu.org Fixes: f84734b87461 ("target/arm: Implement SMSTART, SMSTOP") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250124162836.2332150-4-peter.maydell@linaro.org
2025-01-28tests/functional: Add a test for the arm microbit machineThomas Huth3-0/+33
We don't have any functional tests for this machine yet, thus let's add a test with a MicroPython binary that is available online (thanks to Joel Stanley for providing it, see: https://www.mail-archive.com/qemu-devel@nongnu.org/msg606064.html ). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250124101709.1591761-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-28rust: qemu-api: add sub-subclass to the integration testsZhao Liu1-3/+53
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-28rust/zeroable: Implement Zeroable with const_zero macroZhao Liu1-76/+61
The `const_zero` crate provides a nice macro to zero type-specific constants, which doesn't need to enumerates the fields one by one. Introduce the `const_zero` macro to QEMU (along with its documentation), and use it to simplify the implementation of `Zeroable` trait. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250123163143.679841-1-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-28rust: qdev: make reset take a shared referencePaolo Bonzini2-3/+3
Because register reset is within a borrow_mut() call, reset does not need anymore a mut reference to the PL011State. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-28rust: pl011: drop use of ControlFlowPaolo Bonzini1-21/+18
It is a poor match for what the code is doing, anyway. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-28rust: pl011: pull device-specific code out of MemoryRegionOps callbacksPaolo Bonzini2-26/+15
read() can now return a simple u64. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-28rust: pl011: remove duplicate definitionsPaolo Bonzini2-49/+29
Unify the "Interrupt" enum and the "INT_*" constants with a struct that contains the bits. The "int_level" and "int_enabled" fields could use a crate such as "bitflags". Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-28rust: pl011: wrap registers with BqlRefCellPaolo Bonzini2-22/+32
This is a step towards making memory ops use a shared reference to the device type; it's not yet possible due to the calls to character device functions. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-27rust: pl011: extract PL011RegistersPaolo Bonzini2-127/+166
Pull all the mutable fields of PL011State into a separate struct. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-27rust: pl011: pull interrupt updates out of read/write opsPaolo Bonzini1-36/+48
qemu_irqs are not part of the vmstate, therefore they will remain in PL011State. Update them if needed after regs_read()/regs_write(). Apply #[must_use] to functions that return whether the interrupt state could have changed, so that it's harder to forget the call to update(). Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-27rust: pl011: extract CharBackend receive logic into a separate functionPaolo Bonzini1-6/+9
Prepare for moving all references to the registers and the FIFO into a separate struct. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-27rust: pl011: extract conversion to RegisterOffsetPaolo Bonzini2-60/+79
As an added bonus, this also makes the new function return u32 instead of u64, thus factoring some casts into a single place. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-01-27Merge tag 'pull-aspeed-20250127' of https://github.com/legoater/qemu into ↵Stefan Hajnoczi14-38/+323
staging aspeed queue: * Fixed serial definitions on the command line * Fixed sdhci write protected pin on AST2600 EVB machine * Added timer support on AST2700 SoC * Updated buildroot and SDK images of functional tests * Removed sd devices creation when -nodefaults is used * Added software reset mode support on AST2600 SoC # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmeXSIwACgkQUaNDx8/7 # 7KH5Ew/+Ne9Z0lksOEUw5BJ6Qm3U2oLS90hcjo3MBHpmMHX0MXY2qYOKV2aS7spO # kvWpTUiPaT682X4IrBuxdCdi2F80dhJSmky81vMn7a3+DZgSsUoPEgw2Ophm5Q37 # 788qVEKk55F8m4r4ZCpAd3+Mc+3rVw6YQW/Rvu2+fVbfaLu6dE4fnQdXmDYc2EzF # pCYAcYlRp19dP0YnBJnv4/JK6Eybced1VG1cKGNy8VSyMY3vWM7ZOdP4Ybz+d88R # 0DNEIGRQJQZZFNxvkEJX/tPsK+m2M9G/t5YOuJP22EoF3L8v+rnt7yg+NWE4pbtI # dqzg8ikICidcP6NMYjTe6C2m9PBcKBhbPumRZOW1lWRoZOShy6cHO7KajJZ3oj8K # GUOEEh7i5tKbPGdg46ifc0waGMKh97S3dy/8V/N2XqPfL99TXfRAyiq0sG0mS1je # xGV9vN7LPJ9OYMri6U5SLewrWO93q7Vv4SBv7iDVupZ8Ww6wcJaCWgvUWjxbK7SH # qE003RvQYmK6gkCH4cYnI2LZBlJyp7wKdO7nG4K2vI+05GVpALTkZPcCQ84WhF5L # 8wO5wrQPalQrOwkvankqgEJOifWmBAi3Gs/3y/tRg+u4VHoPKcaXLujBqq8pZl6F # meYAzqqksFj8PJwiCVJVNcHpqvhmyBzvvPAf6NEgbRsDyUiFZAo= # =gOq1 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 27 Jan 2025 03:49:16 EST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20250127' of https://github.com/legoater/qemu: docs/system/arm/aspeed: Remove tacoma-bmc from the documentation aspeed/wdt: Support software reset mode for AST2600 aspeed/wdt: Fix coding style aspeed: Create sd devices only when defaults are enabled test/functional: Update buildroot images to 2024.11 test/functional: Update the Aspeed aarch64 test aspeed/soc: Support Timer for AST2700 hw/timer/aspeed: Add AST2700 Support hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB hw/sd/sdhci: Introduce a new Write Protected pin inverted property hw/arm/aspeed: fix connect_serial_hds_to_uarts Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-27Merge tag 'hppa-system-for-v10-pull-request' of ↵Stefan Hajnoczi3-36/+44
https://github.com/hdeller/qemu-hppa into staging hppa updates * Fixes booting a Linux kernel which is provided on the command line. * Allow more than 4GB RAM on 64-bit boxes # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZ5PvvgAKCRD3ErUQojoP # X7JQAQCn2MR4k4lfClDZHNmAFUNw51j56SB5HC/FCUKfOx4dCQD/Tf2OV/gstMOz # nfpvIH6ouXZ2/p5npzTyOt+A8fwUpw0= # =qrs7 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 24 Jan 2025 14:53:34 EST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'hppa-system-for-v10-pull-request' of https://github.com/hdeller/qemu-hppa: hw/hppa: Fix booting Linux kernel with initrd hw/hppa: Support up to 256 GiB RAM on 64-bit machines Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-27hw/arm/stellaris: Map both I2C controllersPhilippe Mathieu-Daudé1-8/+13
There are 2 I2C controllers, map them both, removing the unimplemented one. Keep the OLED controller on the first I2C bus. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250110160204.74997-7-philmd@linaro.org [PMM: tweak to appease maybe-use-uninitialized warning] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registersPhilippe Mathieu-Daudé1-8/+29
Add definitions (DCx_periph) for the DeviceCapability bits, replace direct bitmask checks with the DEV_CAP() macro, which use the extract/deposit API. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250110160204.74997-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/stellaris: Replace magic numbers by definitionsPhilippe Mathieu-Daudé1-10/+15
Add definitions for the number of controllers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250110160204.74997-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000Philippe Mathieu-Daudé1-2/+0
There is nothing mapped at 0x40002000. I2C#0 is already mapped at 0x40021000. Remove the invalid mapping added in commits aecfbbc97a2 & 394c8bbfb7a. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250110160204.74997-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/stellaris: Constify read-only arraysPhilippe Mathieu-Daudé1-3/+3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250110160204.74997-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/stellaris: Link each board schematicPhilippe Mathieu-Daudé1-0/+8
Board schematic is useful to corroborate GPIOs/IRQs wiring. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250110160204.74997-2-philmd@linaro.org [PMM: Use https:// URLs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/pci-host/designware: Expose MSI IRQBernhard Beschow7-8/+36
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share the MSI IRQ with the INTx lines, so expose it as a dedicated pin. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/char/imx_serial: Update all state before restarting ageing timerBernhard Beschow1-3/+3
Fixes characters to be "echoed" after each keystroke rather than after every other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY only after every other keystroke. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/char/imx_serial: Fix reset value of UFCR registerBernhard Beschow2-1/+2
The value of the UCFR register is respected when echoing characters to the terminal, but its reset value is reserved. Fix the reset value to the one documented in the datasheet. While at it move the related attribute out of the section of unimplemented registers since its value is actually respected. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/v7m: Remove use of &first_cpu in machine_init()Philippe Mathieu-Daudé11-11/+11
When instanciating the machine model, the machine_init() implementations usually create the CPUs, so have access to its first CPU. Use that rather then the &first_cpu global. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Samuel Tardieu <sam@rfc1149.net> Message-id: 20250112225614.33723-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/stellaris: Add 'armv7m' local variablePhilippe Mathieu-Daudé1-10/+11
While the TYPE_ARMV7M object forward its NVIC interrupt lines, it is somehow misleading to name it 'nvic'. Add the 'armv7m' local variable for clarity, but also keep the 'nvic' variable behaving like before when used for wiring IRQ lines. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20250112225614.33723-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'Philippe Mathieu-Daudé2-10/+10
The ARMv7MState object is not simply a CPU, it also contains the NVIC, SysTick timer, and various MemoryRegions. Rename the field as 'armv7m', like other Cortex-M boards. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20250112225614.33723-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27docs/system/arm/aspeed: Remove tacoma-bmc from the documentationThomas Huth1-2/+2
The tacoma-bmc machine has recently been removed, so let's remove it from the documentation now, too. Fixes: 2b1b66e01f ("arm: Remove tacoma-bmc machine") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250124174507.27348-1-thuth@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27aspeed/wdt: Support software reset mode for AST2600Jamin Lin1-1/+15
On the AST2400 and AST2500 platforms, the system can only be reset by enabling the WDT (Watchdog Timer) and waiting for the WDT timeout. However, starting from the AST2600 platform, the reset event can be triggered directly and intentionally by software, without relying on the WDT timeout. This mechanism, referred to as "software restart", is implemented in hardware. When using the software restart mechanism, the WDT counter is not enabled. To trigger a reset generation in software mode, write 0xAEEDF123 to register 0x24 and software mode reset only support SOC reset mode. A new function, "aspeed_wdt_is_soc_reset_mode", is introduced to determine whether the SoC reset mode is active. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250124030249.1706996-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27aspeed/wdt: Fix coding styleJamin Lin1-1/+2
Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250124030249.1706996-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27aspeed: Create sd devices only when defaults are enabledCédric Le Goater1-2/+2
When the -nodefaults option is set, sd devices should not be automatically created by the machine. Instead they should be defined on the command line. Note that it is not currently possible to define which bus an "sd-card" device is attached to: -blockdev node-name=drive0,driver=file,filename=/path/to/file.img \ -device sd-card,drive=drive0,id=sd0 and the first bus named "sd-bus" will be used. Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/20250122070909.1138598-10-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27test/functional: Update buildroot images to 2024.11Cédric Le Goater3-9/+9
The main changes compared to upstream 2024.11 buildroot are - bumped Linux to version 6.11.11 with a custom config - changed U-Boot to OpenBMC branch for more support - included extra target packages See branch [1] for more details. There is a slight output change when powering off the machine, the console now contains : reboot: Power off not available: System halted Adjust accordingly the expect string in do_test_arm_aspeed_buildroot_poweroff(). [1] https://github.com/legoater/buildroot/commits/aspeed-2024.11 Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250122070909.1138598-9-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27test/functional: Update the Aspeed aarch64 testCédric Le Goater1-5/+5
Bumped SDK version to v09.03. v09.04 is available but not yet supported in QEMU. Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250122070909.1138598-8-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27aspeed/soc: Support Timer for AST2700Jamin Lin1-0/+17
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets of 32-bit decrement counters. The base address of TIMER0 to TIMER7 as following. Base Address of Timer 0 = 0x12C1_0000 Base Address of Timer 1 = 0x12C1_0040 Base Address of Timer 2 = 0x12C1_0080 Base Address of Timer 3 = 0x12C1_00C0 Base Address of Timer 4 = 0x12C1_0100 Base Address of Timer 5 = 0x12C1_0140 Base Address of Timer 6 = 0x12C1_0180 Base Address of Timer 7 = 0x12C1_01C0 The interrupt of TIMER0 to TIMER7 as following. GICINT16 = TIMER 0 interrupt GICINT17 = TIMER 1 interrupt GICINT18 = TIMER 2 interrupt GICINT19 = TIMER 3 interrupt GICINT20 = TIMER 4 interrupt GICINT21 = TIMER 5 interrupt GICINT22 = TIMER 6 interrupt GICINT23 = TIMER 7 interrupt Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250113064455.1660564-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-27hw/timer/aspeed: Add AST2700 SupportJamin Lin2-0/+209
The timer controller include 8 sets of 32-bit decrement counters, based on either PCLK or 1MHZ clock and the design of timer controller between AST2600 and AST2700 are almost the same. TIMER0 – TIMER7 has their own individual control and interrupt status register. In other words, users are able to set timer control in register TMC10 with different TIMER base address and clear timer control and interrupt status in register TMC14 with different TIMER base address. Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write" callback functions and a new ast2700 class to support AST2700. The base address of TIMER0 to TIMER7 as following. Base Address of Timer 0 = 0x12C1_0000 Base Address of Timer 1 = 0x12C1_0040 Base Address of Timer 2 = 0x12C1_0080 Base Address of Timer 3 = 0x12C1_00C0 Base Address of Timer 4 = 0x12C1_0100 Base Address of Timer 5 = 0x12C1_0140 Base Address of Timer 6 = 0x12C1_0180 Base Address of Timer 7 = 0x12C1_01C0 The register address space of each TIMER is "0x40" , and uses the following formula to get the index and register of each TIMER. timer_index = offset >> 6; timer_offset = offset & 0x3f; The TMC010 is a counter control set and interrupt status register. Write "1" to TMC10[3:0] will set the specific bits to "1". Introduce a new "aspeed_2700_timer_set_ctrl" function to handle this register behavior. The TMC014 is a counter control clear and interrupt status register, to clear the specific bits to "0", it should write "1" to TMC14[3:0] on the same bit position. Introduce a new "aspeed_2700_timer_clear_ctrl" function to handle this register behavior. TMC014 does not support read operation. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Acked-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250113064455.1660564-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
generated by cgit v1.1 at 2025-09-20 16:24:17 +0000