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2023-06-22hw/net/dp8393x.c: move TYPE_DP8393X and dp8393xState into dp8393x.hMark Cave-Ayland2-31/+61
This is to enable them to be used outside of dp8393x.c. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: Jason Wang <jasowang@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-15-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: move VIA2 device to Q800MachineStateMark Cave-Ayland2-11/+17
Also change the instantiation of the VIA2 device to use object_initialize_child(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-14-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: move VIA1 device to Q800MachineStateMark Cave-Ayland2-7/+11
Also change the instantiation of the VIA1 device to use object_initialize_child(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: reimplement mac-io region aliasing using IO memory regionMark Cave-Ayland2-19/+82
The current use of aliased memory regions causes us 2 problems: firstly the output of "info qom-tree" is absolutely huge and difficult to read, and secondly we have already reached the internal limit for memory regions as adding any new memory region into the mac-io region causes QEMU to assert with "phys_section_add: Assertion `map->sections_nb < TARGET_PAGE_SIZE' failed". Implement the mac-io region aliasing using a single IO memory region that applies IO_SLICE_MASK representing the maximum size of the aliased region and then forwarding the access to the existing mac-io memory region using the address space API. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: introduce mac-io container memory regionMark Cave-Ayland2-0/+7
Move all devices from the IO region to within the container in preparation for updating the IO aliasing mechanism. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: move GLUE device to Q800MachineStateMark Cave-Ayland2-10/+16
Also change the instantiation of the GLUE device to use object_initialize_child(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800-glue.c: switch TypeInfo registration to use DEFINE_TYPES() macroMark Cave-Ayland1-16/+13
The use of the DEFINE_TYPES() macro will soon be recommended over the use of calling type_init() directly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: move GLUE device into separate q800-glue.c fileMark Cave-Ayland5-238/+306
This will allow the q800-glue.h header to be included separately so that the GLUE device can be referenced externally. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-8-mark.cave-ayland@ilande.co.uk> [lv: update comment] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: move ROM memory region to Q800MachineStateMark Cave-Ayland2-8/+7
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: move CPU object into Q800MachineStateMark Cave-Ayland2-5/+16
Also change the instantiation of the CPU to use object_initialize_child() followed by a separate realisation. Restrict valid CPU types to m68040. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-6-mark.cave-ayland@ilande.co.uk> [lv: update commit message] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: rename q800_init() to q800_machine_init()Mark Cave-Ayland1-2/+3
This will enable us later to distinguish between QOM initialisation and machine initialisation. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: introduce Q800MachineStateMark Cave-Ayland3-0/+43
This provides an overall container and owner for Machine-related objects such as MemoryRegions. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: add missing space after parent object in GLUEStateMark Cave-Ayland1-0/+1
This brings GLUEState in line with our current QOM guidelines. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230621085353.113233-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-22q800: fix up minor spacing issues in hw_compat_q800 GlobalProperty arrayMark Cave-Ayland1-5/+5
Ensure there is a space before the final closing brace for all global properties. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-06-21Merge tag 'pull-tricore-20230621-1' of https://github.com/bkoppelmann/qemu ↵Richard Henderson6-51/+237
into staging - Implement privilege levels for TriCore - Fix missing REG_PAIR() for insns using two 32 regs - Fix erroneously saving PSW.CDC on CALL insns - Added some missing v1.6.2 insns # -----BEGIN PGP SIGNATURE----- # # iQJTBAABCgA9FiEEbmNqfoPy3Qz6bm43CtLGOWtpyhQFAmSTIWsfHGtiYXN0aWFu # QG1haWwudW5pLXBhZGVyYm9ybi5kZQAKCRAK0sY5a2nKFEVCEACQFRGj/7ADOWm3 # lhkHGgkwpTgx+YKgeI4rfQ5/AKie9b7BUNljPVp1m2AvPFHU/r/0POzziCTDM+Ty # M90h5gsEgxNRRVS1T+VkfFTKop7yImo48niDBF4mByP9DZGweCvGEvPD2g/FYvLP # 0Up13F0NiWKMvocKp/jjI5qejpJqwtn1hjWHTpEXya3u+K/iEku1alI72Xo2oMKW # pKW2iO/mC4cuEzOdpZt4LSzs9ZMsVpFzVn81VIda9CU2rlSpu+oQevgdWWJhgZGa # 520JnIsrervsJumBWPxh9R0nrjuhHu34I4HXD38eGhD+Ioz2DQnHy2bA99pIVR7B # qtHoDNhl7wqWgXBqntS9HvnvDAFyYdVM6aLqw9C7AxKXdRBuxy14R3/hrwMZghRs # vYx3GUcFHSMJT1tkc8a/P14/mz5SB6/cdjVgPQtTCPBJccly4oc4EG3qn7wYqowZ # Pbq48h+3+QZ7BsC9sT2AiPq+AmLjxRZRq7SE6YrYrjRDIJz/3IoTR600KW5XsFsj # gZu/SYWdbNXAVr4c7CCg77lXXQ2/GhPHgCYFjL3djIKwlPP79bhT4cvLXK71yF/4 # 3RcCBt9kRggxDz6E/4I+u5cE4oMbyN1f6AoIn80GUheDstWMACYph5RhbIskxRhY # PWwJ8ML0c7SOy0A74UbCT82gn1He1A== # =IKrz # -----END PGP SIGNATURE----- # gpg: Signature made Wed 21 Jun 2023 06:12:27 PM CEST # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * tag 'pull-tricore-20230621-1' of https://github.com/bkoppelmann/qemu: target/tricore: Fix ICR.IE offset in RESTORE insn target/tricore: Honour privilege changes on PSW write target/tricore: Implement privilege level for all insns target/tricore: Introduce priv tb flag target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr() target/tricore: ENABLE exit to main-loop target/tricore: Introduce DISAS_TARGET_EXIT target/tricore: Fix RR_JLI clobbering reg A[11] target/tricore: Fix helper_ret() not correctly restoring PSW target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs target/tricore: Correctly fix saving PSW.CDE to CSA on call target/tricore: Fix out-of-bounds index in imask instruction target/tricore: Add DISABLE insn variant target/tricore: Implement SYCSCALL insn target/tricore: Add shuffle insn target/tricore: Add crc32.b insn target/tricore: Add crc32l.w insn target/tricore: Add LHA insn target/tricore: Add popcnt.w insn target/tricore: Introduce ISA 1.6.2 feature Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-21target/tricore: Fix ICR.IE offset in RESTORE insnBastian Koppelmann1-1/+3
from ISA v1.6.1 onwards the bit position of ICR.IE changed. ctx->icr_ie_offset contains the correct value for the ISA version used by the vCPU. We also need to exit this tb here, as we might have enabled interrupts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-9-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Honour privilege changes on PSW writeBastian Koppelmann1-1/+1
the CPU can change the privilege level by writing the corresponding bits in PSW. If this happens all instructions after this 'mtcr' in the TB are translated with the wrong privilege level. So we have to exit to the cpu_loop() and start translating again with the new privilege level. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-8-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Implement privilege level for all insnsBastian Koppelmann1-10/+33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-7-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Introduce priv tb flagBastian Koppelmann2-11/+20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-6-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()Bastian Koppelmann1-1/+6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-5-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: ENABLE exit to main-loopBastian Koppelmann1-0/+5
so we can recognize exceptions after re-enabling interrupts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-4-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Introduce DISAS_TARGET_EXITBastian Koppelmann1-13/+12
this replaces all calls to tcg_gen_exit_tb() and moves them to tricore_tb_stop(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-3-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Fix RR_JLI clobbering reg A[11]Bastian Koppelmann1-1/+1
if A[r1] == A[11], then we would overwrite the destination address of the jump with the return address. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-2-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Fix helper_ret() not correctly restoring PSWBastian Koppelmann1-4/+4
We are always taking the TRICORE_FEATURE_13 branch as every CPU has TRICORE_FEATURE_13. For CPUs with ISA > 1.3 we have to take the else branch. We fix this by inverting the condition. We check for TRICORE_FEATURE_131, which every CPU except TRICORE_FEATURE_13 CPUs have. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1700 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-5-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regsBastian Koppelmann1-2/+9
some insns were not checking if an even index was used to access a 64 bit register. In the worst case that could lead to a buffer overflow as reported in https://gitlab.com/qemu-project/qemu/-/issues/1698. Reported-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-4-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Correctly fix saving PSW.CDE to CSA on callBastian Koppelmann1-1/+6
we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612113245.56667-3-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Fix out-of-bounds index in imask instructionSiqi Chen1-0/+1
When translating "imask" instruction of Tricore architecture, QEMU did not check whether the register index was out of bounds, resulting in a global-buffer-overflow. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698 Reported-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Siqi Chen <coc.cyqh@gmail.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230612065633.149152-1-coc.cyqh@gmail.com> Message-Id: <20230612113245.56667-2-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add DISABLE insn variantBastian Koppelmann2-1/+11
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext as with the other DISABLE insn. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-9-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Implement SYCSCALL insnBastian Koppelmann1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-8-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add shuffle insnBastian Koppelmann4-0/+46
this is based on code by volumit (https://github.com/volumit/qemu/). Reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 and https://gitlab.com/qemu-project/qemu/-/issues/1452. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-7-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add crc32.b insnBastian Koppelmann4-0/+17
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-6-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add crc32l.w insnBastian Koppelmann4-5/+23
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-5-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add LHA insnBastian Koppelmann2-3/+20
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-4-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Add popcnt.w insnBastian Koppelmann2-0/+8
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-3-kbastian@mail.uni-paderborn.de>
2023-06-21target/tricore: Introduce ISA 1.6.2 featureBastian Koppelmann2-0/+14
we also introduce the tc37x CPU that implements that ISA version. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230614100039.1337971-2-kbastian@mail.uni-paderborn.de>
2023-06-21Revert "cputlb: Restrict SavedIOTLB to system emulation"Peter Maydell1-4/+2
This reverts commit d7ee93e24359703debf4137f4cc632563aa4e8d1. That commit tries to make a field in the CPUState struct not be present when CONFIG_USER_ONLY is set. Unfortunately, you can't conditionally omit fields in structs like this based on ifdefs that are set per-target. If you try it, then code in files compiled per-target (where CONFIG_USER_ONLY is or can be set) will disagree about the struct layout with files that are compiled once-only (where this kind of ifdef is never set). This manifests specifically in 'make check-tcg' failing, because code in cpus-common.c that sets up the CPUState::cpu_index field puts it at a different offset from the code in plugins/core.c in qemu_plugin_vcpu_init_hook() which reads the cpu_index field. The latter then hits an assert because from its point of view every thread has a 0 cpu_index. There might be other weird behaviour too. Mostly we catch this kind of bug because the CONFIG_whatever is listed in include/exec/poison.h and so the reference to it in build-once source files will then cause a compiler error. Unfortunately CONFIG_USER_ONLY is an exception to that: we have some places where we use it in "safe" ways in headers that will be seen by once-only source files (e.g. ifdeffing out function prototypes) and it would be a lot of refactoring to be able to get to a position where we could poison it. This leaves us in a "you have to be careful to walk around the bear trap" situation... Fixes: d7ee93e243597 ("cputlb: Restrict SavedIOTLB to system emulation") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230620175712.1331625-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-21Merge tag 'seabios-hppa-v7-pull-request' of ↵Richard Henderson2-0/+0
https://github.com/hdeller/qemu-hppa into staging hppa: New SeaBIOS-hppa version 7 ROM New SeaBIOS-hppa version 7 ROM to fix Debian-12 CD-ROM boot issues. Signed-off-by: Helge Deller <deller@gmx.de> # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZJIExQAKCRD3ErUQojoP # XypaAP9j0YWdl1ovPiyw8fTdY5U6yCKGIjqtkXzk4egPbzkU1AD7BxMY+GbDSKv8 # Lt9K+R4cu0EVxfYsz17e780wSMLPcwc= # =M8NU # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Jun 2023 09:57:57 PM CEST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'seabios-hppa-v7-pull-request' of https://github.com/hdeller/qemu-hppa: target/hppa: New SeaBIOS-hppa version 7 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20target/hppa: New SeaBIOS-hppa version 7Helge Deller2-0/+0
Update SeaBIOS-hppa to version 7 which fixes a boot problem with Debian-12 install CD images. The problem with Debian-12 is, that the ramdisc got bigger than what the firmware could load in one call to the LSI scsi driver. Signed-off-by: Helge Deller <deller@gmx.de>
2023-06-20Merge tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson125-862/+872
tcg: Define _CALL_AIX for clang on ppc64 accel/tcg: Build fix for macos catalina accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN accel/tcg: Restrict SavedIOTLB to system emulation accel/tcg: Use generic 'helper-proto-common.h' header plugins: Remove unused 'exec/helper-proto.h' header *: Check for CONFIG_USER_ONLY instead of CONFIG_SOFTMMU # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSRYmIdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8zbAgAlX4GcShS1OU1BDRe # b0HHHj1fFBB/9yk8f/5WuQb2snYS+pcZCez9XeT175ugovXSOz+shvmFrbRPvpfj # q8C88CIKCJRsXnhWqKWOKDqgTttu2WNXOvCe0eCZbUoGQ9K1seMvUBq6T50fNv2H # fXeHtLSu/+jiHIN3+woJqdgrkp0cko2rrpnwIpjuIsY1iz/J/VKEHmnv7Ah+GsRs # OTYnR7iN6uhBXVll14r3UCylbgdEz58sSSEi3dYYfaTRuijDwOzM0evhk6+5XzHP # DYwGdbtDE5HJOrCLiKegk80Gh6v1XVZQWnn9PdiN1eJcQsWNT9mYV9/4IsCVrsF4 # 8r5KUg== # =JmjK # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Jun 2023 10:25:06 AM CEST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu: cputlb: Restrict SavedIOTLB to system emulation exec/cpu-defs: Check for SOFTMMU instead of !USER_ONLY accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' header plugins: Remove unused 'exec/helper-proto.h' header meson: Replace softmmu_ss -> system_ss meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY accel/tcg: Check for USER_ONLY definition instead of SOFTMMU one hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU one target/ppc: Check for USER_ONLY definition instead of SOFTMMU one target/m68k: Check for USER_ONLY definition instead of SOFTMMU one target/tricore: Remove pointless CONFIG_SOFTMMU guard target/i386: Simplify i386_tr_init_disas_context() tcg/ppc: Define _CALL_AIX for clang on ppc64(be) accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN host/include/x86_64: Use __m128i for "x" constraints Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20cputlb: Restrict SavedIOTLB to system emulationPhilippe Mathieu-Daudé1-2/+4
Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in case of reset") added the SavedIOTLB structure -- which is system emulation specific -- in the generic CPUState structure. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20exec/cpu-defs: Check for SOFTMMU instead of !USER_ONLYPhilippe Mathieu-Daudé1-6/+6
We want to check the softmmu tlb availability, not if we are targetting system emulation. Besides, this code could be used by user emulation in the future. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230605230216.17202-1-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' headerPhilippe Mathieu-Daudé1-1/+1
We only need lookup_tb_ptr() prototype. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230611085846.21415-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20plugins: Remove unused 'exec/helper-proto.h' headerPhilippe Mathieu-Daudé1-1/+0
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230611085846.21415-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé101-714/+714
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé13-18/+18
Since we *might* have user emulation with softmmu, use the clearer 'CONFIG_SYSTEM_ONLY' key to check for system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé1-0/+1
We use the CONFIG_USER_ONLY key to describe user emulation, and the CONFIG_SOFTMMU key to describe system emulation. Alias it as 'CONFIG_SYSTEM_ONLY' for parity with user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-8-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20accel/tcg: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2-5/+5
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert some if() ladders for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-7-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2-53/+53
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert the #ifdef'ry in TCGCPUOps structure for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-6-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20target/ppc: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2-14/+12
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20230613133347.82210-5-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20target/m68k: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé4-25/+23
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert some if() ladders for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-4-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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