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2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt3-0/+8
The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt4-0/+9
fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis3-5/+14
Add support for disabling/enabling the "Counters" extension. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Remove user version informationAlistair Francis2-25/+9
Remove the user version information. This was never used and never publically exposed in a release of QEMU, so let's just remove it. In future to manage versions we can extend the extension properties to specify version. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis1-0/+6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1Alistair Francis1-0/+8
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new 1.10.0 and the ratified 1.11.0. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis1-3/+5
Set the priv spec version 1.11.0 as the default and allow selecting it via the command line. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis2-2/+16
1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Fix counter access semantics, change commit message to indicate the behavior is fully emulated.] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis2-1/+2
Add support for the ratified RISC-V privledge spec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis2-14/+17
Restructure the deprecated CPUs to make it clear in the code that these are depreated. They are already marked as deprecated in qemu-deprecated.texi. There are no functional changes. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt2-7/+8
Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(), where a pair of recently added MemoryRegion instances would not be freed if there were errors elsewhere in the function. The fix here is to simply not use dynamic allocation for these instances: there's always one of each in SiFiveESoCState, so instead we just include them within the struct. Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device") Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-06-23riscv: virt: Correct pci "bus-range" encodingBin Meng1-1/+1
The largest pci bus number should be calculated from ECAM size, instead of its base address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Fix a PMP check with the correct access sizeHesham Almatary1-2/+1
The PMP check should be of the memory access size rather than TARGET_PAGE_SIZE. Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Fix a PMP bug where it succeeds even if PMP entry is offHesham Almatary1-4/+5
The current implementation returns 1 (PMP check success) if the address is in range even if the PMP entry is off. This is a bug. For example, if there is a PMP check in S-Mode which is in range, but its PMP entry is off, this will succeed, which it should not. The patch fixes this bug by only checking the PMP permissions if the address is in range and its corresponding PMP entry it not off. Otherwise, it will keep the ret = -1 which will be checked and handled correctly at the end of the function. Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary2-1/+10
The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Suggested-by: Jonathan Behrens <fintelia@gmail.com> Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary3-5/+13
The current PMP check function checks for env->priv which is not the effective memory privilege mode. For example, mstatus.MPRV could be set while executing in M-Mode, and in that case the privilege mode for the PMP check should be S-Mode rather than M-Mode (in env->priv) if mstatus.MPP == PRV_S. This patch passes the effective memory privilege mode to the PMP check. Functions that call the PMP check should pass the correct memory privilege mode after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists). Suggested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary1-3/+6
Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary1-0/+1
The current implementation unnecessarily checks for PMP even if MMU translation failed. This may trigger a wrong PMP access exception instead of a page exception. For example, the very first instruction fetched after the first satp write in S-Mode will trigger a PMP access fault instead of an instruction fetch page fault. This patch prioritises MMU exceptions over PMP exceptions and only checks for PMP if MMU translation succeeds. This patch is required for future commits that properly report PMP exception violations if PTW succeeds. Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark3-0/+19
This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark <mjc@sifive.com> [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23target/riscv: Fix PMP range boundary address bugDayeol Lee1-1/+1
A wrong address is passed to `pmp_is_in_range` while checking if a memory access is within a PMP range. Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea) is set to the last address in the range (i.e., pmp base + pmp size - 1), memory accesses containg the last address in the range will always fail. For example, assume that a PMP range is 4KB from 0x87654000 such that the last address within the range is 0x87654fff. 1-byte access to 0x87654fff should be considered to be fully inside the PMP range. However the access now fails and complains partial inclusion because pmp_is_in_range(env, i, addr + size) returns 0 whereas pmp_is_in_range(env, i, addr) returns 1. Signed-off-by: Dayeol Lee <dayeol@berkeley.edu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23sifive_prci: Read and write PRCI registersNathaniel Graff2-8/+73
Writes to the SiFive PRCI registers are preserved while leaving the ready bits set for the HFX/HFR oscillators and the lock bit set for the PLL. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis2-2/+79
This patch allows us to enable/disable the RISC-V ISA extensions from the QEMU command line. This works with the rv32 and rv64 machines. The idea is that in the future we can now add extensions and leave them disabled by default until enabled by the user. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-21Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' ↵Peter Maydell264-942/+2605
into staging MIPS queue for June 21st, 2019 # gpg: Signature made Fri 21 Jun 2019 10:46:57 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-21-2019: target/mips: Fix emulation of ILVR.<B|H|W> on big endian host target/mips: Fix emulation of ILVL.<B|H|W> on big endian host target/mips: Fix emulation of ILVOD.<B|H|W> on big endian host target/mips: Fix emulation of ILVEV.<B|H|W> on big endian host tests/tcg: target/mips: Amend tests for MSA pack instructions tests/tcg: target/mips: Include isa/ase and group name in test output target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c target/mips: Fix some space checkpatch errors in translate.c MAINTAINERS: Consolidate MIPS disassembler-related items MAINTAINERS: Update file items for MIPS Malta board Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-21Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell27-329/+1506
* Nuke hw_compat_4_0_1 and pc_compat_4_0_1 (Greg) * Static analysis fixes (Igor, Lidong) * X86 Hyper-V CPUID improvements (Vitaly) * X86 nested virt migration (Liran) * New MSR-based features (Xiaoyao) # gpg: Signature made Fri 21 Jun 2019 12:25:42 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (25 commits) hw: Nuke hw_compat_4_0_1 and pc_compat_4_0_1 util/main-loop: Fix incorrect assertion sd: Fix out-of-bounds assertions target/i386: kvm: Add nested migration blocker only when kernel lacks required capabilities target/i386: kvm: Add support for KVM_CAP_EXCEPTION_PAYLOAD target/i386: kvm: Add support for save and restore nested state vmstate: Add support for kernel integer types linux-headers: sync with latest KVM headers from Linux 5.2 target/i386: kvm: Block migration for vCPUs exposed with nested virtualization target/i386: kvm: Re-inject #DB to guest with updated DR6 target/i386: kvm: Use symbolic constant for #DB/#BP exception constants KVM: Introduce kvm_arch_destroy_vcpu() target/i386: kvm: Delete VMX migration blocker on vCPU init failure target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY i386/kvm: add support for Direct Mode for Hyper-V synthetic timers i386/kvm: hv-evmcs requires hv-vapic i386/kvm: hv-tlbflush/ipi require hv-vpindex i386/kvm: hv-stimer requires hv-time and hv-synic i386/kvm: implement 'hv-passthrough' mode i386/kvm: document existing Hyper-V enlightenments ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-21hw: Nuke hw_compat_4_0_1 and pc_compat_4_0_1Greg Kurz5-17/+9
Commit c87759ce876a fixed a regression affecting pc-q35 machines by introducing a new pc-q35-4.0.1 machine version to be used instead of pc-q35-4.0. The only purpose was to revert the default behaviour of not using split irqchip, but the change also introduced the usual hw_compat and pc_compat bits, and wired them for pc-q35 only. This raises questions when it comes to add new compat properties for 4.0* machine versions of any architecture. Where to add them ? In 4.0, 4.0.1 or both ? Error prone. Another possibility would be to teach all other architectures about 4.0.1. This solution isn't satisfying, especially since this is a pc-q35 specific issue. It turns out that the split irqchip default is handled in the machine option function and doesn't involve compat lists at all. Drop all the 4.0.1 compat lists and use the 4.0 ones instead in the 4.0.1 machine option function. Move the compat props that were added to the 4.0.1 since c87759ce876a to 4.0. Even if only hw_compat_4_0_1 had an impact on other architectures, drop pc_compat_4_0_1 as well for consistency. Fixes: c87759ce876a "q35: Revert to kernel irqchip" Suggested-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <156051774276.244890.8660277280145466396.stgit@bahia.lan> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21util/main-loop: Fix incorrect assertionLidong Chen1-1/+1
The check for poll_fds in g_assert() was incorrect. The correct assertion should check "n_poll_fds + w->num <= ARRAY_SIZE(poll_fds)" because the subsequent for-loop is doing access to poll_fds[n_poll_fds + i] where i is in [0, w->num). This could happen with a very high number of file descriptors and/or wait objects. Signed-off-by: Lidong Chen <lidong.chen@oracle.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Liam Merwick <liam.merwick@oracle.com> Reviewed-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <ded30967982811617ce7f0222d11228130c198b7.1560806687.git.lidong.chen@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21sd: Fix out-of-bounds assertionsLidong Chen1-2/+2
Due to an off-by-one error, the assert statements allow an out-of-bound array access. This doesn't happen in practice, but the static analyzer notices. Signed-off-by: Lidong Chen <lidong.chen@oracle.com> Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-Id: <6b19cb7359a10a6bedc3ea0fce22fed3ef93c102.1560806687.git.lidong.chen@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: kvm: Add nested migration blocker only when kernel lacks ↵Liran Alon2-3/+8
required capabilities Previous commits have added support for migration of nested virtualization workloads. This was done by utilising two new KVM capabilities: KVM_CAP_NESTED_STATE and KVM_CAP_EXCEPTION_PAYLOAD. Both which are required in order to correctly migrate such workloads. Therefore, change code to add a migration blocker for vCPUs exposed with Intel VMX or AMD SVM in case one of these kernel capabilities is missing. Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Message-Id: <20190619162140.133674-11-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: kvm: Add support for KVM_CAP_EXCEPTION_PAYLOADLiran Alon6-24/+187
Kernel commit c4f55198c7c2 ("kvm: x86: Introduce KVM_CAP_EXCEPTION_PAYLOAD") introduced a new KVM capability which allows userspace to correctly distinguish between pending and injected exceptions. This distinguish is important in case of nested virtualization scenarios because a L2 pending exception can still be intercepted by the L1 hypervisor while a L2 injected exception cannot. Furthermore, when an exception is attempted to be injected by QEMU, QEMU should specify the exception payload (CR2 in case of #PF or DR6 in case of #DB) instead of having the payload already delivered in the respective vCPU register. Because in case exception is injected to L2 guest and is intercepted by L1 hypervisor, then payload needs to be reported to L1 intercept (VMExit handler) while still preserving respective vCPU register unchanged. This commit adds support for QEMU to properly utilise this new KVM capability (KVM_CAP_EXCEPTION_PAYLOAD). Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-10-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: kvm: Add support for save and restore nested stateLiran Alon5-0/+290
Kernel commit 8fcc4b5923af ("kvm: nVMX: Introduce KVM_CAP_NESTED_STATE") introduced new IOCTLs to extract and restore vCPU state related to Intel VMX & AMD SVM. Utilize these IOCTLs to add support for migration of VMs which are running nested hypervisors. Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Tested-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-9-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21vmstate: Add support for kernel integer typesLiran Alon1-0/+26
Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190619162140.133674-8-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21linux-headers: sync with latest KVM headers from Linux 5.2Liran Alon1-11/+22
Improve the KVM_{GET,SET}_NESTED_STATE structs by detailing the format of VMX nested state data in a struct. In order to avoid changing the ioctl values of KVM_{GET,SET}_NESTED_STATE, there is a need to preserve sizeof(struct kvm_nested_state). This is done by defining the data struct as "data.vmx[0]". It was the most elegant way I found to preserve struct size while still keeping struct readable and easy to maintain. It does have a misfortunate side-effect that now it has to be accessed as "data.vmx[0]" rather than just "data.vmx". Because we are already modifying these structs, I also modified the following: * Define the "format" field values as macros. * Rename vmcs_pa to vmcs12_pa for better readability. Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Message-Id: <20190619162140.133674-7-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: kvm: Block migration for vCPUs exposed with nested virtualizationLiran Alon3-13/+19
Commit d98f26073beb ("target/i386: kvm: add VMX migration blocker") added a migration blocker for vCPU exposed with Intel VMX. However, migration should also be blocked for vCPU exposed with AMD SVM. Both cases should be blocked because QEMU should extract additional vCPU state from KVM that should be migrated as part of vCPU VMState. E.g. Whether vCPU is running in guest-mode or host-mode. Fixes: d98f26073beb ("target/i386: kvm: add VMX migration blocker") Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-6-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/mips: Fix emulation of ILVR.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVR.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix emulation of ILVL.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVL.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix emulation of ILVOD.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVOD.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix emulation of ILVEV.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVEV.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21tests/tcg: target/mips: Amend tests for MSA pack instructionsAleksandar Markovic13-12/+708
Add tests for cases when destination register is the same as one of source registers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561031359-6727-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21tests/tcg: target/mips: Include isa/ase and group name in test outputAleksandar Markovic260-736/+1492
For better appearance and usefullnes, include ISA/ASE name and instruction group name in the output of tests. For example, all this data will be displayed for FMAX_A.W test: | MSA | Float Max Min | FMAX_A.W | | PASS: 80 | FAIL: 0 | elapsed time: 0.16 ms | (the data will be displayed in one row; they are presented here in two rows not to exceed the width of the commit message) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561031359-6727-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix if-else-switch-case arms checkpatch errors in translate.cAleksandar Markovic1-72/+133
Remove if-else-switch-case-arms-related checkpatch errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561037595-14413-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix some space checkpatch errors in translate.cAleksandar Markovic1-118/+122
Remove some space-related checkpatch warning. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561037595-14413-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21MAINTAINERS: Consolidate MIPS disassembler-related itemsAleksandar Markovic1-4/+1
Eliminate duplicate MIPS disassembler-related items in the MAINTAINERS file, and use wildcards to shorten the list of involved files. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561037595-14413-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21MAINTAINERS: Update file items for MIPS Malta boardAleksandar Markovic1-0/+1
hw/mips/gt64xxx_pci.c is used for Malta only, so it is logical to place this file in Malta board section of the MAINTAINERS file. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561037595-14413-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/i386: kvm: Re-inject #DB to guest with updated DR6Liran Alon1-0/+3
If userspace (QEMU) debug guest, when #DB is raised in guest and intercepted by KVM, KVM forwards information on #DB to userspace instead of injecting #DB to guest. While doing so, KVM don't update vCPU DR6 but instead report the #DB DR6 value to userspace for further handling. See KVM's handle_exception() DB_VECTOR handler. QEMU handler for this case is kvm_handle_debug(). This handler basically checks if #DB is related to one of user set hardware breakpoints and if not, it re-inject #DB into guest. The re-injection is done by setting env->exception_injected to #DB which will later be passed as events.exception.nr to KVM_SET_VCPU_EVENTS ioctl by kvm_put_vcpu_events(). However, in case userspace re-injects #DB, KVM expects userspace to set vCPU DR6 as reported to userspace when #DB was intercepted! Otherwise, KVM_REQ_EVENT handler will inject #DB with wrong DR6 to guest. Fix this issue by updating vCPU DR6 appropriately when re-inject #DB to guest. Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-5-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: kvm: Use symbolic constant for #DB/#BP exception constantsLiran Alon1-4/+4
Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-4-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21KVM: Introduce kvm_arch_destroy_vcpu()Liran Alon8-0/+48
Simiar to how kvm_init_vcpu() calls kvm_arch_init_vcpu() to perform arch-dependent initialisation, introduce kvm_arch_destroy_vcpu() to be called from kvm_destroy_vcpu() to perform arch-dependent destruction. This was added because some architectures (Such as i386) currently do not free memory that it have allocated in kvm_arch_init_vcpu(). Suggested-by: Maran Wilson <maran.wilson@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-3-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: kvm: Delete VMX migration blocker on vCPU init failureLiran Alon1-2/+5
Commit d98f26073beb ("target/i386: kvm: add VMX migration blocker") added migration blocker for vCPU exposed with Intel VMX because QEMU doesn't yet contain code to support migration of nested virtualization workloads. However, that commit missed adding deletion of the migration blocker in case init of vCPU failed. Similar to invtsc_mig_blocker. This commit fix that issue. Fixes: d98f26073beb ("target/i386: kvm: add VMX migration blocker") Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Message-Id: <20190619162140.133674-2-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITYXiaoyao Li3-1/+35
MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only enumerates the feature split lock detection (via bit 5) by now. The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30]. The latest kernel patches about them can be found here: https://lkml.org/lkml/2019/4/24/1909 Signed-off-by: Xiaoyao Li <xiaoyao.li@linux.intel.com> Message-Id: <20190617153654.916-1-xiaoyao.li@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21i386/kvm: add support for Direct Mode for Hyper-V synthetic timersVitaly Kuznetsov5-0/+23
Hyper-V on KVM can only use Synthetic timers with Direct Mode (opting for an interrupt instead of VMBus message). This new capability is only announced in KVM_GET_SUPPORTED_HV_CPUID. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20190517141924.19024-10-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-21i386/kvm: hv-evmcs requires hv-vapicVitaly Kuznetsov1-1/+2
Enlightened VMCS is enabled by writing to a field in VP assist page and these require virtual APIC. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20190517141924.19024-9-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2024-07-22 06:27:11 +0000