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2017-09-07tcg: Infrastructure for managing constant poolsRichard Henderson4-1/+119
A new shared header tcg-pool.inc.c adds new_pool_label, for registering a tcg_target_ulong to be emitted after the generated code, plus relocation data to install a pointer to the data. A new pointer is added to the TCGContext, so that we dump the constant pool as data, not code. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg: Rearrange ldst label trackingRichard Henderson19-91/+57
Dispense with TCGBackendData, as it has never been used for more than holding a single pointer. Use a define in the cpu/tcg-target.h to signal requirement for TCGLabelQemuLdst, so that we can drop the no-op tcg-be-null.h stubs. Rename tcg-be-ldst.h to tcg-ldst.inc.c. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.hRichard Henderson16-116/+106
Replace the USE_DIRECT_JUMP ifdef with a TCG_TARGET_HAS_direct_jump boolean test. Replace the tb_set_jmp_target1 ifdef with an unconditional function tb_target_set_jmp_target. While we're touching all backends, add a parameter for tb->tc_ptr; we're going to need it shortly for some backends. Move tb_set_jmp_target and tb_add_jump from exec-all.h to cpu-exec.c. This opens the possibility for TCG_TARGET_HAS_direct_jump to be a runtime decision -- based on host cpu capabilities, the size of code_gen_buffer, or a future debugging switch. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/tci: Add TCG_TARGET_DEFAULT_MORichard Henderson1-0/+5
Missed being added as part of 71650df7b0ee. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-09-06' into ↵Peter Maydell10-111/+141
staging nbd patches for 2017-09-06 - Daniel P. Berrange: [0/2] Fix / skip recent iotests with LUKS driver - Eric Blake: [0/3] nbd: Use common read/write-all qio functions # gpg: Signature made Wed 06 Sep 2017 16:17:55 BST # gpg: using RSA key 0xA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2017-09-06: nbd: Use new qio_channel_*_all() functions io: Add new qio_channel_read{, v}_all_eof functions io: Yield rather than wait when already in coroutine iotests: blacklist 194 with the luks driver iotests: rewrite 192 to use _launch_qemu to fix LUKS support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch ↵Peter Maydell48-213/+978
'remotes/pmaydell/tags/pull-target-arm-20170907' into staging target-arm: * cleanups converting to DEFINE_PROP_LINK * allwinner-a10: mark as not user-creatable * initial patches working towards ARMv8M support * implement generating aborts on memory transaction failures * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later # gpg: Signature made Thu 07 Sep 2017 14:26:07 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits) target/arm: Add Jazelle feature target/arm: Implement new do_transaction_failed hook hw/arm: Set ignore_memory_transaction_failures for most ARM boards boards.h: Define new flag ignore_memory_transaction_failures target/arm: Implement BXNS, and banked stack pointers target/arm: Move regime_is_secure() to target/arm/internals.h target/arm: Make CFSR register banked for v8M target/arm: Make MMFAR banked for v8M target/arm: Make CCR register banked for v8M target/arm: Make MPU_CTRL register banked for v8M target/arm: Make MPU_RNR register banked for v8M target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M target/arm: Make VTOR register banked for v8M nvic: Add NS alias SCS region target/arm: Make CONTROL register banked for v8M target/arm: Make FAULTMASK register banked for v8M target/arm: Make PRIMASK register banked for v8M target/arm: Make BASEPRI register banked for v8M target/arm: Add MMU indexes for secure v8M ... # Conflicts: # target/arm/translate.c
2017-09-07Merge remote-tracking branch ↵Peter Maydell9-85/+35
'remotes/dgilbert/tags/pull-migration-20170906a' into staging migration pull 2017-09-06 # gpg: Signature made Wed 06 Sep 2017 19:39:23 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20170906a: migration: dump str in migrate_set_state trace snapshot/tests: Try loadvm twice migration: Reset rather than destroy main_thread_load_event runstate/migrate: Two more transitions host-utils: Simplify pow2ceil() host-utils: Proactively fix pow2floor(), switch to unsigned xbzrle: Drop unused cache_resize() migration: Report when bdrv_inactivate_all fails Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/rth/tags/pull-tgt-20170906' into stagingPeter Maydell17-570/+909
tcg generic translate loop v15 # gpg: Signature made Wed 06 Sep 2017 17:02:31 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tgt-20170906: (32 commits) target/arm: Perform per-insn cross-page check only for Thumb target/arm: Split out thumb_tr_translate_insn target/arm: Move ss check to init_disas_context target/arm: [a64] Move page and ss checks to init_disas_context target/arm: [tcg] Port to generic translation framework target/arm: [tcg,a64] Port to disas_log target/arm: [tcg] Port to disas_log target/arm: [tcg,a64] Port to tb_stop target/arm: [tcg] Port to tb_stop target/arm: [tcg,a64] Port to translate_insn target/arm: [tcg] Port to translate_insn target/arm: [tcg,a64] Port to breakpoint_check target/arm: [tcg,a64] Port to insn_start target/arm: [tcg] Port to insn_start target/arm: [tcg] Port to tb_start target/arm: [tcg,a64] Port to init_disas_context target/arm: [tcg] Port to init_disas_context target/arm: [tcg] Port to DisasContextBase target/i386: [tcg] Port to generic translation framework target/i386: [tcg] Port to disas_log ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07target/arm: Add Jazelle featurePortia Stephens3-1/+5
This adds a feature bit indicating support of the (trivial) Jazelle implementation if ARM_FEATURE_V6 is set or if the processor is arm926 or arm1026. This fixes the issue that any BXJ instruction will result in an illegal_op. BXJ instructions will now check if the architecture supports ARM_FEATURE_JAZELLE. Signed-off-by: Portia Stephens <portia.stephens@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com [PMM: edited commit message and comment text a bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07target/arm: Implement new do_transaction_failed hookPeter Maydell3-0/+54
Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1504626814-23124-4-git-send-email-peter.maydell@linaro.org
2017-09-07hw/arm: Set ignore_memory_transaction_failures for most ARM boardsPeter Maydell27-0/+43
Set the MachineClass flag ignore_memory_transaction_failures for almost all ARM boards. This means they retain the legacy behaviour that accesses to unimplemented addresses will RAZ/WI rather than aborting, when a subsequent commit adds support for external aborts. The exceptions are: * virt -- we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables * mps2 -- this board was written to use unimplemented-device for all the ranges with devices we don't yet handle New boards should not set the flag, but instead be written like the mps2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org For the Xilinx boards: Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-09-07boards.h: Define new flag ignore_memory_transaction_failuresPeter Maydell3-1/+33
Define a new MachineClass field ignore_memory_transaction_failures. If this is flag is true then the CPU will ignore memory transaction failures which should cause the CPU to take an exception due to an access to an unassigned physical address; the transaction will instead return zero (for a read) or be ignored (for a write). This should be set only by legacy board models which rely on the old RAZ/WI behaviour for handling devices that QEMU does not yet model. New board models should instead use "unimplemented-device" for all memory ranges where the guest will attempt to probe for a device that QEMU doesn't implement and a stub device is required. We need this for ARM boards, where we're about to implement support for generating external aborts on memory transaction failures. Too many of our legacy board models rely on the RAZ/WI behaviour and we would break currently working guests when their "probe for device" code provoked an external abort rather than a RAZ. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1504626814-23124-2-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell6-1/+138
Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear. This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state. BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Move regime_is_secure() to target/arm/internals.hPeter Maydell2-26/+26
Move the regime_is_secure() utility function to internals.h; we are going to want to call it from translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell4-13/+30
Make the CFSR register banked if v8M security extensions are enabled. Not all the bits in this register are banked: the BFSR bits [15:8] are shared between S and NS, and we store them in the NS copy of the register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell4-6/+7
Make the MMFAR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell5-13/+42
Make the CCR register banked if v8M security extensions are enabled. This is slightly more complicated than the other "add banking" patches because there is one bit in the register which is not banked. We keep the live data in the NS copy of the register, and adjust it on register reads and writes. (Since we don't currently implement the behaviour that the bit controls, there is nowhere else that needs to care.) This patch includes the enforcement of the bits which are newly RES1 in ARMv8M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell4-8/+11
Make the MPU_CTRL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell5-16/+26
Make the MPU_RNR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell5-21/+40
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8MPeter Maydell4-10/+14
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make VTOR register banked for v8MPeter Maydell4-9/+11
Make the VTOR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org
2017-09-07nvic: Add NS alias SCS regionPeter Maydell2-1/+66
For v8M the range 0xe002e000..0xe002efff is an alias region which for secure accesses behaves like a NonSecure access to the main SCS region. (For nonsecure accesses including when the security extension is not implemented, it is RAZ/WI.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1503414539-28762-11-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CONTROL register banked for v8MPeter Maydell4-14/+17
Make the CONTROL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make FAULTMASK register banked for v8MPeter Maydell4-9/+39
Make the FAULTMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to be restricted). This patch includes the code to determine for v8M which copy of FAULTMASK should be updated on exception exit; further changes will be required to the exception exit code in general to support v8M, so this is just a small piece of that. The v8M ARM ARM introduces a notation where individual paragraphs are labelled with R (for rule) or I (for information) followed by a random group of subscript letters. In comments where we want to refer to a particular part of the manual we use this convention, which should be more stable across document revisions than using section or page numbers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-9-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make PRIMASK register banked for v8MPeter Maydell4-6/+11
Make the PRIMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to be restricted). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-8-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make BASEPRI register banked for v8MPeter Maydell4-8/+23
Make the BASEPRI register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to be restricted). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Add MMU indexes for secure v8MPeter Maydell2-3/+25
Now that MPU lookups can return different results for v8M when the CPU is in secure vs non-secure state, we need to have separate MMU indexes; add the secure counterparts to the existing three M profile MMU indexes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-6-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Register second AddressSpace for secure v8M CPUsPeter Maydell1-7/+6
If a v8M CPU supports the security extension then we need to give it two AddressSpaces, the same way we do already for an A profile core with EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Add state field, feature bit and migration for v8M secure statePeter Maydell4-1/+34
As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Implement new PMSAv8 behaviourPeter Maydell1-1/+110
Implement the behavioural side of the new PMSAv8 specification. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-3-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Implement ARMv8M's PMSAv8 registersPeter Maydell4-20/+180
As part of ARMv8M, we need to add support for the PMSAv8 MPU architecture. PMSAv8 differs from PMSAv7 both in register/data layout (for instance using base and limit registers rather than base and size) and also in behaviour (for example it does not have subregions); rather than trying to wedge it into the existing PMSAv7 code and data structures, we define separate ones. This commit adds the data structures which hold the state for a PMSAv8 MPU and the register interface to it. The implementation of the MPU behaviour will be added in a subsequent commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org
2017-09-07hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = falseThomas Huth2-1/+2
QEMU currently exits unexpectedly when the user accidentially tries to do something like this: $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic QEMU 2.9.93 monitor - type 'help' for more information (qemu) device_add allwinner-a10 Unsupported NIC model: smc91c111 Exiting just due to a "device_add" should not happen. Looking closer at the the realize and instance_init function of this device also reveals that it is using serial_hds and nd_table directly there, so this device is clearly not creatable by the user and should be marked accordingly. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 1503416789-32080-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07xilinx_axidma: Convert to DEFINE_PROP_LINKFam Zheng1-12/+4
Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170905131149.10669-7-famz@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07xilinx_axienet: Convert to DEFINE_PROP_LINKFam Zheng1-12/+4
Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170905131149.10669-6-famz@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07xlnx_zynqmp: Convert to DEFINE_PROP_LINKFam Zheng1-5/+2
Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170905131149.10669-5-famz@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07gicv3: Convert to DEFINE_PROP_LINKFam Zheng1-12/+7
Signed-off-by: Fam Zheng <famz@redhat.com> Message-id: 20170905131149.10669-4-famz@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07armv7m: Convert armv7m.memory to DEFINE_PROP_LINKFam Zheng1-6/+2
Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170905131149.10669-3-famz@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07armv7m: Convert bitband.source-memory to DEFINE_PROP_LINKFam Zheng1-6/+2
Signed-off-by: Fam Zheng <famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170905131149.10669-2-famz@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170906' into stagingPeter Maydell16-13622/+432
Queued tcg patches # gpg: Signature made Wed 06 Sep 2017 15:27:16 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170906: tcg/s390: Use slbgr for setcond le and leu tcg/s390: Use load-on-condition-2 facility tcg/s390: Use distinct-operands facility tcg/s390: Merge ori+xori facilities check to tcg_target_op_def tcg/s390: Merge add2i facilities check to tcg_target_op_def tcg/s390: Merge muli facilities check to tcg_target_op_def tcg/s390: Merge cmpi facilities check to tcg_target_op_def tcg/s390: Fully convert tcg_target_op_def disas/i386: Add disassembly of rorx disas/i386: Add disassembly of vex.0f38.f5 disas/i386: Fix disassembly of two-byte vex prefixes tcg: Implement implicit ordering semantics tcg: Add tcg target default memory ordering tcg: Remove support for ia64 as host Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell26-453/+1886
Block layer patches # gpg: Signature made Wed 06 Sep 2017 14:44:41 BST # gpg: using RSA key 0x7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: qcow2: move qcow2_store_persistent_dirty_bitmaps() before cache flushing qemu-iotests: add 184 for throttle filter driver block: add throttle block filter driver block: convert ThrottleGroup to object with QOM block: tidy ThrottleGroupMember initializations block: add aio_context field in ThrottleGroupMember block: move ThrottleGroup membership to ThrottleGroupMember block: document semantics of bdrv_co_preadv|pwritev qcow: Check failure of bdrv_getlength() and bdrv_truncate() qcow: Change signature of get_cluster_offset() block: add default implementations for bdrv_co_get_block_status() block: remove bdrv_truncate callback in blkdebug block: remove unused bdrv_media_changed block: pass bdrv_* methods to bs->file by default in block filters Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/juanquintela/tags/tests/20170906' into ↵Peter Maydell3-13/+7
staging tests/next for 20170906 # gpg: Signature made Wed 06 Sep 2017 12:42:29 BST # gpg: using RSA key 0xF487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" # gpg: aka "Juan Quintela <quintela@trasno.org>" # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/juanquintela/tags/tests/20170906: tests: Make vmgenid test compile tests: Use real size for iov tests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-06migration: dump str in migrate_set_state tracePeter Xu2-2/+3
Strings are more readable for debugging. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <1504081950-2528-5-git-send-email-peterx@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Fixed up merge with 977c73
2017-09-06nbd: Use new qio_channel_*_all() functionsEric Blake5-93/+18
Rather than open-coding our own read/write-all functions, we can make use of the recently-added qio code. It slightly changes the error message in one of the iotests. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20170905191114.5959-4-eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
2017-09-06io: Add new qio_channel_read{, v}_all_eof functionsEric Blake2-8/+93
Some callers want to distinguish between clean EOF (no bytes read) vs. a short read (at least one byte read, but EOF encountered before reaching the desired length), as it allows clients the ability to do a graceful shutdown when a server shuts down at defined safe points in the protocol, rather than treating all shutdown scenarios as an error due to EOF. However, we don't want to require all callers to have to check for early EOF. So add another wrapper function that can be used by the callers that care about the distinction. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20170905191114.5959-3-eblake@redhat.com> Acked-by: Daniel P. Berrange <berrange@redhat.com>
2017-09-06io: Yield rather than wait when already in coroutineEric Blake1-2/+10
The new qio_channel_{read,write}{,v}_all functions are documented as yielding until data is available. When used on a blocking channel, this yield is done via qio_channel_wait() which spawns a nested event loop under the hood (so it is that secondary loop which yields as needed); but if we are already in a coroutine (at which point QIO_CHANNEL_ERR_BLOCK is only possible if we are a non-blocking channel), we want to yield the current coroutine instead of spawning a nested event loop. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20170905191114.5959-2-eblake@redhat.com> Acked-by: Daniel P. Berrange <berrange@redhat.com> [commit message updated] Signed-off-by: Eric Blake <eblake@redhat.com>
2017-09-06target/arm: Perform per-insn cross-page check only for ThumbRichard Henderson1-25/+33
ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: Split out thumb_tr_translate_insnRichard Henderson1-41/+80
We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: Move ss check to init_disas_contextRichard Henderson1-5/+8
We can check for single-step just once. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06target/arm: [a64] Move page and ss checks to init_disas_contextRichard Henderson1-8/+9
Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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