riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-11	Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into s...	Peter Maydell	18	-258/+1210
2024-01-11	hw/intc/loongarch_extioi: Add vmstate post_load support	Bibo Mao	1	-44/+76
2024-01-11	hw/intc/loongarch_extioi: Add dynamic cpu number support	Bibo Mao	3	-40/+81
2024-01-11	hw/loongarch/virt: Set iocsr address space per-board rather than percpu	Bibo Mao	10	-104/+128
2024-01-11	hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops	Bibo Mao	1	-59/+77
2024-01-11	target/loongarch: Add loongarch kvm into meson build	Tianrui Zhao	3	-0/+4
2024-01-11	target/loongarch: Implement set vcpu intr for kvm	Tianrui Zhao	4	-1/+40
2024-01-11	target/loongarch: Restrict TCG-specific code	Tianrui Zhao	1	-9/+21
2024-01-11	target/loongarch: Implement kvm_arch_handle_exit	Tianrui Zhao	2	-1/+24
2024-01-11	target/loongarch: Implement kvm_arch_init_vcpu	Tianrui Zhao	3	-0/+27
2024-01-11	target/loongarch: Implement kvm_arch_init function	Tianrui Zhao	1	-0/+1
2024-01-11	target/loongarch: Implement kvm get/set registers	Tianrui Zhao	7	-3/+599
2024-01-11	target/loongarch: Supplement vcpu env initial when vcpu reset	Tianrui Zhao	2	-1/+3
2024-01-11	target/loongarch: Define some kvm_arch interfaces	Tianrui Zhao	1	-0/+131
2024-01-11	linux-headers: Synchronize linux headers from linux v6.7.0-rc8	Tianrui Zhao	1	-4/+6
2024-01-11	Merge tag 'pull-target-arm-20240111' of https://git.linaro.org/people/pmaydel...	Peter Maydell	39	-80/+1203
2024-01-11	Merge tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu into staging	Peter Maydell	5	-25/+67
2024-01-11	util: fix build with musl libc on ppc64le	Natanael Copa	1	-3/+3
2024-01-11	tcg/ppc: Use new registers for LQ destination	Richard Henderson	3	-7/+19
2024-01-11	tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates	Paolo Bonzini	1	-0/+11
2024-01-11	tcg/i386: convert add/sub of 128 to sub/add of -128	Paolo Bonzini	1	-15/+34
2024-01-10	Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qem...	Peter Maydell	68	-359/+2247
2024-01-10	Merge tag 'qemu-sparc-20240110' of https://github.com/mcayland/qemu into staging	Peter Maydell	2	-10/+55
2024-01-10	target/riscv: Ensure mideleg is set correctly on reset	Alistair Francis	1	-0/+8
2024-01-10	target/riscv: Don't adjust vscause for exceptions	Alistair Francis	1	-2/+2
2024-01-10	target/riscv: Assert that the CSR numbers will be correct	Alistair Francis	1	-1/+4
2024-01-10	target/riscv: pmp: Ignore writes when RW=01 and MML=0	Ivan Klokov	1	-1/+1
2024-01-10	roms/opensbi: Upgrade from v1.3.1 to v1.4	Bin Meng	3	-0/+0
2024-01-10	docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions	Bin Meng	1	-21/+12
2024-01-10	target/riscv/kvm: add RVV and Vector CSR regs	Daniel Henrique Barboza	1	-0/+74
2024-01-10	target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()	Daniel Henrique Barboza	1	-0/+29
2024-01-10	linux-headers: riscv: add ptrace.h	Daniel Henrique Barboza	2	-0/+135
2024-01-10	linux-headers: Update to Linux v6.7-rc5	Daniel Henrique Barboza	29	-27/+498
2024-01-10	target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1...	Yong-Xuan Wang	1	-14/+17
2024-01-10	target/riscv: add rva22s64 cpu	Daniel Henrique Barboza	2	-0/+9
2024-01-10	target/riscv: add RVA22S64 profile	Daniel Henrique Barboza	1	-0/+32
2024-01-10	target/riscv: add 'parent' in profile description	Daniel Henrique Barboza	3	-1/+15
2024-01-10	target/riscv: add satp_mode profile support	Daniel Henrique Barboza	3	-0/+42
2024-01-10	target/riscv/cpu.c: add riscv_cpu_is_32bit()	Daniel Henrique Barboza	2	-1/+7
2024-01-10	target/riscv/cpu.c: finalize satp_mode earlier	Daniel Henrique Barboza	1	-8/+8
2024-01-10	target/riscv: add priv ver restriction to profiles	Daniel Henrique Barboza	3	-0/+34
2024-01-10	target/riscv: implement svade	Daniel Henrique Barboza	3	-0/+7
2024-01-10	target/riscv: add 'rva22u64' CPU	Daniel Henrique Barboza	3	-0/+27
2024-01-10	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	Daniel Henrique Barboza	1	-0/+14
2024-01-10	target/riscv/tcg: validate profiles during finalize	Daniel Henrique Barboza	1	-0/+69
2024-01-10	target/riscv/tcg: honor user choice for G MISA bits	Daniel Henrique Barboza	1	-25/+48
2024-01-10	target/riscv/tcg: add hash table insert helpers	Daniel Henrique Barboza	1	-12/+16
2024-01-10	target/riscv/tcg: handle profile MISA bits	Daniel Henrique Barboza	1	-0/+21
2024-01-10	target/riscv/tcg: add riscv_cpu_write_misa_bit()	Daniel Henrique Barboza	1	-14/+18
2024-01-10	target/riscv/tcg: add MISA user options hash	Daniel Henrique Barboza	1	-1/+14