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2017-10-06Merge remote-tracking branch ↵Peter Maydell9-110/+898
'remotes/pmaydell/tags/pull-target-arm-20171006' into staging target-arm: * v8M: more preparatory work * nvic: reset properly rather than leaving the nvic in a weird state * xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false * sd: fix out-of-bounds check for multi block reads * arm: Fix SMC reporting to EL2 when QEMU provides PSCI # gpg: Signature made Fri 06 Oct 2017 16:58:15 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20171006: nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit target/arm: Factor out "get mmuidx for specified security state" target/arm: Fix calculation of secure mm_idx values target/arm: Implement security attribute lookups for memory accesses nvic: Implement Security Attribution Unit registers target/arm: Add v8M support to exception entry code target/arm: Add support for restoring v8M additional state context target/arm: Update excret sanity checks for v8M target/arm: Add new-in-v8M SFSR and SFAR target/arm: Don't warn about exception return with PC low bit set for v8M target/arm: Warn about restoring to unaligned stack target/arm: Check for xPSR mismatch usage faults earlier for v8M target/arm: Restore SPSEL to correct CONTROL register on exception return target/arm: Restore security state on exception return target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode target/arm: Don't switch to target stack early in v7M exception return nvic: Clear the vector arrays and prigroup on reset hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false hw/sd: fix out-of-bounds check for multi block reads arm: Fix SMC reporting to EL2 when QEMU provides PSCI Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-06nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bitPeter Maydell1-0/+1
When we added support for the new SHCSR bits in v8M in commit 437d59c17e9 the code to support writing to the new HARDFAULTPENDED bit was accidentally only added for non-secure writes; the secure banked version of the bit should also be writable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-21-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Factor out "get mmuidx for specified security state"Peter Maydell1-11/+21
For the SG instruction and secure function return we are going to want to do memory accesses using the MMU index of the CPU in secure state, even though the CPU is currently in non-secure state. Write arm_v7m_mmu_idx_for_secstate() to do this job, and use it in cpu_mmu_index(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-17-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Fix calculation of secure mm_idx valuesPeter Maydell1-5/+7
In cpu_mmu_index() we try to do this: if (env->v7m.secure) { mmu_idx += ARMMMUIdx_MSUser; } but it will give the wrong answer, because ARMMMUIdx_MSUser includes the 0x40 ARM_MMU_IDX_M field, and so does the mmu_idx we're adding to, and we'll end up with 0x8n rather than 0x4n. This error is then nullified by the call to arm_to_core_mmu_idx() which masks out the high part, but we're about to factor out the code that calculates the ARMMMUIdx values so it can be used without passing it through arm_to_core_mmu_idx(), so fix this bug first. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-16-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Implement security attribute lookups for memory accessesPeter Maydell2-2/+195
Implement the security attribute lookups for memory accesses in the get_phys_addr() functions, causing these to generate various kinds of SecureFault for bad accesses. The major subtlety in this code relates to handling of the case when the security attributes the SAU assigns to the address don't match the current security state of the CPU. In the ARM ARM pseudocode for validating instruction accesses, the security attributes of the address determine whether the Secure or NonSecure MPU state is used. At face value, handling this would require us to encode the relevant bits of state into mmu_idx for both S and NS at once, which would result in our needing 16 mmu indexes. Fortunately we don't actually need to do this because a mismatch between address attributes and CPU state means either: * some kind of fault (usually a SecureFault, but in theory perhaps a UserFault for unaligned access to Device memory) * execution of the SG instruction in NS state from a Secure & NonSecure code region The purpose of SG is simply to flip the CPU into Secure state, so we can handle it by emulating execution of that instruction directly in arm_v7m_cpu_do_interrupt(), which means we can treat all the mismatch cases as "throw an exception" and we don't need to encode the state of the other MPU bank into our mmu_idx values. This commit doesn't include the actual emulation of SG; it also doesn't include implementation of the IDAU, which is a per-board way to specify hard-coded memory attributes for addresses, which override the CPU-internal SAU if they specify a more secure setting than the SAU is programmed to. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-15-git-send-email-peter.maydell@linaro.org
2017-10-06nvic: Implement Security Attribution Unit registersPeter Maydell4-0/+167
Implement the register interface for the SAU: SAU_CTRL, SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the actual behaviour is implemented here; registers just read back as written. When the CPU definition for Cortex-M33 is eventually added, its initfn will set cpu->sau_sregion, in the same way that we currently set cpu->pmsav7_dregion for the M3 and M4. Number of SAU regions is typically a configurable CPU parameter, but this patch doesn't provide a QEMU CPU property for it. We can easily add one when we have a board that requires it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-14-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Add v8M support to exception entry codePeter Maydell1-20/+145
Add support for v8M and in particular the security extension to the exception entry code. This requires changes to: * calculation of the exception-return magic LR value * push the callee-saves registers in certain cases * clear registers when taking non-secure exceptions to avoid leaking information from the interrupted secure code * switch to the correct security state on entry * use the vector table for the security state we're targeting Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-13-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Add support for restoring v8M additional state contextPeter Maydell1-0/+30
For v8M, exceptions from Secure to Non-Secure state will save callee-saved registers to the exception frame as well as the caller-saved registers. Add support for unstacking these registers in exception exit when necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-12-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Update excret sanity checks for v8MPeter Maydell1-15/+58
In v8M, more bits are defined in the exception-return magic values; update the code that checks these so we accept the v8M values when the CPU permits them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-11-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Add new-in-v8M SFSR and SFARPeter Maydell3-0/+48
Add the new M profile Secure Fault Status Register and Secure Fault Address Register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-10-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Don't warn about exception return with PC low bit set for v8MPeter Maydell1-7/+15
In the v8M architecture, return from an exception to a PC which has bit 0 set is not UNPREDICTABLE; it is defined that bit 0 is discarded [R_HRJH]. Restrict our complaint about this to v7M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-9-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Warn about restoring to unaligned stackPeter Maydell1-0/+7
Attempting to do an exception return with an exception frame that is not 8-aligned is UNPREDICTABLE in v8M; warn about this. (It is not UNPREDICTABLE in v7M, and our implementation can handle the merely-4-aligned case fine, so we don't need to do anything except warn.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-8-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Check for xPSR mismatch usage faults earlier for v8MPeter Maydell1-3/+27
ARM v8M specifies that the INVPC usage fault for mismatched xPSR exception field and handler mode bit should be checked before updating the PSR and SP, so that the fault is taken with the existing stack frame rather than by pushing a new one. Perform this check in the right place for v8M. Since v7M specifies in its pseudocode that this usage fault check should happen later, we have to retain the original code for that check rather than being able to merge the two. (The distinction is architecturally visible but only in very obscure corner cases like attempting an invalid exception return with an exception frame in read only memory.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-7-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Restore SPSEL to correct CONTROL register on exception returnPeter Maydell1-13/+27
On exception return for v8M, the SPSEL bit in the EXC_RETURN magic value should be restored to the SPSEL bit in the CONTROL register banked specified by the EXC_RETURN.ES bit. Add write_v7m_control_spsel_for_secstate() which behaves like write_v7m_control_spsel() but allows the caller to specify which CONTROL bank to use, reimplement write_v7m_control_spsel() in terms of it, and use it in exception return. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-6-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Restore security state on exception returnPeter Maydell1-0/+2
Now that we can handle the CONTROL.SPSEL bit not necessarily being in sync with the current stack pointer, we can restore the correct security state on exception return. This happens before we start to read registers off the stack frame, but after we have taken possible usage faults for bad exception return magic values and updated CONTROL.SPSEL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-5-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler modePeter Maydell3-24/+51
In the v7M architecture, there is an invariant that if the CPU is in Handler mode then the CONTROL.SPSEL bit cannot be nonzero. This in turn means that the current stack pointer is always indicated by CONTROL.SPSEL, even though Handler mode always uses the Main stack pointer. In v8M, this invariant is removed, and CONTROL.SPSEL may now be nonzero in Handler mode (though Handler mode still always uses the Main stack pointer). In preparation for this change, change how we handle this bit: rename switch_v7m_sp() to the now more accurate write_v7m_control_spsel(), and make it check both the handler mode state and the SPSEL bit. Note that this implicitly changes the point at which we switch active SP on exception exit from before we pop the exception frame to after it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-4-git-send-email-peter.maydell@linaro.org
2017-10-06target/arm: Don't switch to target stack early in v7M exception returnPeter Maydell1-32/+98
Currently our M profile exception return code switches to the target stack pointer relatively early in the process, before it tries to pop the exception frame off the stack. This is awkward for v8M for two reasons: * in v8M the process vs main stack pointer is not selected purely by the value of CONTROL.SPSEL, so updating SPSEL and relying on that to switch to the right stack pointer won't work * the stack we should be reading the stack frame from and the stack we will eventually switch to might not be the same if the guest is doing strange things Change our exception return code to use a 'frame pointer' to read the exception frame rather than assuming that we can switch the live stack pointer this early. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-3-git-send-email-peter.maydell@linaro.org
2017-10-06nvic: Clear the vector arrays and prigroup on resetPeter Maydell1-0/+5
Reset for devices does not include an automatic clear of the device state (unlike CPU state, where most of the state structure is cleared to zero). Add some missing initialization of NVIC state that meant that the device was left in the wrong state if the guest did a warm reset. (In particular, since we were resetting the computed state like s->exception_prio but not all the state it was computed from like s->vectors[x].active, the NVIC wound up in an inconsistent state that could later trigger assertion failures.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1506092407-26985-2-git-send-email-peter.maydell@linaro.org
2017-10-06hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = falseThomas Huth1-0/+2
The device uses serial_hds in its realize function and thus can't be used twice. Apart from that, the comma in its name makes it quite hard to use for the user anyway, since a comma is normally used to separate the device name from its properties when using the "-device" parameter or the "device_add" HMP command. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1506441116-16627-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-06hw/sd: fix out-of-bounds check for multi block readsMichael Olbrich1-6/+6
The current code checks if the next block exceeds the size of the card. This generates an error while reading the last block of the card. Do the out-of-bounds check when starting to read a new block to fix this. This issue became visible with increased error checking in Linux 4.13. Cc: qemu-stable@nongnu.org Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170916091611.10241-1-m.olbrich@pengutronix.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-06arm: Fix SMC reporting to EL2 when QEMU provides PSCIJan Kiszka2-11/+25
This properly forwards SMC events to EL2 when PSCI is provided by QEMU itself and, thus, ARM_FEATURE_EL3 is off. Found and tested with the Jailhouse hypervisor. Solution based on suggestions by Peter Maydell. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-id: 4f243068-aaea-776f-d18f-f9e05e7be9cd@siemens.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-06Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20171006' into stagingPeter Maydell31-295/+730
s390x changes: - support for IDA (indirect addressing in ccws) via ccw data stream - support for extended TOD-Clock (z14 feature) - various fixes and improvements all over the place # gpg: Signature made Fri 06 Oct 2017 10:52:22 BST # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20171006: (33 commits) hw/s390x: Mark the "sclpquiesce" device with user_creatable = false s390x/tcg: initialize machine check queue s390x/sclp: mark sclp-cpu-hotplug as non-usercreatable s390x/sclp: Mark the sclp device with user_creatable = false s390/kvm: make TOD setting failures fatal for migration s390/kvm: Support for get/set of extended TOD-Clock for guest s390x/css: fix css migration compat handling s390x: sort some devices into categories s390x/tcg: make STFL store into the lowcore s390x: introduce and use S390_MAX_CPUS target/s390x: get rid of next_core_id s390x/cpumodel: fix max STFL(E) bit number s390x: raise CPU hotplug irq after really hotplugged MAINTAINERS: use KVM s390x maintainers for kvm-stubs.c and kvm_s390x.h s390x/3270: handle writes of arbitrary length s390x/3270: IDA support for 3270 via CcwDataStream Revert "s390x/ccw: create s390 phb conditionally" s390x/tcg: make idte/ipte use the new _real mmu s390x/tcg: make testblock use the new _real mmu s390x/tcg: make stora(g) use the new _real mmu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-06hw/s390x: Mark the "sclpquiesce" device with user_creatable = falseThomas Huth1-1/+6
The "sclpquiesce" device is just an internal device that should not be created by the user directly. Though it currently does not seem to cause any obvious trouble when the user instantiates an additional device, let's better mark it with user_creatable = false to avoid unexpected behavior, e.g. because the quiesce notifier gets registered multiple times. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1507193105-15627-1-git-send-email-thuth@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: initialize machine check queueCornelia Huck1-0/+2
Just as for external interrupts and I/O interrupts, we need to initialize mchk_index during cpu reset. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/sclp: mark sclp-cpu-hotplug as non-usercreatableCornelia Huck1-0/+6
A TYPE_SCLP_CPU_HOTPLUG device for handling cpu hotplug events is already created by the sclp event facility. Adding a second TYPE_SCLP_CPU_HOTPLUG device via -device sclp-cpu-hotplug creates an ambiguity in raise_irq_cpu_hotplug(), leading to a crash once a cpu is hotplugged. To fix this, disallow creating a sclp-cpu-hotplug device manually. Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/sclp: Mark the sclp device with user_creatable = falseThomas Huth1-0/+5
The "sclp" device is just an internal device that can not be instantiated by the users. If they try to use it, they only get a simple error message: $ qemu-system-s390x -nographic -device sclp qemu-system-s390x: Option '-device s390-sclp-event-facility' cannot be handled by this machine Since sclp_init() tries to create a TYPE_SCLP_EVENT_FACILITY which is a non-pluggable sysbus device, there is really no way that the "sclp" device can be used by the user, so let's set the user_creatable = false accordingly. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1507125199-22562-1-git-send-email-thuth@redhat.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Reviewed-by: Farhan Ali <alifm@linux.vnet.ibm.com> Acked-by: Halil Pasic <pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390/kvm: make TOD setting failures fatal for migrationCollin L. Walling1-5/+2
If we fail to set a proper TOD clock on the target system, this can already result in some problematic cases. We print several warn messages on source and target in that case. If kvm fails to set a nonzero epoch index, then we must ultimately fail the migration as this will result in a giant time leap backwards. This patch lets the migration fail if we can not set the guest time on the target. On failure the guest will resume normally on the original host machine. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Reviewed-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [split failure change from epoch index change, minor fixups] Message-Id: <20171004105751.24655-3-borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390/kvm: Support for get/set of extended TOD-Clock for guestCollin L. Walling4-8/+63
Provides an interface for getting and setting the guest's extended TOD-Clock via a single ioctl to kvm. If the ioctl fails because it is not support by kvm, then we fall back to the old style of retrieving the clock via two ioctls. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Reviewed-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [split failure change from epoch index change] Message-Id: <20171004105751.24655-2-borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> [some cosmetic fixes]
2017-10-06s390x/css: fix css migration compat handlingHalil Pasic1-3/+3
Commit e996583eb3 ("s390x/css: activate ChannelSubSys migration", 2017-07-11) was supposed to enable css migration for virtio-ccw machines starting 2.10, but it ended up effectively enabling it only for 2.10 as the registration of the appropriate VMStateDescription happens in ccw_machine_2_10_instance_options which does not get called for machines more recent than 2_10. Let us move the corresponding chunk of code (which conditionally enables the migration based on the value of the corresponding class property) to ccw_init, which is called for each virtio-ccw machine instance. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reported-by: Thomas Huth <thuth@redhat.com> Message-Id: <20171004110109.16525-1-pasic@linux.vnet.ibm.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x: sort some devices into categoriesCornelia Huck3-0/+3
Add missing categorizations for some s390x devices: - zpci device -> misc - 3270 -> display - vfio-ccw -> misc Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: make STFL store into the lowcoreDavid Hildenbrand2-2/+7
Using virtual memory access is wrong and will soon include low-address protection checks, which is to be bypassed for STFL. STFL is a privileged instruction and using LowCore requires !CONFIG_USER_ONLY, so add the ifdef and move the declaration to the right place. This was originally part of a bigger STFL(E) refactoring. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170927170027.8539-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x: introduce and use S390_MAX_CPUSDavid Hildenbrand2-1/+3
Will be handy in the future. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928134609.16985-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06target/s390x: get rid of next_core_idDavid Hildenbrand4-9/+11
core_id is not needed by linux-user, as the core_id a.k.a. CPU address is only accessible from kernel space. Therefore, drop next_core_id and make cpu_index get autoassigned again for linux-user. While at it, shield core_id and cpuid completely from linux-user. cpuid can also only be queried from kernel space. Suggested-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928134609.16985-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/cpumodel: fix max STFL(E) bit numberDavid Hildenbrand1-1/+1
Not that it would matter in the near future, but it is actually 2048 bytes, therefore 16384 possible bits. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928134609.16985-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x: raise CPU hotplug irq after really hotpluggedDavid Hildenbrand2-8/+4
Let's move it into the machine, so we trigger the IRQ after setting ms->possible_cpus (which SCLP uses to construct the list of online CPUs). This also fixes a problem reported by Thomas Huth, whereby qemu can be crashed using the none machine qemu-s390x-softmmu -M none -monitor stdio -> device_add qemu-s390-cpu Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928134609.16985-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06MAINTAINERS: use KVM s390x maintainers for kvm-stubs.c and kvm_s390x.hDavid Hildenbrand1-0/+2
Forgot it when factoring code out into these files. This is 100% s390x KVM material. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928134609.16985-2-david@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/3270: handle writes of arbitrary lengthHalil Pasic1-12/+18
The problem is, that the current implementation places unrealistic and arbitrary constraints on the length of writes to the device (that is the outbound requests), by asserting ccw.count being such that that even the worst case escaped payload will fit an more or less arbitrary sized buffer. Actually on protocol level there is nothing to justify such a limitation. Another strange thing is the return value which more or less reflects the size (written) after escaping instead of before escaping. This is strange, because this return value is used to calculate SCSW.count. Let us teach 3270 how to deal with arbitrary long writes. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reported-by: Jason J . Herne <jjherne@linux.vnet.ibm.com> Tested-by: Jason J . Herne <jjherne@linux.vnet.ibm.com> Message-Id: <20170920172314.102710-3-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/3270: IDA support for 3270 via CcwDataStreamHalil Pasic3-12/+15
Let us convert the 3270 code so it uses the recently introduced CcwDataStream abstraction instead of blindly assuming direct data access. This patch does not change behavior beyond introducing IDA support: for direct data access CCWs everything stays as-is. (If there are bugs, they are also preserved). Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Message-Id: <20170920172314.102710-2-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06Revert "s390x/ccw: create s390 phb conditionally"Christian Borntraeger1-7/+9
This reverts commit d32bd032d8fde41281aae34c16a4aa97e9acfeac. Turns out that old QEMUs always created a pci host bridge and for many CPU models the migration from old QEMUs to new QEMUs will fail with qemu-system-s390x: Unknown savevm section or instance 'PCIBUS' 0 qemu-system-s390x: load of migration failed: Invalid argument As a quick fix we will revert the commit and always create the pci host bridge. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [fixed revert to keep the comment fixup, added a comment in the code] Cc: Cornelia Huck <cohuck@redhat.com> Cc: David Hildenbrand <david@redhat.com> Message-Id: <20170928131831.81393-1-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: make idte/ipte use the new _real mmuDavid Hildenbrand1-4/+5
We don't wrap addresses in the mmu for the _real case, therefore the behavior should be unchanged. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170926183318.12995-7-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: make testblock use the new _real mmuDavid Hildenbrand1-10/+2
Low address protection checks will be moved into the mmu later. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170926183318.12995-6-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: make stora(g) use the new _real mmuDavid Hildenbrand2-8/+2
As we properly handle the return address now, we can drop potential_page_fault(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170926183318.12995-5-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: make lura(g) use the new _real mmu.David Hildenbrand2-8/+2
Looks like, lurag was not loading 64bit but only 32bit. As we properly handle the return address now, we can drop potential_page_fault(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170926183318.12995-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: add MMU for real addressesDavid Hildenbrand4-10/+40
This makes it easy to access real addresses (prefix) and in addition checks for valid memory addresses, which is missing when using e.g. stl_phys(). We can later reuse it to implement low address protection checks (then we might even decide to introduce yet another MMU for absolute addresses, just for handling storage keys and low address protection). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170926183318.12995-3-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/tcg: fix checking for invalid memory checkDavid Hildenbrand1-1/+3
It should have been a >=, but let's directly perform a proper access check to also be able to deal with hotplugged memory later. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170926183318.12995-2-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/css: support ccw IDAHalil Pasic1-1/+113
Let's add indirect data addressing support for our virtual channel subsystem. This implementation does not bother with any kind of prefetching. We simply step through the IDAL on demand. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-6-pasic@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06390x/css: introduce maximum data address checkingHalil Pasic2-0/+11
The architecture mandates the addresses to be accessed on the first indirection level (that is, the data addresses without IDA, and the (M)IDAW addresses with (M)IDA) to be checked against an CCW format dependent limit maximum address. If a violation is detected, the storage access is not to be performed and a channel program check needs to be generated. As of today, we fail to do this check. Let us stick even closer to the architecture specification. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-5-pasic@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06virtio-ccw: use ccw data streamHalil Pasic1-109/+46
Replace direct access which implicitly assumes no IDA or MIDA with the new ccw data stream interface which should cope with these transparently in the future. Note that checking the return code for ccw_dstream_* will be done in a follow-on patch. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-4-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/css: use ccw data streamHalil Pasic1-4/+5
Replace direct access which implicitly assumes no IDA or MIDA with the new ccw data stream interface which should cope with these transparently in the future. Note that checking the return code for ccw_dstream_* will be done in a follow-on patch. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-3-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-06s390x/css: introduce css data streamHalil Pasic2-0/+122
This is a preparation for introducing handling for indirect data addressing and modified indirect data addressing (CCW). Here we introduce an interface which should make the addressing scheme transparent for the client code. Here we implement only the basic scheme (no IDA or MIDA). Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Message-Id: <20170921180841.24490-2-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
generated by cgit v1.1 at 2025-01-23 12:48:39 +0000