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2021-01-07tcg/sparc: Use tcg_tbrel_diffRichard Henderson1-8/+7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/ppc: Support split-wx code generationRichard Henderson2-24/+31
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TBRichard Henderson1-3/+2
The maximum TB code gen size is UINT16_MAX, which the current code does not support. Use our utility function to optimally add an arbitrary constant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/ppc: Use tcg_tbrel_diffRichard Henderson1-3/+3
Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Introduce tcg_tbrel_diffRichard Henderson1-0/+13
Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/tci: Push const down through bytecode readingRichard Henderson1-26/+34
Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07disas: Push const down through host disassemblyRichard Henderson3-6/+4
Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/aarch64: Support split-wx code generationRichard Henderson2-26/+33
Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/aarch64: Use B not BL for tcg_out_goto_longRichard Henderson1-1/+1
A typo generated a branch-and-link insn instead of plain branch. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/i386: Support split-wx code generationRichard Henderson2-10/+12
Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Return the TB pointer from the rx region from exit_tbRichard Henderson2-15/+33
This produces a small pc-relative displacement within the generated code to the TB structure that preceeds it. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07accel/tcg: Support split-wx for darwin/iOS with vm_remapRichard Henderson1-0/+67
Cribbed from code posted by Joelle van Dyne <j@getutm.app>, and rearranged to a cleaner structure. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07accel/tcg: Support split-wx for linux with memfdRichard Henderson1-8/+76
We cannot use a real temp file, because we would need to find a filesystem that does not have noexec enabled. However, a memfd is not associated with any filesystem. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Add --accel tcg,split-wx propertyRichard Henderson15-12/+72
Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Use Error with alloc_code_gen_bufferRichard Henderson1-26/+34
Report better error messages than just "could not allocate". Let alloc_code_gen_buffer set ctx->code_gen_buffer_size and ctx->code_gen_buffer, and simply return bool. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson12-12/+23
There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Make DisasContextBase.tb constRichard Henderson6-8/+8
There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson14-42/+44
Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust tcg_register_jit for constRichard Henderson10-14/+14
We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust tcg_out_label for constRichard Henderson2-8/+8
Simplify the arguments to always use s->code_ptr instead of take it as an argument. That makes it easy to ensure that the value_ptr is always the rx version. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust tcg_out_call for constRichard Henderson10-19/+19
We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Adjust TCGLabel for constRichard Henderson7-9/+10
Change TCGLabel.u.value_ptr to const, and initialize it with tcg_splitwx_to_rx. Propagate const through tcg/host/ only as far as needed to avoid errors from the value_ptr change. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Introduce tcg_splitwx_to_{rx,rw}Richard Henderson13-40/+105
Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour. Begin using the functions in tcg common code only. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Add in_code_gen_bufferRichard Henderson2-18/+19
Create a function to determine if a pointer is within the buffer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson11-15/+16
This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Move tcg prologue pointer out of TCGContextRichard Henderson3-8/+14
This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Use the correct function pointer type, and name the variable tcg_qemu_tb_exec, which means that we are able to remove the macro that does the casting. Replace HAVE_TCG_QEMU_TB_EXEC with CONFIG_TCG_INTERPRETER, as this is somewhat clearer in intent. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07util: Specialize flush_idcache_range for aarch64Richard Henderson1-0/+69
For darwin, the CTR_EL0 register is not accessible, but there are system routines that we can use. For other hosts, copy the single pointer implementation from libgcc and modify it to support the double pointer interface we require. This halves the number of cache operations required when split-rwx is enabled. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07util: Enhance flush_icache_range with separate data pointerRichard Henderson9-30/+51
We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Do not flush icache for interpreterRichard Henderson1-0/+4
This is currently a no-op within tci/tcg-target.h, but is about to be moved to a more generic location. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07util/oslib: Assert qemu_try_memalign() alignment is a power of 2Philippe Mathieu-Daudé2-0/+3
qemu_try_memalign() expects a power of 2 alignment: - posix_memalign(3): The address of the allocated memory will be a multiple of alignment, which must be a power of two and a multiple of sizeof(void *). - _aligned_malloc() The alignment value, which must be an integer power of 2. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201021173803.2619054-3-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07util/oslib-win32: Use _aligned_malloc for qemu_try_memalignRichard Henderson1-7/+4
We do not need or want to be allocating page sized quanta. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20201018164836.1149452-1-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson15-12/+49
Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson2-75/+47
Always true when movbe is available, otherwise leave this to generic code. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07linux-user: Conditionalize TUNSETVNETLERichard Henderson1-0/+2
This fixes the build for older ppc64 kernel headers. Fixes: 6addf06a3c4 Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-06Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' ↵Peter Maydell4-6/+13
into staging Testing updates (back to green) - include ccache in Debian 10 docker image - iotests: drop 312 from auto group - bound reading of s390x framebuffer file - cirrus: drop non-x86 tests so we complete # gpg: Signature made Wed 06 Jan 2021 17:31:14 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-060121-4: cirrus: don't run full qtest on macOS tests/acceptance: bound the size of readline in s390_ccw_virtio tests/iotests: drop test 312 from auto group tests/docker: Include 'ccache' in Debian base image Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-06cirrus: don't run full qtest on macOSDaniel P. Berrangé1-4/+10
The Cirrus CI macOS build hosts have exhibited a serious performance degradation in recent months. For example the "qom-test" qtest takes over an hour for only the qemu-system-aarch64 binary. This is as much 20-40 times slower than other environments. The other qtests all show similar performance degradation, as do many of the unit tests. This does not appear related to QEMU code changes, since older git commits which were known to fully complete in less than 1 hour on Cirrus CI now also show similar bad performance. Either Cirrus CI performance has degraded, or an change in its environment has exposed a latent bug widely affecting all of QEMU. Debugging the qom-test showed no easily identified large bottleneck - every step of the test execution was simply slower. macOS builds/tests run outside Cirrus CI show normal performance. With an inability to identify any obvious problem, the only viable way to get a reliably completing Cirrus CI macOS job is to cut out almost all of the qtests. We choose to run the x86_64 target only, since that has very few machine types and thus is least badly impacted in the qom-test execution. With this change, the macOS jobs complete in approx 35 minutes. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210106114159.981538-1-berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-01-06tests/acceptance: bound the size of readline in s390_ccw_virtioAlex Bennée1-1/+1
The read binary data as text via a PPM export of the frame buffer seems a bit sketchy and it did blow up in the real world when the assertion failed: https://gitlab.com/qemu-project/qemu/-/jobs/943183183 However short of cleaning up the test to be more binary focused at least limit the attempt to dump the whole file as hexified zeros in the logs. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210105124405.15424-1-alex.bennee@linaro.org>
2021-01-06tests/iotests: drop test 312 from auto groupAlex Bennée1-1/+1
The "auto" documentation states: That means they should run with every QEMU binary (also non-x86) which is not the case as the check-system-fedora build which only includes a rag tag group of rare and deprecated targets doesn't support the virtio device required. Fixes: ef9bba1484b ("quorum: Implement bdrv_co_block_status()") Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210105100402.12350-1-alex.bennee@linaro.org>
2021-01-06tests/docker: Include 'ccache' in Debian base imagePhilippe Mathieu-Daudé1-0/+1
Include the 'ccache' package to speed up compilation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201213211601.253530-1-f4bug@amsat.org> Fixes: d6db2a1cdf ("docker: add debian-buster-arm64-cross") Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-01-06Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell67-874/+1013
staging From Alex's pull request: * improve cross-build KVM coverage * new --without-default-features configure flag * add __repr__ for ConsoleSocket for debugging * build tcg tests with -Werror * test 32 bit builds with fedora * remove last traces of debian9 * hotfix for centos8 powertools repo * Move lots of feature detection code to meson (Alex, myself) * CFI and LTO support (Daniele) * test-char dangling pointer (Eduardo) * Build system and win32 fixes (Marc-André) * Initialization fixes (myself) * TCG include cleanup (Richard, myself) * x86 'int N' fix (Peter) # gpg: Signature made Wed 06 Jan 2021 09:21:25 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (52 commits) win32: drop fd registration to the main-loop on setting non-block configure: move tests/qemu-iotests/common.env generation to meson meson.build: convert --with-default-devices to meson libattr: convert to meson cap_ng: convert to meson virtfs: convert to meson seccomp: convert to meson zstd: convert to meson lzfse: convert to meson snappy: convert to meson lzo: convert to meson rbd: convert to meson libnfs: convert to meson libiscsi: convert to meson bzip2: convert to meson glusterfs: convert to meson curl: convert to meson curl: remove compatibility code, require 7.29.0 brlapi: convert to meson configure: remove CONFIG_FILEVERSION and CONFIG_PRODUCTVERSION ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # trace/meson.build
2021-01-06Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210106' ↵Peter Maydell6-22/+37
into staging qemu-sparc queue # gpg: Signature made Wed 06 Jan 2021 11:43:02 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20210106: sun4m: don't connect two qemu_irqs directly to the same input include/hw/sparc/grlib.h: Remove unused set_pil_in_fn typedef hw/sparc: Make grlib-irqmp device handle its own inbound IRQ lines hw/timer/slavio_timer: Allow 64-bit accesses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-06sun4m: don't connect two qemu_irqs directly to the same inputMark Cave-Ayland2-5/+20
The sun4m board code connects both of the IRQ outputs of each ESCC to the same slavio input qemu_irq. Connecting two qemu_irqs outputs directly to the same input is not valid as it produces subtly wrong behaviour (for instance if both the IRQ lines are high, and then one goes low, the PIC input will see this as a high-to-low transition even though the second IRQ line should still be holding it high). This kind of wiring needs an explicitly created OR gate; add one. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20201219111934.5540-1-mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-06include/hw/sparc/grlib.h: Remove unused set_pil_in_fn typedefPeter Maydell1-2/+0
The grlib.h header defines a set_pil_in_fn typedef which is never used; remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20201212144134.29594-3-peter.maydell@linaro.org> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-06hw/sparc: Make grlib-irqmp device handle its own inbound IRQ linesPeter Maydell3-15/+13
Currently the GRLIB_IRQMP device is used in one place (the leon3 board), but instead of the device providing inbound gpio lines for the board to wire up, the board code itself calls qemu_allocate_irqs() with the handler function being a set_irq function defined in the code for the device. Refactor this into the standard setup of a device having input gpio lines. This fixes a trivial Coverity memory leak report (the leon3 board code leaks the IRQ array returned from qemu_allocate_irqs()). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20201212144134.29594-2-peter.maydell@linaro.org> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-06hw/timer/slavio_timer: Allow 64-bit accessesPhilippe Mathieu-Daudé1-0/+4
Per the "NCR89C105 Chip Specification" referenced in the header: Chip-level Address Map ------------------------------------------------------------------ | 1D0 0000 -> | Counter/Timers | W,D | | 1DF FFFF | | | ... The address map indicated the allowed accesses at each address. [...] W indicates a word access, and D indicates a double-word access. The SLAVIO timer controller is implemented expecting 32-bit accesses. Commit a3d12d073e1 restricted the memory accesses to 32-bit, while the device allows 64-bit accesses. This was not an issue until commit 5d971f9e67 which reverted ("memory: accept mismatching sizes in memory_region_access_valid"). Fix by renaming .valid MemoryRegionOps as .impl, and add the valid access range (W -> 4, D -> 8). Since commit 21786c7e598 ("memory: Log invalid memory accesses") this class of bug can be quickly debugged displaying 'guest_errors' accesses, as: $ qemu-system-sparc -M SS-20 -m 256 -bios ss20_v2.25_rom -serial stdio -d guest_errors Power-ON Reset Invalid access at addr 0x0, size 8, region 'timer-1', reason: invalid size (min:4 max:4) $ qemu-system-sparc -M SS-20 -m 256 -bios ss20_v2.25_rom -monitor stdio -S (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system ... 0000000ff1300000-0000000ff130000f (prio 0, i/o): timer-1 ^^^^^^^^^ ^^^^^^^ \ memory region base address and name / (qemu) info qtree bus: main-system-bus dev: slavio_timer, id "" <-- device type name gpio-out "sysbus-irq" 17 num_cpus = 1 (0x1) mmio 0000000ff1310000/0000000000000014 mmio 0000000ff1300000/0000000000000010 <--- base address mmio 0000000ff1301000/0000000000000010 mmio 0000000ff1302000/0000000000000010 ... Reported-by: Yap KV <yapkv@yahoo.com> Buglink: https://bugs.launchpad.net/bugs/1906905 Fixes: a3d12d073e1 ("slavio_timer: convert to memory API") CC: qemu-stable@nongnu.org Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201205150903.3062711-1-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-06Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210106' ↵Peter Maydell22-383/+616
into staging ppc patch queue 2021-01-06 First pull request for 2021, which has a bunch of things accumulated over the holidays. Includes: * A number of cleanups to sam460ex and ppc440 code from BALATON Zoltan * Several fixes for builds with --without-default-devices from Greg Kurz * Fixes for some DRC reset problems from Greg Kurz * QOM conversion of the PPC 4xx UIC devices from Peter Maydell * Some other assorted fixes and cleanups # gpg: Signature made Wed 06 Jan 2021 03:33:19 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.0-20210106: (22 commits) ppc440_pcix: Fix up pci config access ppc440_pcix: Fix register write trace event ppc440_pcix: Improve comment for IRQ mapping sam460ex: Remove FDT_PPC dependency from KConfig ppc4xx: Move common dependency on serial to common option pnv: Fix reverse dependency on PCI express root ports ppc: Simplify reverse dependencies of POWERNV and PSERIES on XICS and XIVE ppc: Fix build with --without-default-devices spapr: Add drc_ prefix to the DRC realize and unrealize functions spapr: Use spapr_drc_reset_all() at machine reset spapr: Introduce spapr_drc_reset_all() spapr: Fix reset of transient DR connectors spapr: Call spapr_drc_reset() for all DRCs at CAS spapr: Fix buffer overflow in spapr_numa_associativity_init() spapr: Allow memory unplug to always succeed spapr: Fix DR properties of the root node spapr/xive: Make spapr_xive_pic_print_info() static spapr: DRC lookup cannot fail hw/ppc/ppc440_bamboo: Drop use of ppcuic_init() hw/ppc/virtex_ml507: Drop use of ppcuic_init() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-06win32: drop fd registration to the main-loop on setting non-blockMarc-André Lureau1-1/+0
Low-level fd users from QEMU use aio_set_fd_handler(), which handles event registration with the main loop; qemu_fd_register() is only needed together with the main loop's poll notifiers, of which SLIRP is the only user. This removes a dependency from oslib-win32.c to main-loop.c. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20201218135712.674094-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-06configure: move tests/qemu-iotests/common.env generation to mesonPaolo Bonzini3-7/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-06meson.build: convert --with-default-devices to mesonPaolo Bonzini3-11/+9
Pass the boolean option directly instead of writing CONFIG_MINIKCONF_MODE to config-host.mak. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-06libattr: convert to mesonPaolo Bonzini3-44/+41
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>