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2014-01-31target-arm: Add set_neon_rmode helperWill Newton2-0/+18
This helper sets the rounding mode in the standard_fp_status word to allow NEON instructions to modify the rounding mode whilst using the standard FPSCR values for everything else. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add support for AArch32 SIMD VRINTXWill Newton1-1/+10
Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add support for AArch32 FP VRINTXWill Newton1-0/+11
Add support for the AArch32 floating-point VRINTX instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add support for AArch32 FP VRINTZWill Newton1-0/+16
Add support for the AArch32 floating-point VRINTZ instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add support for AArch32 FP VRINTRWill Newton1-0/+11
Add support for the AArch32 floating-point VRINTR instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTMWill Newton1-0/+54
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Move arm_rmode_to_sf to a shared location.Will Newton3-28/+30
This function will be needed for AArch32 ARMv8 support, so move it to helper.c where it can be used by both targets. Also moves the code out of line, but as it is quite a large function I don't believe this should be a significant performance impact. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31display: avoid multi-statement macroPaolo Bonzini4-29/+59
For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xx Coverity noticed that it is used inside an "if" statement. Fix it because it's the file with the highest number of defects in the whole QEMU tree! Use "do...while (0)", or just remove the semicolon if there's a single statement in the macro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31ZYNQ: Implement board MIDR control for ZynqAlistair Francis1-0/+7
This patch uses the fact that the midr variable is now a property This patch sets the midr variable to the boards custom midr Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31ARM: Convert MIDR to a propertyAlistair Francis1-0/+1
Convert the MIDR register to a property. This allows boards to later set a custom MIDR value. This has been done in such a way to maintain compatibility with all existing CPUs and boards Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 878613f2f12d4162f12629522fd99de8df904856.1390176489.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31hw/arm/boot: Don't set up ATAGS for autogenerated dtb bootingPeter Maydell1-2/+7
The code which decides whether to set up the ATAGS data structure on reset was using the wrong conditional, which meant we were creating an ATAGS structure when doing a device-tree boot if the dtb was autogenerated by the board. This is harmless, but unnecessary, so bring it in to line with user-provided-dtb boots. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1388326833-656-1-git-send-email-peter.maydell@linaro.org
2014-01-31target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell1-1/+42
Add support for the SIMD scalar copy instruction group (C3.6.7), which consists of the single instruction DUP (element, scalar). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD modified immediate groupAlex Bennée1-1/+119
This patch adds support for the AdvSIMD modified immediate group (C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic). Signed-off-by: Alexander Graf <agraf@suse.de> [AJB: new decode struct, minor bug fixes, optimisation] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD copy operationsAlex Bennée1-1/+209
This adds support for the all the AdvSIMD vector copy operations (ARM ARM 3.6.5). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD across-lanes instructionsMichael Matz1-1/+176
Add support for the SIMD "across lanes" instruction group (C3.6.4). Signed-off-by: Michael Matz <matz@suse.de> [PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD ZIP/UZP/TRNMichael Matz1-1/+75
Add support for the SIMD ZIP/UZIP/TRN instruction group (C3.6.3). Signed-off-by: Michael Matz <matz@suse.de> [PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD TBL/TBLXMichael Matz3-1/+86
Add support for the SIMD TBL/TBLX instructions (group C3.6.2). Signed-off-by: Michael Matz <matz@suse.de> [PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD EXTPeter Maydell1-1/+78
Add support for the SIMD EXT instruction (the only one in its group, C3.6.1). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add decode skeleton for SIMD data processing insnsAlex Bennée1-1/+305
Add decode skeleton and function placeholders for all the SIMD data processing instructions. Due to the complexity of this part of the table the normal extract and switch approach gets very messy very quickly, so we use a simple data-driven pattern-and-mask approach. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD ld/st singlePeter Maydell1-2/+142
Implement the SIMD ld/st single structure instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD ld/st multipleAlex Bennée1-2/+248
This adds support support for the SIMD load/store multiple category of instructions. This also brings in a couple of helper functions for manipulating sections of the SIMD registers: * do_vec_get - fetch value from a slice of a vector register * do_vec_set - set a slice of a vector register which use vec_reg_offset for consistent processing of offsets in an endian aware manner. There are also additional helpers: * do_vec_ld - load value into SIMD * do_vec_st - store value from SIMD which load or store a slice of a vector register to memory. These don't zero extend like the fp variants. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into stagingPeter Maydell3-13/+29
Tracing pull request # gpg: Signature made Mon 27 Jan 2014 14:51:09 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * stefanha/tags/tracing-pull-request: trace: fix simple trace "disable" keyword trace: add glib 2.32+ static GMutex support trace: [simple] Do not include "trace/simple.h" in generated tracer headers tracing: start trace processing thread in final child process Message-id: 1390834386-23139-1-git-send-email-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31Merge remote-tracking branch 'mst/tags/for_anthony' into stagingPeter Maydell49-338/+1963
acpi,pci,pc,virtio fixes and enhancements This includes new unit-tests for acpi by Marcel, hotplug for pci bridges by myself (piix only so far) and cpu hotplug for q35. And a bunch of fixes all over the place as usual. I included the patch to fix memory alignment for q35 as well - even though it limits 32 bit guests to 3G (they previously could address more memory with PAE). To remove the limit, this will have to be fixed in seabios. I also added self as virtio co-maintainer so I don't need to troll the list for patches to review. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 26 Jan 2014 11:12:09 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * mst/tags/for_anthony: (35 commits) MAINTAINERS: add self as virtio co-maintainer q35: document gigabyte_align q35: gigabyte alignment for ram acpi: Fix PCI hole handling on build_srat() pc: Save size of RAM below 4GB hw/pci: fix error flow in pci multifunction init acpi-test: update expected AML since recent changes pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated pc: ACPI: unify source of CPU hotplug IO base/len pc: ACPI: expose PRST IO range via _CRS pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources pc: set PRST base in DSDT depending on chipset acpi: ich9: add CPU hotplug handling to Q35 machine acpi: factor out common cpu hotplug code for PIIX4/Q35 acpi-build: enable hotplug for PCI bridges piix4: add acpi pci hotplug support pcihp: generalization of piix4 acpi pci: add pci_for_each_bus_depth_first pc: make: fix dependencies: rebuild when included file is changed ... Message-id: 1390735289-15563-1-git-send-email-mst@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31Merge remote-tracking branch 'sstabellini/xen-170114' into stagingPeter Maydell2-5/+10
* sstabellini/xen-170114: xen_pt: Fix passthrough of device with ROM. xen_pt: Fix debug output. xenfb: map framebuffer read-only and handle unmap errors Message-id: alpine.DEB.2.02.1401171537140.21510@kaball.uk.xensource.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30Merge remote-tracking branch 'stefanha/tags/net-pull-request' into stagingPeter Maydell3-13/+12
Net patches # gpg: Signature made Mon 27 Jan 2014 14:45:35 GMT using RSA key ID 81AB73C8 # gpg: Can't check signature: public key not found * stefanha/tags/net-pull-request: tap-linux: Get features once and use it many times Fix lan9118 buffer length handling Fix lan9118 TX "CMD A" handling net: Use g_strdup_printf instead of snprintf. Message-id: 1390834129-19625-1-git-send-email-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30Merge remote-tracking branch 'rth/tcg-movbe' into stagingPeter Maydell2-52/+101
* rth/tcg-movbe: tcg/i386: cleanup useless #ifdef tcg/i386: use movbe instruction in qemu_ldst routines tcg/i386: add support for three-byte opcodes tcg/i386: remove hardcoded P_REXW value disas/i386.c: disassemble movbe instruction Message-id: 1390692772-15282-1-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30Merge remote-tracking branch 'mjt/tags/trivial-patches-2014-01-16' into stagingPeter Maydell12-12/+16
trivial-patches for 2014-01-16 # gpg: Signature made Thu 16 Jan 2014 17:29:05 GMT using RSA key ID 74F0C838 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: E190 8639 3B10 B51B AC2C 8B73 5253 C5AD 74F0 C838 Message-id: 1389893719-16336-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30TCG: Fix I64-on-32bit-host temporariesAlexander Graf1-1/+1
We have cache pools of temporaries that we can reuse later when they've already been allocated before. These cache pools differenciate between the target TCG variable type they contain. So we have one pool for I32 and one pool for I64 variables. On a 32bit system, we can't work with 64bit registers though. So instead we spawn two I32 temporaries for every I64 temporary we create. All caching works the same way as on a real 64-bit system though: We create a cache entry in the 64bit array for the first i32 index. However, when we free such a temporary we free it to the pool of its type (which is always i32 on 32bit systems) rather than its base_type (which is i64 or i32 depending on the variable). This means we put a temporary that is of base_type == i64 into the i32 preallocated temporary pool. Eventually, this results in failures like this on 32bit hosts: qemu-system-ppc64: tcg/tcg.c:515: tcg_temp_new_internal: Assertion `ts->base_type == type' failed. This patch makes the free routine use the base_type instead for the free case, so it's consistent with the temporary allocation. It fixes the above failure for me. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1390146811-59936-1-git-send-email-agraf@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-27trace: fix simple trace "disable" keywordStefan Hajnoczi1-1/+2
The trace-events "disable" keyword turns an event into a nop at compile-time. This is important for high-frequency events that can impact performance. The "disable" keyword is currently broken in the simple trace backend. This patch fixes the problem as follows: Trace events are identified by their TraceEventID number. When events are disabled there are two options for assigning TraceEventID numbers: 1. Skip disabled events and don't assign them a number. 2. Assign numbers for all events regardless of the disabled keyword. The simple trace backend and its binary file format uses approach #1. The tracetool infrastructure has been using approach #2 for a while. The result is that the numbers used in simple trace files do not correspond with TraceEventIDs. In trace/simple.c we assumed that they are identical and therefore emitted bogus numbers. This patch fixes the bug by using TraceEventID for trace_event_id() while sticking to approach #1 for simple trace file numbers. This preserves simple trace file format compatibility. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27trace: add glib 2.32+ static GMutex supportStefan Hajnoczi1-7/+16
The GStaticMutex API was deprecated in glib 2.32. We cannot switch over to GMutex unconditionally since we would drop support for older glib versions. But the deprecated API warnings during build are annoying so use static GMutex when possible. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27trace: [simple] Do not include "trace/simple.h" in generated tracer headersLluís Vilanova2-3/+1
The header is not necessary, given that the simple backend does not define any inlined tracing routines. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27tracing: start trace processing thread in final child processMichael Mueller1-2/+10
When running with trace backend e.g. "simple" the writer thread needs to be implemented in the same process context as the trace points that will be processed. Under libvirtd control, qemu gets first started in daemonized mode to privide its capabilities. Creating the writer thread in the initial process context then leads to a dead lock because the thread gets termined together with the initial parent. (-daemonize) Signed-off-by: Michael Mueller <mimu@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [minor whitespace fixes] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27tap-linux: Get features once and use it many timesKusanagi Kouichi1-6/+8
Signed-off-by: Kusanagi Kouichi <slash@ac.auone-net.jp> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27Fix lan9118 buffer length handlingRoy Franz1-1/+1
The 9118 ethernet controller supports transmission of multi-buffer packets with arbitrary byte alignment of the start and end bytes. All writes to the packet fifo are 32 bits, so the controller discards bytes at the beginning and end of each buffer based on the 'Data start offset' and 'Buffer size' of the TX command 'A' format. This patch uses the provided buffer length to limit the bytes transmitted. Previously all the bytes of the last 32-bit word written to the TX fifo were added to the internal transmit buffer structure resulting in more bytes being transmitted than were submitted to the hardware in the command. This resulted in extra bytes being inserted into the middle of multi-buffer packets when the non-final buffers had non-32bit aligned ending addresses. Signed-off-by: Roy Franz <roy.franz@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27Fix lan9118 TX "CMD A" handlingRoy Franz1-2/+2
The 9118 ethernet controller supports transmission of multi-buffer packets with arbitrary byte alignment of the start and end bytes. All writes to the packet fifo are 32 bits, so the controller discards bytes at the beginning and end of each buffer based on the 'Data start offset' and 'Buffer size' of the TX command 'A' format. This patch changes the buffer size and offset internal state variables to be updated on every "TX command A" write. Previously they were only updated for the first segment, which resulted incorrect behavior for packets with more than one segment. Each segment of the packet has its own CMD A command, with its own buffer size and start offset. Also update extraction of fields from the CMD A word to use extract32(). Signed-off-by: Roy Franz <roy.franz@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-27net: Use g_strdup_printf instead of snprintf.Hani Benhabiles1-4/+1
assign_name() in net/net.c is using snprintf + g_strdup to get the same result as g_strdup_printf. Signed-off-by: Hani Benhabiles <kroosec@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-01-26MAINTAINERS: add self as virtio co-maintainerMichael S. Tsirkin1-0/+1
This will help make sure I get Cc'd on patches. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26q35: document gigabyte_alignMichael S. Tsirkin1-0/+13
Document the logic behind the below/above 4G split. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26q35: gigabyte alignment for ramGerd Hoffmann1-2/+5
Map 2G (q35) of memory below 4G, so the RAM pieces are nicely aligned to gigabyte borders. Keep old memory layout for (a) old machine types and (b) in case all memory fits below 4G and thus we don't have to split RAM into pieces in the first place. The later makes sure this change doesn't take away memory from 32bit guests. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26acpi: Fix PCI hole handling on build_srat()Eduardo Habkost1-5/+5
The original SeaBIOS code used the RamSize variable, that was used by SeaBIOS for the size of RAM below 4GB, not for all RAM. When copied to QEMU, the code was changed to use the full RAM size, and this broke the build_srat() code that handles the PCI hole. Change build_srat() to use ram_size_below_4g instead of ram_size, to restore the original behavior from SeaBIOS. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: Save size of RAM below 4GBEduardo Habkost2-1/+2
The ram_below_4g value will be useful in other places, such as the ACPI table code, and other code that currently requires passing below_4g_mem_size around in function arguments. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26hw/pci: fix error flow in pci multifunction initMarcel Apfelbaum1-10/+10
Scenario: - There is a non multifunction pci device A on 00:0X.0. - Hot-plug another multifunction pci device B at 00:0X.1. - The operation will fail of course. - Try to hot-plug the B device 2-3 more times, qemu will crash. Reason: The error flow leaves the B's address space into global address spaces list, but the device object is freed. Fixed that. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26acpi-test: update expected AML since recent changesMichael S. Tsirkin4-0/+0
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generatedIgor Mammedov4-92/+225
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: ACPI: unify source of CPU hotplug IO base/lenIgor Mammedov6-7/+9
use C headers defines as source of IO base/len for respective values in ASL code. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: ACPI: expose PRST IO range via _CRSIgor Mammedov1-1/+13
.. so OSPM could notice resource conflict if there is any. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resourcesIgor Mammedov3-7/+15
... for range defined at hw/acpi/ich9.c:ICH9_PROC_BASE Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resourcesIgor Mammedov3-7/+41
.. so that they might not be used by PCI devices. Note: Resort to concatenating templates with preprocessor help, because 1.0b spec isn't supporting ConcatenateResTemplate, as result Windows XP fails to execute PCI0._CRS method if ConcatenateResTemplate() is used. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26pc: set PRST base in DSDT depending on chipsetIgor Mammedov3-1/+3
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-01-26acpi: ich9: add CPU hotplug handling to Q35 machineIgor Mammedov4-1/+22
.. use IO port 0cd8-0xcf7 range for CPU present bitmap Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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