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2016-06-27hw/net/rocker: Don't use *_to_cpup()Peter Maydell1-3/+3
Don't use *_to_cpup() to do byte-swapped loads; instead use ld*_p() which correctly handle misaligned accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Jason Wang <jasowang@redhat.com> Acked-by: Dmitry Fleytman <dmitry@daynix.com <mailto:dmitry@daynix.com>> Message-id: 1466097446-981-4-git-send-email-peter.maydell@linaro.org
2016-06-27hw/net/rtl8139.c: Don't use *_to_cpup()Peter Maydell1-5/+4
Don't use *_to_cpup() to do byte-swapped loads; instead use ld*_p() which correctly handle misaligned accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Jason Wang <jasowang@redhat.com> Acked-by: Dmitry Fleytman <dmitry@daynix.com <mailto:dmitry@daynix.com>> Message-id: 1466097446-981-3-git-send-email-peter.maydell@linaro.org
2016-06-27hw/net/eepro100.c: Don't use cpu_to_*w() and *_to_cpup()Peter Maydell1-4/+4
Don't use cpu_to_*w() and *_to_cpup() to do byte-swapped loads and stores; instead use ld*_p() and st*_p() which correctly handle misaligned accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Jason Wang <jasowang@redhat.com> Acked-by: Dmitry Fleytman <dmitry@daynix.com <mailto:dmitry@daynix.com>> Message-id: 1466097446-981-2-git-send-email-peter.maydell@linaro.org
2016-06-27Merge remote-tracking branch ↵Peter Maydell12-70/+698
'remotes/pmaydell/tags/pull-target-arm-20160627' into staging target-arm queue: * arm_gicv3: add missing 'break' statements * cadence_uart: protect against transmit errors * cadence_gem: avoid infinite loops with misconfigured buffer * cadence_gem: set the 'last' bit when 'wrap' is set * reenable tmp105 test case * palmetto-bmc: add ASPEED system control unit model * m25p80: add new 512Mbit and 1Gbit devices # gpg: Signature made Mon 27 Jun 2016 15:43:42 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160627: m25p80: Fix WINBOND fast read command handling m25p80: New flash devices. m25p80: Fast read commands family changes. m25p80: Introduce configuration registers. m25p80: Introduce quad and equad modes. m25p80: Add additional flash commands: m25p80: Introduce COLLECTING_VAR_LEN_DATA state. m25p80: Allow more than four banks. m25p80: Make a table for JEDEC ID. m25p80: Replace JEDEC ID masking with function. palmetto-bmc: Configure the SCU's hardware strapping register ast2400: Integrate the SCU model and set silicon revision hw/misc: Add a model for the ASPEED System Control Unit arm: Re-enable tmp105 test cadence_gem: Set the last bit when wrap is set cadence_gem: Avoid infinite loops with a misconfigured buffer cadence_uart: Protect against transmit errors hw/intc/arm_gicv3: Add missing break Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Fix WINBOND fast read command handlingMarcin Krzeminski1-2/+5
This commit fix obvious bug in WINBOND command handling. Datasheet states that default dummy cycles is 8 so fix it. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Message-id: 1466755631-25201-11-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: New flash devices.Marcin Krzeminski1-6/+13
Macronix: mx66u51235f and mx66u1g45g Micron: mt25ql01g and mt25qu01g Spansion: s25fs512s and s70fs01gs Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-10-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Fast read commands family changes.Marcin Krzeminski1-37/+117
Support for Spansion and Macronix flashes. Additionally Numonyx(Micron) moved from default in fast read commands family. Also moved fast read command decoding to functions. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-9-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Introduce configuration registers.Marcin Krzeminski1-0/+47
Configuration registers for Spansion and Macronix devices. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-8-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Introduce quad and equad modes.Marcin Krzeminski1-5/+65
Quad and Equad modes for Spansion and Macronix flash devices. This commit also includes modification and new command to manipulate quad mode (status registers and dedicated commands). This work is based on Pawel Lenkow work. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-7-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Add additional flash commands:Marcin Krzeminski1-0/+9
Page program 4byte/quad and erase 32K sectors 4 bytes. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-6-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Introduce COLLECTING_VAR_LEN_DATA state.Marcin Krzeminski1-0/+5
Some flash allows to stop read at any time. Allow framework to support this. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-5-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Allow more than four banks.Marcin Krzeminski1-3/+2
Allow to have more than four 16MiB regions for bigger flash devices. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-4-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Make a table for JEDEC ID.Marcin Krzeminski1-19/+42
Since it is now longer than 4. This work based on Pawel Lenkow changes and the kernel SPI framework. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466755631-25201-3-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27m25p80: Replace JEDEC ID masking with function.Marcin Krzeminski1-9/+40
Instead of always reading and comparing jededc ID, replace it by function. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Message-id: 1466755631-25201-2-git-send-email-marcin.krzeminski@nokia.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27palmetto-bmc: Configure the SCU's hardware strapping registerAndrew Jeffery1-0/+2
The magic constant configures the following options: * 28:27: Configure DRAM size as 256MB * 26:24: DDR3 SDRAM with CL = 6, CWL = 5 * 23: Configure 24/48MHz CLKIN * 22: Disable GPIOE pass-through mode * 21: Disable GPIOD pass-through mode * 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses * 19: Disable ACPI * 18: Configure 48MHz CLKIN * 17: Disable BMC 2nd boot watchdog timer * 16: Decode SuperIO address 0x2E * 15: VGA Class Code * 14: Enable LPC dedicated reset pin * 13:12: Enable SPI Master and SPI Slave to AHB Bridge * 11:10: Select CPU:AHB ratio = 2:1 * 9:8: Select 384MHz H-PLL * 7: Configure MAC#2 for RMII/NCSI * 6: Configure MAC#1 for RMII/NCSI * 5: No VGA BIOS ROM * 4: Boot using 32bit SPI address mode * 3:2: Select 16MB VGA memory * 1:0: Boot from SPI flash memory Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466744305-23163-4-git-send-email-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27ast2400: Integrate the SCU model and set silicon revisionAndrew Jeffery2-0/+23
By specifying the silicon revision we select the appropriate reset values for the SoC. Additionally, expose hardware strapping properties aliasing those provided by the SCU for board-specific configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1466744305-23163-3-git-send-email-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27hw/misc: Add a model for the ASPEED System Control UnitAndrew Jeffery4-0/+321
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes. Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping. Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1466744305-23163-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop unnecessary inttypes.h include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27arm: Re-enable tmp105 testThomas Huth1-1/+1
The tmp105 test is currently not executed since the following line in the Makefile overwrites the check-qtest-arm-y variable instead of extending it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1466760306-21849-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27cadence_gem: Set the last bit when wrap is setAlistair Francis1-0/+6
The Cadence GEM data sheet says: "Wrap - marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame." which seems to imply that when the wrap bit is set so is the last bit. Previously if the wrap bit is set, but the last is not then QEMU will enter an infinite loop. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reported-by: Li Qiang <liqiang6-s@360.cn> Reported-by: P J P <ppandit@redhat.com> Message-id: eb23f15c67989ea6a53609dc66568399dadf52a7.1466539342.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27cadence_gem: Avoid infinite loops with a misconfigured bufferAlistair Francis1-0/+7
A guest can write zero to the DMACFG resulting in an infinite loop when it reaches the while(bytes_to_copy) loop. To avoid this issue enforce a minimum size for the RX buffer. Hardware does not have this enforcement and relies on the guest to set a non-zero value. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reported-by: Li Qiang <liqiang6-s@360.cn> Reported-by: P J P <ppandit@redhat.com> Message-id: 84bb1c391b833275da3f573d4972920cea34c188.1466539342.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27cadence_uart: Protect against transmit errorsAlistair Francis1-2/+5
If qemu_chr_fe_write() returns an error (represented by a negative number) we should skip incrementing the count and initiating a memmove(). Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 667e5dc534d33338fcfc2471e5aa32fe7cbd13dc.1466546703.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27hw/intc/arm_gicv3: Add missing breakShannon Zhao1-0/+2
These are spotted by coverity 1356936 and 1356937. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1466387717-13740-1-git-send-email-zhaoshenglong@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160627' ↵Peter Maydell8-33/+29
into staging ppc patch queue for 2016-06-27 Small queue this time. Main reason for sending it is the pair of patches to fix up the new cpu hotplug model used on Power to what should be an actually usable state. There's also a small BookE bugfix and a XICS trivial cleanup. # gpg: Signature made Mon 27 Jun 2016 06:28:37 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160627: qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCore qapi: Report support for -device cpu hotplug in query-machines ppc/xics: Remove unused xics_set_irq_type() target-ppc: ppce500_spin.c uses SPR_PIR, should use SPR_BOOKE_PIR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160624' into stagingPeter Maydell22-673/+1167
MIPS patches 2016-06-24 Changes: * support IEEE 754-2008 in MIPS CPUs # gpg: Signature made Fri 24 Jun 2016 16:09:38 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160624: target-mips: Add FCR31's FS bit definition target-mips: Implement FCR31's R/W bitmask and related functionalities target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA linux-user: Update preprocessor constants for Mips-specific e_flags bits softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd() softfloat: For Mips only, correct default NaN values softfloat: Clean code format in fpu/softfloat-specialize.h softfloat: Implement run-time-configurable meaning of signaling NaN bit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell1-1/+4
staging qemu-sparc update # gpg: Signature made Fri 24 Jun 2016 18:19:36 BST # gpg: using RSA key 0x5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: target-sparc: fix register corruption in ldstub if there is no write permission Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCorePeter Krempa4-19/+23
struct CPUCore uses 'id' suffix in the property name. As docs for query-hotpluggable-cpus state that the cpu core properties should be passed back to device_add by management in case new members are added and thus the names for the fields should be kept in sync. Signed-off-by: Peter Krempa <pkrempa@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [dwg: Removed a duplicated word in comment] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-27qapi: Report support for -device cpu hotplug in query-machinesPeter Krempa2-1/+5
For management apps it's very useful to know whether the selected machine type supports cpu hotplug via the new -device approach. Using the presence of 'query-hotpluggable-cpus' alone is not enough as a witness. Add a property to 'MachineInfo' called 'hotpluggable-cpus' that will report the presence of this feature. Example of output: { "hotpluggable-cpus": false, "name": "mac99", "cpu-max": 1 }, { "hotpluggable-cpus": true, "name": "pseries-2.7", "is-default": true, "cpu-max": 255, "alias": "pseries" }, Signed-off-by: Peter Krempa <pkrempa@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-27ppc/xics: Remove unused xics_set_irq_type()Benjamin Herrenschmidt2-12/+0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Adjusted for context to apply without original series] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-27target-ppc: ppce500_spin.c uses SPR_PIR, should use SPR_BOOKE_PIRAaron Larson1-1/+1
ppce500_spin.c uses SPR_PIR to initialize the spin table, however on Book E processors the correct SPR is SPR_BOOKE_PIR. Signed-off-by: Aaron Larson <alarson@ddci.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-24target-sparc: fix register corruption in ldstub if there is no write permissionArtyom Tarasenko1-1/+4
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2016-06-24target-mips: Add FCR31's FS bit definitionAleksandar Markovic1-1/+2
Add preprocessor definition of FCR31's FS bit, and update related code for setting this bit. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24target-mips: Implement FCR31's R/W bitmask and related functionalitiesAleksandar Markovic6-19/+56
This patch implements read and write access rules for Mips floating point control and status register (FCR31). The change can be divided into following parts: - Add fields that will keep FCR31's R/W bitmask in procesor definitions and processor float_status structure. - Add appropriate value for FCR31's R/W bitmask for each supported processor. - Add function for setting snan_bit_is_one, and integrate it in appropriate places. - Modify handling of CTC1 (case 31) instruction to use FCR31's R/W bitmask. - Modify handling user mode executables for Mips, in relation to the bit EF_MIPS_NAN2008 from ELF header, that is in turn related to reading and writing to FCR31. - Modify gdb behavior in relation to FCR31. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>Aleksandar Markovic3-48/+461
New set of helpers for handling nan2008-syle versions of instructions <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6. All involved instructions have float operand and integer result. Their core functionality is implemented via invocations of appropriate SoftFloat functions. The problematic cases are when the operand is a NaN, and also when the operand (float) is out of the range of the result. Here one can distinguish three cases: CASE MIPS-A: (FCR31.NAN2008 == 1) 1. Operand is a NaN, result should be 0; 2. Operand is larger than INT_MAX, result should be INT_MAX; 3. Operand is smaller than INT_MIN, result should be INT_MIN. CASE MIPS-B: (FCR31.NAN2008 == 0) 1. Operand is a NaN, result should be INT_MAX; 2. Operand is larger than INT_MAX, result should be INT_MAX; 3. Operand is smaller than INT_MIN, result should be INT_MAX. CASE SoftFloat: 1. Operand is a NaN, result is INT_MAX; 2. Operand is larger than INT_MAX, result is INT_MAX; 3. Operand is smaller than INT_MIN, result is INT_MIN. Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> implements case MIPS-B. This patch relates to case MIPS-A. For case MIPS-A, only return value for NaN-operands should be corrected after appropriate SoftFloat library function is called. Related MSA instructions FTRUNC_S and FTINT_S already handle well all cases, in the fashion similar to the code from this patch. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: * removed a statement from the description which caused slight confusion] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>Aleksandar Markovic1-4/+22
Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy (pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore, any NaN operand causes signaling invalid operation), while abs2008 ones are non-arithmetic, always and only changing the sign bit, even for NaN-like operands. Details on these instructions are documented in [1] p. 35 and 359. Implementation-wise, abs2008 versions are implemented without helpers, for simplicity and performance sake. [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSAAleksandar Markovic1-1/+2
Function msa_reset() is updated so that flag snan_bit_is_one is properly set to 0. By applying this patch, a number of incorrect MSA behaviors that require IEEE 754-2008 compliance will be fixed. Those are behaviors that (up to the moment of applying this patch) did not get the desired functionality from SoftFloat library with respect to distinguishing between quiet and signaling NaN, getting default NaN values (both quiet and signaling), establishing if a floating point number is NaN or not, etc. Two examples: * FMAX, FMIN will now correctly detect and propagate NaNs. * FCLASS.D ans FCLASS.S will now correcty detect NaN flavors. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24linux-user: Update preprocessor constants for Mips-specific e_flags bitsAleksandar Markovic1-0/+2
Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd()Aleksandar Markovic1-12/+29
Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct the order of argument comparisons in pickNaNMulAdd(). For more info, see [1], page 53, section "3.5.3 NaN Propagation". [1] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * reworded the subject of the patch * swapped if/else code blocks to match the commit description] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: For Mips only, correct default NaN valuesAleksandar Markovic1-0/+12
Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct default NaN values (in their 16-, 32-, and 64-bit flavors). For more info, see [1], page 84, Table 6.3 "Value Supplied When a New Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN Encodings". [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 [2] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Clean code format in fpu/softfloat-specialize.hAleksandar Markovic1-29/+28
fpu/softfloat-specialize.h is the most critical file in SoftFloat library, since it handles numerous differences between platforms in relation to floating point arithmetics. This patch makes the code in this file more consistent format-wise, and hopefully easier to debug and maintain. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic19-561/+555
This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * cherry-picked 2 chunks from patch #2 to fix compilation warnings] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-24Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell53-439/+2505
pc, pci, virtio: new features, cleanups, fixes nvdimm label support cpu acpi hotplug rework virtio rework misc cleanups and fixes Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 24 Jun 2016 06:50:32 BST # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (34 commits) virtio-bus: remove old set_host_notifier callback virtio-mmio: convert to ioeventfd callbacks virtio-pci: convert to ioeventfd callbacks virtio-ccw: convert to ioeventfd callbacks virtio-bus: have callers tolerate new host notifier api virtio-bus: common ioeventfd infrastructure pc: acpi: drop intermediate PCMachineState.node_cpu acpi-test-data: update expected pc: use new CPU hotplug interface since 2.7 machine type acpi: cpuhp: add cpu._OST handling acpi: cpuhp: implement hot-remove parts of CPU hotplug interface acpi: cpuhp: implement hot-add parts of CPU hotplug interface pc: acpi: introduce AcpiDeviceIfClass.madt_cpu hook acpi: cpuhp: add CPU devices AML with _STA method pc: piix4/ich9: add 'cpu-hotplug-legacy' property docs: update ACPI CPU hotplug spec with new protocol i386: pci-assign: Fix MSI-X table size docs: add NVDIMM ACPI documentation nvdimm acpi: support Set Namespace Label Data function nvdimm acpi: support Get Namespace Label Data function ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-24virtio-bus: remove old set_host_notifier callbackCornelia Huck4-38/+7
All users have been converted to the new ioevent callbacks. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24virtio-mmio: convert to ioeventfd callbacksCornelia Huck1-87/+41
Convert to the new interface. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24virtio-pci: convert to ioeventfd callbacksCornelia Huck1-83/+41
Convert to new interface. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24virtio-ccw: convert to ioeventfd callbacksCornelia Huck1-88/+45
Use the new interface. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24virtio-bus: have callers tolerate new host notifier apiCornelia Huck3-12/+42
Have vhost and dataplane use the new api for transports that have been converted. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24virtio-bus: common ioeventfd infrastructureCornelia Huck2-0/+162
Introduce a set of ioeventfd callbacks on the virtio-bus level that can be implemented by the individual transports. At the virtio-bus level, do common handling for host notifiers (which is actually most of it). Two things of note: - When setting the host notifier, we only switch from/to the generic ioeventfd handler. This fixes a latent bug where we had no ioeventfd assigned for a certain window. - We always iterate over all possible virtio queues, even though ccw (currently) has a lower limit. It does not really matter here. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: acpi: drop intermediate PCMachineState.node_cpuIgor Mammedov3-19/+9
PCMachineState.node_cpu was used for mapping APIC ID to numa node id as CPU entries in SRAT used to be built on sparse APIC ID bitmap (up to apic_id_limit). However since commit 5803fce pc: acpi: SRAT: create only valid processor lapic entries CPU entries in SRAT aren't build using apic bitmap but using 0..maxcpus index instead which is also used for creating numa_info[x].node_cpu map. So instead of doing useless intermediate conversion from 1. node by cpu index -> node by apic id i.e. numa_info[x].node_cpu -> PCMachineState.node_cpu 2. apic id -> srat entry PMX PCMachineState.node_cpu[apic id] -> PMX value use numa_info[x].node_cpu map directly like ARM does and do 1. numa_info[x].node_cpu -> PMX value using index in range 0..maxcpus and drop not necessary PCMachineState.node_cpu and related code. That also removes the last (not counting legacy hotplug) dependency of ACPI code on apic_id_limit and need to allocate huge sparse PCMachineState.node_cpu array in case of 32-bit APIC IDs. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24acpi-test-data: update expectedMichael S. Tsirkin6-0/+0
switched to new cpu hotplug interface, aml changed. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-24pc: use new CPU hotplug interface since 2.7 machine typeIgor Mammedov10-2/+118
For compatibility reasons PC/Q35 will start with legacy CPU hotplug interface by default but with new CPU hotplug AML code since 2.7 machine type. That way legacy firmware that doesn't use QEMU generated ACPI tables will be able to continue using legacy CPU hotplug interface. While new machine type, with firmware supporting QEMU provided ACPI tables, will generate new CPU hotplug AML, which will switch to new CPU hotplug interface when guest OS executes its _INI method on ACPI tables loading. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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