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2021-03-07esp: use in-built TC to determine PDMA transfer lengthMark Cave-Ayland2-16/+13
2021-03-07esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMAMark Cave-Ayland2-16/+8
2021-03-07esp: move PDMA length adjustments into esp_pdma_read()/esp_pdma_write()Mark Cave-Ayland1-10/+14
2021-03-07esp: remove redundant pdma_start from ESPStateMark Cave-Ayland2-18/+2
2021-03-07esp: remove the buf and buflen parameters from get_cmd()Mark Cave-Ayland1-5/+6
2021-03-07esp: remove buf parameter from do_cmd()Mark Cave-Ayland1-6/+7
2021-03-07esp: accumulate SCSI commands for PDMA transfers in cmdbuf instead of pdma_bufMark Cave-Ayland2-33/+25
2021-03-07esp: move pdma_len and TC logic into esp_pdma_read()/esp_pdma_write()Mark Cave-Ayland1-18/+32
2021-03-07esp: use pdma_origin directly in esp_pdma_read()/esp_pdma_write()Mark Cave-Ayland1-6/+28
2021-03-07esp: introduce esp_pdma_read() and esp_pdma_write() functionsMark Cave-Ayland1-8/+20
2021-03-07esp: remove minlen restriction in handle_tiMark Cave-Ayland1-10/+2
2021-03-07esp: remove dma_left from ESPStateMark Cave-Ayland2-18/+34
2021-03-07esp: remove dma_counter from ESPStateMark Cave-Ayland2-6/+1
2021-03-07esp: apply transfer length adjustment when STC is zero at TC load timeMark Cave-Ayland1-4/+5
2021-03-07esp: introduce esp_get_stc()Mark Cave-Ayland1-3/+12
2021-03-07esp: introduce esp_get_tc() and esp_set_tc()Mark Cave-Ayland1-15/+23
2021-03-07esp: determine transfer direction directly from SCSI phaseMark Cave-Ayland1-3/+2
2021-03-07esp: add PDMA trace eventsMark Cave-Ayland2-0/+10
2021-03-07esp: fix esp_reg_read() trace eventMark Cave-Ayland1-6/+12
2021-03-07esp: add trace event when receiving a TI commandMark Cave-Ayland2-0/+2
2021-03-07esp: add vmstate_esp version to embedded ESPStateMark Cave-Ayland3-3/+25
2021-03-07esp: QOMify the internal ESP device stateMark Cave-Ayland3-20/+82
2021-03-07esp: rename existing ESP QOM type to SYSBUS_ESPMark Cave-Ayland6-13/+13
2021-03-07esp: checkpatch fixesMark Cave-Ayland1-21/+31
2021-03-05Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305' into...Peter Maydell8-17/+48
2021-03-05Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-03-05' into ...Peter Maydell6-56/+45
2021-03-05qapi: Fix parse errors for removal of null from schema languageMarkus Armbruster3-6/+6
2021-03-05qapi: Remove QMP events and commands from user-mode buildsPhilippe Mathieu-Daudé1-4/+8
2021-03-05qga: Utilize QAPI_LIST_APPEND in qmp_guest_network_get_interfacesEric Blake1-45/+30
2021-03-05error: Fix "Converting to ERRP_GUARD()" doc on "valid at return"Markus Armbruster1-1/+1
2021-03-05Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell29-64/+1285
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng6-37/+19
2021-03-04MAINTAINERS: Add a SiFive machine sectionAlistair Francis1-0/+9
2021-03-04goldfish_rtc: re-arm the alarm after migrationLaurent Vivier1-0/+2
2021-03-04docs/system: riscv: Add documentation for sifive_u machineBin Meng2-0/+346
2021-03-04docs/system: Add RISC-V documentationBin Meng2-0/+63
2021-03-04docs/system: Sort targets in alphabetical orderBin Meng1-7/+12
2021-03-04hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng1-1/+1
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng3-2/+45
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng3-0/+58
2021-03-04hw/ssi: Add SiFive SPI controller supportBin Meng4-0/+410
2021-03-04hw/block: m25p80: Add various ISSI flash informationBin Meng1-0/+13
2021-03-04hw/block: m25p80: Add ISSI SPI flash supportBin Meng1-1/+43
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang5-0/+210
2021-03-04roms/opensbi: Upgrade from v0.8 to v0.9Bin Meng5-0/+0
2021-03-04hw/misc: sifive_u_otp: Use error_report() when block operation failsBin Meng1-8/+5
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng1-1/+1
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