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2023-10-25hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc fieldPhilippe Mathieu-Daudé1-49/+52
We want to derivate the big AspeedSoCState object in some more SoC-specific ones. Since the object size will vary, allocate it dynamically. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-10-25hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specificPhilippe Mathieu-Daudé1-4/+11
Keep aspeed_soc_class_init() generic, set the realize handler to aspeed_ast2400_soc_realize() in each 2400/2500 class_init. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-10-25hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specificPhilippe Mathieu-Daudé1-3/+3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-10-25hw/arm/aspeed: Extract code common to all boards to a common filePhilippe Mathieu-Daudé3-96/+115
aspeed_soc.c contains definitions specific to the AST2400 and AST2500 SoCs, but also some definitions for other AST SoCs: move them to a common file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-10-25MAINTAINERS: aspeed: Update Andrew's email addressAndrew Jeffery1-1/+1
I've changed employers, have company email that deals with patch-based workflows without too much of a headache, and am trying to steer some content out of my personal mail. Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-10-23Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi22-987/+1127
tcg: Drop unused tcg_temp_free define tcg: Introduce tcg_use_softmmu tcg: Optimize past conditional branches tcg: Use constant zero when expanding with divu2 tcg: Add negsetcondi tcg: Define MO_TL tcg: Export tcg_gen_ext_{i32,i64,tl} target/*: Use tcg_gen_ext_* tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB tcg/ppc: Use ADDPCIS for power9 tcg/ppc: Use prefixed instructions for power10 tcg/ppc: Disable TCG_REG_TB for Power9/Power10 tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB tcg/ppc: Use ADDPCIS for power9 tcg/ppc: Use prefixed instructions for power10 tcg/ppc: Disable TCG_REG_TB for Power9/Power10 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU2t18dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9uXQgAhT1mDy5sg7mfSWuc # X7i54C3n6Ykyra0HDG47dt4G0gkACEs7tDkllHIxhqTPKCrzpevyZEoyigr2MEOa # 3GCwxvJORb27Ql2aiM1K8cdlEbzcrx+RZbl4lwqZpZbmMUbz/ZQI4xPEAf2yKdfB # jTzi+Iu6ziPVqVQrg6fTm1I7YgQI85qcfKxi5lBaXgSfxPXGSlLeDw9Y8QjLHXRx # nSiGpWiUd5TkqZgLIctShDbK4NEHcvjXUTW4rMWU9l5Cjdf9ZIhxcCxgKTXtOxBi # 9tUdGOiup2HudOFf+DpQorzWpwRwy3NGpUF7n+WmevQZ1Qh8uNKsveFB0uuqObLg # zlTI2Q== # =lgiT # -----END PGP SIGNATURE----- # gpg: Signature made Mon 23 Oct 2023 11:11:43 PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu: (38 commits) target/xtensa: Use tcg_gen_sextract_i32 target/tricore: Use tcg_gen_*extract_tl target/rx: Use tcg_gen_ext_i32 target/m68k: Use tcg_gen_ext_i32 target/i386: Use tcg_gen_ext_tl target/arm: Use tcg_gen_ext_i64 tcg: Define MO_TL tcg: Export tcg_gen_ext_{i32,i64,tl} tcg: add negsetcondi target/i386: Use i128 for 128 and 256-bit loads and stores tcg: Add tcg_gen_{ld,st}_i128 tcg: Optimize past conditional branches tcg: Use constant zero when expanding with divu2 tcg: drop unused tcg_temp_free define tcg/s390x: Use tcg_use_softmmu tcg/riscv: Use tcg_use_softmmu tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero tcg/ppc: Use tcg_use_softmmu tcg/mips: Use tcg_use_softmmu tcg/loongarch64: Use tcg_use_softmmu ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-23Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi43-833/+1215
into staging virtio,pc,pci: features, cleanups infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU # pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd # 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT # ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV # 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa # zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= # =ILek # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Oct 2023 02:18:43 PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (62 commits) intel-iommu: Report interrupt remapping faults, fix return value MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section vhost-user: Fix protocol feature bit conflict tests/acpi: Update DSDT.cxl with QTG DSM hw/cxl: Add QTG _DSM support for ACPI0017 device tests/acpi: Allow update of DSDT.cxl hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range vhost-user: fix lost reconnect vhost-user-scsi: start vhost when guest kicks vhost-user-scsi: support reconnect to backend vhost: move and rename the conn retry times vhost-user-common: send get_inflight_fd once hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine hw/isa/piix: Implement multi-process QEMU support also for PIIX4 hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 hw/isa/piix: Rename functions to be shared for PCI interrupt triggering hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Share PIIX3's base class with PIIX4 hw/isa/piix: Harmonize names of reset control memory regions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-23Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingStefan Hajnoczi5-56/+43
trivial patches for 2023-10-21 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmUzviQPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZasYH/2ex+XBdvMGU9wghGXAqPCy6NEwzSQaaPkai # xuoly0Z3vahOgJK05lXH2bQmGPP1DG8la4fv8owysteIjSncBiq8Nk9+pHylgJJj # 7eZ6BPZu+xoJRTGrBhQC5F6cCAi2YQlgGwfH+bDB4YJPm2BdYbfMuw7Wm88gVDEh # nqbU6mtV1wGaDQJtHlpJNSACxWeN6Buq5Jcj27rpeCWAGlqeJBh8qEbPgN8nDnSm # mBb3DMAWtKAZPjQLnri1MRyyXnfBavBPmeTYHz4nQQHYmeHaGw4Cez5EswnZRlau # zyMMKwYK9eo7f5mFeTr3+I6XMbiIfuICGhFwLXnNqqlgB79R9w0= # =/gNQ # -----END PGP SIGNATURE----- # gpg: Signature made Sat 21 Oct 2023 05:03:48 PDT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: MAINTAINERS: Add the ompic.c file to the or1k-sim section MAINTAINERS: Fix typo in openpic_kvm.c entry MAINTAINERS: Add unvalued folders in tests/tcg/ to the right sections MAINTAINERS: Add PPC common files to PowerPC TCG CPUs MAINTAINERS: Add fw_cfg.c to PPC mac99 machine MAINTAINERS: Adjust file list for PPC pseries machine MAINTAINERS: Adjust file list for PPC e500 machines MAINTAINERS: Adjust file list for PPC 4xx CPUs MAINTAINERS: Adjust file list for PPC ref405ep machine ppc/{bamboo, virtex_ml507}: Remove useless dependency on ppc405.h header MAINTAINERS: Fix a couple s390 paths MAINTAINERS: Add docs/devel/ebpf_rss.rst to the EBPF section MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section MAINTAINERS: Add the nios2 interrupt controller to the nios2 section MAINTAINERS: Cover hw/ppc/ppc440_uc.c with Sam460ex board hw/ppc/ppc440_uc: Remove dead l2sram_update_mappings() hw/rdma/vmw/pvrdma_cmd: Use correct struct in query_port() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-23Merge tag 'hw-misc-20231020' of https://github.com/philmd/qemu into stagingStefan Hajnoczi1-1/+1
Misc hardware patch queue - MAINTAINERS updates (Zoltan, Thomas) - Fix cutils::get_relocated_path on Windows host (Akihiko) - Housekeeping in Memory APIs (Marc-André) - SDHCI fix for SDMA transfer (Lu, Jianxian) - Various QOM/QDev/SysBus cleanups (Philippe) - Constify QemuInputHandler structure (Philippe) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmUydwwACgkQ4+MsLN6t # wN6ROw//eFpuUdzFXEp3kdZMyKkP898G3L137i5b1p6Aq5SmFoVgeAmP/pAi8FVm # yAW68BKWXcYEikGLLFcq7UCW7v+dQXAAQdQHgo+1I9QPIytuWps+v9EFiuVY8EDW # Bd7H3IfGoBHlP5IJwzgpjzR9JEN2H6aEL5mNGXEdIsShNCw7ief4vwWvFjTv/mrS # bDHg8D6yUitnHAeQv9CMLlhbZXZvZtc/qKWtJjr+w42ZiV9HrmSR3RK07ydl311k # N8z2rWbLWw2q+BhmeMnCzdSB6eUq76ZZZbMdw5M+3GQVOKW4KdPoBKBnPIDPySRK # HoULrTAgAh/ZHB6l9kltDzXPTXD4oDSme+DB/aTTqvrXG/KqXFAjgwVwPC7AzONe # adtimxBXP3EHiLh2PBGBHpCa2+FON7rD23bVbuf5G0emFydU/3sPh+gCpvdzT9oT # iUifE9WstZg1tPvrRqwf8xoDXVx0f2v+h7V4WOoVWygYbA+1PkRImzsHcqqpOKYS # YLP857mtDYzL1xhW8gdwn4Zkmj6E6irICHbd4HDh5VQJMy8dQoUMT3DlxUPUOriW # vitoLJTvk6yHfUODXFcvs34wEgPGGlM5WM9qh2J0tpjUR6st/6tTTxZUkQ8a5QjM # q6+YZ85ZwtP3Eax16Re5hwcI1VrRyv/YdFQmTuiW1dQPGgQV+/8= # =KiWh # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Oct 2023 05:48:12 PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20231020' of https://github.com/philmd/qemu: (41 commits) ui/input: Constify QemuInputHandler structure hw/net: Declare link using static DEFINE_PROP_LINK() macro hw/dma: Declare link using static DEFINE_PROP_LINK() macro hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros hw/virtio/virtio-pmem: Replace impossible check by assertion hw/s390x/css-bridge: Realize sysbus device before accessing it hw/isa: Realize ISA bridge device before accessing it hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it hw/acpi: Realize ACPI_GED sysbus device before accessing it hw/pci-host/bonito: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Move sysbus_init_mmio() calls around hw/ppc/pnv: Do not use SysBus API to map local MMIO region hw/ppc/pnv_xscom: Do not use SysBus API to map local MMIO region ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-22target/xtensa: Use tcg_gen_sextract_i32Richard Henderson1-11/+1
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/tricore: Use tcg_gen_*extract_tlRichard Henderson1-16/+4
The EXTR instructions can use the extract opcodes. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/rx: Use tcg_gen_ext_i32Richard Henderson1-8/+3
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/m68k: Use tcg_gen_ext_i32Richard Henderson1-20/+3
We still need to check OS_{BYTE,WORD,LONG}, because m68k includes floating point in OS_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/i386: Use tcg_gen_ext_tlRichard Henderson1-25/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/arm: Use tcg_gen_ext_i64Richard Henderson1-35/+2
The ext_and_shift_reg helper does this plus a shift. The non-zero check for shift count is duplicate to the one done within tcg_gen_shli_i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Define MO_TLPaolo Bonzini1-0/+2
This will also come in handy later for "less than" comparisons. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <03ba02fd-fade-4409-be16-2f81a5690b4c@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Export tcg_gen_ext_{i32,i64,tl}Richard Henderson3-4/+14
The two concrete type functions already existed, merely needing a bit of hardening to invalid inputs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: add negsetcondiPaolo Bonzini3-0/+18
This can be useful to write a shift bit extraction that does not depend on TARGET_LONG_BITS. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231019104648.389942-15-pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22target/i386: Use i128 for 128 and 256-bit loads and storesRichard Henderson1-34/+29
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Add tcg_gen_{ld,st}_i128Richard Henderson2-0/+25
Do not require the translators to jump through concat and extract of i64 in order to move values to and from env. Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Optimize past conditional branchesRichard Henderson1-3/+5
We already register allocate through extended basic blocks, optimize through extended basic blocks as well. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Use constant zero when expanding with divu2Richard Henderson1-8/+8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: drop unused tcg_temp_free defineMike Frysinger1-2/+0
Use of the API was removed a while back, but the define wasn't. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231015010046.16020-1-vapier@gentoo.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/s390x: Use tcg_use_softmmuRichard Henderson1-80/+77
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/riscv: Use tcg_use_softmmuRichard Henderson1-87/+90
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zeroRichard Henderson1-2/+4
Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the JIT") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use tcg_use_softmmuRichard Henderson1-127/+129
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/mips: Use tcg_use_softmmuRichard Henderson1-110/+105
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/loongarch64: Use tcg_use_softmmuRichard Henderson1-65/+61
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/i386: Use tcg_use_softmmuRichard Henderson1-101/+99
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/aarch64: Use tcg_use_softmmuRichard Henderson1-88/+87
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/arm: Use tcg_use_softmmuRichard Henderson1-109/+100
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Provide guest_base fallback for system modeRichard Henderson1-0/+4
Provide a define to allow !tcg_use_softmmu code paths to compile in system mode, but require elimination. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg: Introduce tcg_use_softmmuRichard Henderson3-12/+19
Begin disconnecting CONFIG_SOFTMMU from !CONFIG_USER_ONLY. Introduce a variable which can be set at startup to select one method or another for user-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Disable TCG_REG_TB for Power9/Power10Richard Henderson1-1/+1
This appears to slightly improve performance on power9/10. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PLD in tcg_out_goto_tbRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use prefixed instructions in tcg_out_dupi_vecRichard Henderson1-0/+9
The prefixed instructions have a pc-relative form to use here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PLD in tcg_out_movi for constant poolRichard Henderson1-0/+24
The prefixed instruction has a pc-relative form to use here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use prefixed instructions in tcg_out_mem_longRichard Henderson1-0/+66
When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PADDI in tcg_out_moviRichard Henderson1-0/+51
PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_goto_tbRichard Henderson1-2/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS for the constant poolRichard Henderson1-0/+12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_movi_intRichard Henderson1-0/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_tb_startRichard Henderson1-3/+22
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Reinterpret tb-relative to TB+4Richard Henderson1-5/+10
It saves one insn to load the address of TB+4 instead of TB. Adjust all of the indexing to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TBJordan Niethe1-31/+17
Direct branch patching was disabled when using TCG_REG_TB in commit 736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation"). The issue with direct branch patching with TCG_REG_TB is the lack of synchronization between the new TCG_REG_TB being established and the direct branch being patched in. If each translation block is responsible for establishing its own TCG_REG_TB then there can be no synchronization issue. Make each translation block begin by setting up its own TCG_REG_TB. Use the preferred 'bcl 20,31,$+4' sequence. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> [rth: Split out tcg_out_tb_start, power9 addpcis] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Untabify tcg-target.c.incRichard Henderson1-3/+3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22intel-iommu: Report interrupt remapping faults, fix return valueDavid Woodhouse2-48/+103
A generic X86IOMMUClass->int_remap function should not return VT-d specific values; fix it to return 0 if the interrupt was successfully translated or -EINVAL if not. The VTD_FR_IR_xxx values are supposed to be used to actually raise faults through the fault reporting mechanism, so do that instead for the case where the IRQ is actually being injected. There is more work to be done here, as pretranslations for the KVM IRQ routing table can't fault; an untranslatable IRQ should be handled in userspace and the fault raised only when the IRQ actually happens (if indeed the IRTE is still not valid at that time). But we can work on that later; we can at least raise faults for the direct case. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Message-Id: <31bbfc9041690449d3ac891f4431ec82174ee1b4.camel@infradead.org> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-10-22MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip sectionThomas Huth1-0/+1
i8259.c is already listed here, so the corresponding header should be mentioned in this section, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231017152625.229022-1-thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-10-22vhost-user: Fix protocol feature bit conflictHanna Czenczek3-2/+15
The VHOST_USER_PROTOCOL_F_XEN_MMAP feature bit was defined in f21e95ee97d, which has been part of qemu's 8.1.0 release. However, it seems it was never added to qemu's code, but it is well possible that it is already used by different front-ends outside of qemu (i.e., Xen). VHOST_USER_PROTOCOL_F_SHARED_OBJECT in contrast was added to qemu's code in 16094766627, but never defined in the vhost-user specification. As a consequence, both bits were defined to be 17, which cannot work. Regardless of whether actual code or the specification should take precedence, F_XEN_MMAP is already part of a qemu release, while F_SHARED_OBJECT is not. Therefore, bump the latter to take number 18 instead of 17, and add this to the specification. Take the opportunity to add at least a little note on the VhostUserShared structure to the specification. This structure is referenced by the new commands introduced in 16094766627, but was not defined. Fixes: 160947666276c5b7f6bca4d746bcac2966635d79 ("vhost-user: add shared_object msg") Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016083201.23736-1-hreitz@redhat.com> Reviewed-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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