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2023-11-07hw/cxl: Use switch statements for read and write of cachemem registersJonathan Cameron1-23/+43
Establishing that only register accesses of size 4 and 8 can occur using these functions requires looking at their callers. Make it easier to see that by using switch statements. Assertions are used to enforce that the register storage is of the matching size, allowing fixed values to be used for divisors of the array indices. Suggested-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Message-Id: <20231023140210.3089-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07hw/cxl: Use a switch to explicitly check size in caps_reg_read()Jonathan Cameron1-4/+7
Bring this read function inline with the others that do check for unexpected size values. Also reduces line lengths to sub 80 chars. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fan Ni <fan.ni@samsung.com> Message-Id: <20231023140210.3089-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread ↵Zhao Liu4-3/+0
count2 test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000CA6 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[434h 1076 1] Subtable Type : 00 [Processor Local APIC] +[435h 1077 1] Length : 08 +[436h 1078 1] Processor ID : 81 +[437h 1079 1] Local Apic ID : 81 +[438h 1080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082 [snip] +[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC] +[C4Dh 3149 1] Length : 10 +[C4Eh 3150 2] Reserved : 0000 +[C50h 3152 4] Processor x2Apic ID : 00000181 +[C54h 3156 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[C58h 3160 4] Processor UID : 00000103 + +[C5Ch 3164 1] Subtable Type : 01 [I/O APIC] +[C5Dh 3165 1] Length : 0C +[C5Eh 3166 1] I/O Apic ID : 00 +[C5Fh 3167 1] Reserved : 00 +[C60h 3168 4] Address : FEC00000 +[C64h 3172 4] Interrupt : 00000000 + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 [snip] +[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000083EA (33770) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x01 + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C081, 0x81, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x81)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x81) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x81, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 thread count2Zhao Liu1-0/+31
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is more than 255, then smbios type4 table encodes threads per socket into the thread count2 field. So for the topology in this case, there're the following considerations: 1. threads per socket should be more than 255 to ensure we could cover the thread count2 field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count2 field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count2 field. Note we don't consider the topology with multiple sockets since this topology would create too many vCPUs (more than 255 threads per socket with at least 2 sockets, which may cause the failure "Number of hotpluggable cpus requested (*) exceeds the maximum cpus supported by KVM (*) socket_accept failed: Resource temporarily unavailable"), and the calculation of threads per socket has already been covered by "thread count" test case. Based on these considerations, select the topology as the follow: -smp cpus=210,maxcpus=260,dies=2,cores=65,threads=2 The expected thread count2 = threads per socket = threads (2) * cores (65) * dies (2) = 260. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231023094635.1588282-16-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu4-0/+3
thread count2 test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count2 field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-15-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread ↵Zhao Liu4-3/+0
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 63 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 thread countZhao Liu1-0/+27
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is not more than 255, then smbios type4 table encodes threads per socket into the thread count field. So for the topology in this case, there're the following considerations: 1. threads per socket should be not more than 255 to ensure we could cover the thread count field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count field. Based on these considerations, select the topology as the follow: -smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3 The expected thread count = threads per socket = threads (3) * cores (3) * dies (3) = 27. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-13-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu4-0/+3
thread count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-12-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Update ACPI table binaries for smbios core count2 testZhao Liu3-2/+0
Change the core count2 from 275 to 260. Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: APIC: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023 + * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023 * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 4] Table Length : 000009AE +[004h 0004 4] Table Length : 00000CA6 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : CE +[009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Local Apic Address : FEE00000 [028h 0040 4] Flags (decoded below) : 00000001 PC-AT Compatibility : 1 [02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] [02Dh 0045 1] Length : 08 [02Eh 0046 1] Processor ID : 00 [02Fh 0047 1] Local Apic ID : 00 [030h 0048 4] Flags (decoded below) : 00000001 Processor Enabled : 1 @@ -1051,1256 +1051,1136 @@ [42Ch 1068 1] Subtable Type : 00 [Processor Local APIC] [42Dh 1069 1] Length : 08 [42Eh 1070 1] Processor ID : 80 [42Fh 1071 1] Local Apic ID : 80 [430h 1072 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 [434h 1076 1] Subtable Type : 00 [Processor Local APIC] [435h 1077 1] Length : 08 [436h 1078 1] Processor ID : 81 [437h 1079 1] Local Apic ID : 81 [438h 1080 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 -[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC] -[43Dh 1085 1] Length : 08 -[43Eh 1086 1] Processor ID : 82 -[43Fh 1087 1] Local Apic ID : 82 -[440h 1088 4] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Runtime Online Capable : 0 - -[444h 1092 1] Subtable Type : 00 [Processor Local APIC] -[445h 1093 1] Length : 08 -[446h 1094 1] Processor ID : 83 -[447h 1095 1] Local Apic ID : 83 -[448h 1096 4] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Runtime Online Capable : 0 [snip] - -[964h 2404 1] Subtable Type : 01 [I/O APIC] -[965h 2405 1] Length : 0C -[966h 2406 1] I/O Apic ID : 00 -[967h 2407 1] Reserved : 00 -[968h 2408 4] Address : FEC00000 -[96Ch 2412 4] Interrupt : 00000000 - -[970h 2416 1] Subtable Type : 02 [Interrupt Source Override] -[971h 2417 1] Length : 0A -[972h 2418 1] Bus : 00 -[973h 2419 1] Source : 00 -[974h 2420 4] Interrupt : 00000002 -[978h 2424 2] Flags (decoded below) : 0000 +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082 + +[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC] +[44Dh 1101 1] Length : 10 +[44Eh 1102 2] Reserved : 0000 +[450h 1104 4] Processor x2Apic ID : 00000101 +[454h 1108 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[458h 1112 4] Processor UID : 00000083 + [snip] + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override] -[97Bh 2427 1] Length : 0A -[97Ch 2428 1] Bus : 00 -[97Dh 2429 1] Source : 05 -[97Eh 2430 4] Interrupt : 00000005 -[982h 2434 2] Flags (decoded below) : 000D +[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override] +[C73h 3187 1] Length : 0A +[C74h 3188 1] Bus : 00 +[C75h 3189 1] Source : 05 +[C76h 3190 4] Interrupt : 00000005 +[C7Ah 3194 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[984h 2436 1] Subtable Type : 02 [Interrupt Source Override] -[985h 2437 1] Length : 0A -[986h 2438 1] Bus : 00 -[987h 2439 1] Source : 09 -[988h 2440 4] Interrupt : 00000009 -[98Ch 2444 2] Flags (decoded below) : 000D +[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override] +[C7Dh 3197 1] Length : 0A +[C7Eh 3198 1] Bus : 00 +[C7Fh 3199 1] Source : 09 +[C80h 3200 4] Interrupt : 00000009 +[C84h 3204 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override] -[98Fh 2447 1] Length : 0A -[990h 2448 1] Bus : 00 -[991h 2449 1] Source : 0A -[992h 2450 4] Interrupt : 0000000A -[996h 2454 2] Flags (decoded below) : 000D +[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override] +[C87h 3207 1] Length : 0A +[C88h 3208 1] Bus : 00 +[C89h 3209 1] Source : 0A +[C8Ah 3210 4] Interrupt : 0000000A +[C8Eh 3214 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[998h 2456 1] Subtable Type : 02 [Interrupt Source Override] -[999h 2457 1] Length : 0A -[99Ah 2458 1] Bus : 00 -[99Bh 2459 1] Source : 0B -[99Ch 2460 4] Interrupt : 0000000B -[9A0h 2464 2] Flags (decoded below) : 000D +[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI] -[9A3h 2467 1] Length : 0C -[9A4h 2468 2] Flags (decoded below) : 0000 +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[9A6h 2470 4] Processor UID : FFFFFFFF -[9AAh 2474 1] Interrupt Input LINT : 01 -[9ABh 2475 3] Reserved : 000000 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000 ... DSDT: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023 + * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023 * * Original Table Header: * Signature "DSDT" - * Length 0x00007EEF (32495) + * Length 0x000083EA (33770) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x52 + * Checksum 0x01 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -4196,107 +4196,32 @@ } If ((Arg0 == 0x0101)) { Notify (C101, Arg1) } If ((Arg0 == 0x0102)) { Notify (C102, Arg1) } If ((Arg0 == 0x0103)) { Notify (C103, Arg1) } - - If ((Arg0 == 0x0104)) - { - Notify (C104, Arg1) - } - - If ((Arg0 == 0x0105)) - { - Notify (C105, Arg1) - } - - If ((Arg0 == 0x0106)) - { - Notify (C106, Arg1) - } - [snip] - If ((Arg0 == 0x0112)) - { - Notify (C112, Arg1) - } } Method (CSTA, 1, Serialized) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) \_SB.PCI0.PRES.CSEL = Arg0 Local0 = Zero If ((\_SB.PCI0.PRES.CPEN == One)) { Local0 = 0x0F } Release (\_SB.PCI0.PRES.CPLK) Return (Local0) } @@ -4306,33 +4231,33 @@ \_SB.PCI0.PRES.CSEL = Arg0 \_SB.PCI0.PRES.CEJ0 = One Release (\_SB.PCI0.PRES.CPLK) } Method (CSCN, 0, Serialized) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) Name (CNEW, Package (0xFF) {}) Local3 = Zero Local4 = One While ((Local4 == One)) { Local4 = Zero Local0 = One Local1 = Zero - While (((Local0 == One) && (Local3 < 0x0113))) + While (((Local0 == One) && (Local3 < 0x0104))) { Local0 = Zero \_SB.PCI0.PRES.CSEL = Local3 \_SB.PCI0.PRES.CCMD = Zero If ((\_SB.PCI0.PRES.CDAT < Local3)) { Break } If ((Local1 == 0xFF)) { Local4 = One Break } Local3 = \_SB.PCI0.PRES.CDAT @@ -7220,3281 +7145,3281 @@ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry { 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x81) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x81, Arg0, Arg1, Arg2) } } - Processor (C082, 0x82, 0x00000000, 0x00) + Device (C082) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x82) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x82)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x82) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x82, Arg0, Arg1, Arg2) } } - Processor (C083, 0x83, 0x00000000, 0x00) + Device (C083) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x83) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x83)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x83) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x83, Arg0, Arg1, Arg2) } } - Processor (C084, 0x84, 0x00000000, 0x00) + Device (C084) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x84) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x84)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x84) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x84, Arg0, Arg1, Arg2) } } [snip] - Processor (C0FE, 0xFE, 0x00000000, 0x00) + Device (C0FE) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0xFE) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0xFE)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|... + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0xFE) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0xFE, Arg0, Arg1, Arg2) } } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-11-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Extend smbios core count2 test to cover general ↵Zhao Liu1-2/+4
topology The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed the miscalculation of cores per socket. The original core count2 test (with the topology configured by "-smp 275") didn't recognize that topology-related but because it just created a special topology with only one socket and one die by default, ignoring the effect of more topology levels (between socket and core) on the cores per socket calculation. So for the topology in this case, there're the following considerations: 1. cores per socket should be more than 255 to ensure we could cover the core count2 field. 2. The original bug was that cores per socket was miscalculated, so now we should include as many topology levels as possible (multiple sockets or dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the cores per socket encoded in the core count2 field is correct. Based on these considerations, select the topology with multiple dies: -smp 260,dies=2,cores=130,threads=1 Note, here we doesn't configure multiple sockets to avoid the error ("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user uses the default ulimit seeting on his machine. And the cores per socket calculation for multiple sockets has already been covered by the core count test case, so that only multiple dies configuration is enough. The expected core count2 = cores per socket = cores (130) * dies (2) = 260. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-10-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core ↵Zhao Liu1-0/+2
count2 test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be changed about the type 4 core count2 test case. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-9-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count ↵Zhao Liu4-3/+0
test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 3C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } [snip] + If ((Arg0 == 0x35)) + { + Notify (C035, Arg1) + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-8-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 core countZhao Liu1-0/+19
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of cores in the socket is not more than 255, then smbios type4 table encodes cores per socket into the core count field. So for the topology in this case, there're the following considerations: 1. cores per socket should be not more than 255 to ensure we could cover the core count field. 2. The original bug was that cores per socket was miscalculated, so now we should include as many topology levels as possible (mutiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the cores per socket encoded in the core count field is correct. Based on these considerations, select the topology with multiple sockets and dies: -smp 54,sockets=2,dies=3,cores=3,threads=3 The expected core count = cores per socket = cores (3) * dies (3) = 9. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-7-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core ↵Zhao Liu4-0/+3
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 core count field. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 count testZhao Liu4-3/+0
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000430 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : C5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC] +[3E5h 0997 1] Length : 08 +[3E6h 0998 1] Processor ID : 77 +[3E7h 0999 1] Local Apic ID : 9E +[3E8h 1000 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[3ECh 1004 1] Subtable Type : 01 [I/O APIC] +[3EDh 1005 1] Length : 0C +[3EEh 1006 1] I/O Apic ID : 00 +[3EFh 1007 1] Reserved : 00 +[3F0h 1008 4] Address : FEC00000 +[3F4h 1012 4] Interrupt : 00000000 + +[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override] +[3F9h 1017 1] Length : 0A +[3FAh 1018 1] Bus : 00 +[3FBh 1019 1] Source : 00 +[3FCh 1020 4] Interrupt : 00000002 +[400h 1024 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[402h 1026 1] Subtable Type : 02 [Interrupt Source Override] +[403h 1027 1] Length : 0A +[404h 1028 1] Bus : 00 +[405h 1029 1] Source : 05 +[406h 1030 4] Interrupt : 00000005 +[40Ah 1034 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override] +[40Dh 1037 1] Length : 0A +[40Eh 1038 1] Bus : 00 +[40Fh 1039 1] Source : 09 +[410h 1040 4] Interrupt : 00000009 +[414h 1044 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[416h 1046 1] Subtable Type : 02 [Interrupt Source Override] +[417h 1047 1] Length : 0A +[418h 1048 1] Bus : 00 +[419h 1049 1] Source : 0A +[41Ah 1050 4] Interrupt : 0000000A +[41Eh 1054 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[420h 1056 1] Subtable Type : 02 [Interrupt Source Override] +[421h 1057 1] Length : 0A +[422h 1058 1] Bus : 00 +[423h 1059 1] Source : 0B +[424h 1060 4] Interrupt : 0000000B +[428h 1064 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI] +[42Bh 1067 1] Length : 06 +[42Ch 1068 1] Processor ID : FF +[42Dh 1069 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[42Fh 1071 1] Interrupt Input LINT : 01 + ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000489D (18589) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xDB + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + [snip] + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C077, 0x77, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x77)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w..... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x77) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x77, Arg0, Arg1, Arg2) + } + } + } + } + ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 countZhao Liu1-1/+32
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets calculation"). In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built for each socket, so the count of type4 tables should be equal to the number of sockets. Thus for the topology in this case, there're the following considerations: 1. The topology should include multiple sockets to ensure smbios could create type4 tables for each socket. 2. In addition to sockets, for the more general topology, we should also configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it), to ensure that smbios is able to exclude the effect of other topology levels to create the type4 tables only for sockets. 3. The original miscalculation bug also misused "smp.cpus", so it's necessary to configure "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) as well to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of the count of type4 tables. Based on these considerations, select the topology as the follow: -smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3 The expected count of type4 tables = sockets (5). Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-4-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu4-0/+3
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 count. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-3-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: test-smp-parse: Add the test for cores/threads per socket helpersZhao Liu1-13/+54
Use the different ways to calculate cores/threads per socket, so that the new CPU topology levels won't be missed in these 2 helpes: * machine_topo_get_cores_per_socket() * machine_topo_get_threads_per_socket() Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/ threads per socket"). Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-2-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vdpa: Allow VIRTIO_NET_F_RSS in SVQHawkins Jiawei1-0/+1
Enable SVQ with VIRTIO_NET_F_RSS feature. Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <626449eb303207de408126b3dc7c155cd72b028b.1698195059.git.yin31149@gmail.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vdpa: Restore receive-side scaling stateHawkins Jiawei1-23/+44
This patch reuses vhost_vdpa_net_load_rss() with some refactorings to restore the receive-side scaling state at device's startup. Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <cf5b78a16ed0318982ceffb195f2227f6aad4ac1.1698195059.git.yin31149@gmail.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vdpa: Add SetSteeringEBPF method for NetClientStateHawkins Jiawei1-0/+8
At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must be loaded for the vhost backend. Given that vhost-vdpa is one of the vhost backend, we need to implement the SetSteeringEBPF method to support RSS for vhost-vdpa, even if vhost-vdpa calculates the rss hash in the hardware device instead of in the kernel by eBPF. Although this requires QEMU to be compiled with `--enable-bpf` configuration even if the vdpa device does not use eBPF to calculate the rss hash, this can avoid adding the specific conditional statements for vDPA case to enable the VIRTIO_NET_F_RSS feature, which reduces code maintainbility. Suggested-by: Eugenio Pérez <eperezma@redhat.com> Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <280e20ddce55b6de60f1552ba0865bffffe909b2.1698195059.git.yin31149@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQHawkins Jiawei1-0/+1
Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature. Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <d66b0aee501cdad7954231900c35a11cad1e13db.1698194366.git.yin31149@gmail.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vdpa: Restore hash calculation stateHawkins Jiawei1-0/+91
This patch introduces vhost_vdpa_net_load_rss() to restore the hash calculation state at device's startup. Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <dbf699acff8c226596136a55a6abe35ebfeac8b0.1698194366.git.yin31149@gmail.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07docs/system: add basic virtio-snd documentationManos Pitsidianakis3-0/+51
This commit adds basic documentation for using virtio-snd. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <e7fb941cf7636fdff40cbdcdcd660dec5f15ca3c.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: implement audio capture (RX)Manos Pitsidianakis2-35/+230
To perform audio capture we duplicate the TX logic of the previous commit with the following difference: we receive data from the QEMU audio backend and write it in the virt queue IO buffers the guest sends to QEMU. When they are full (i.e. they have `period_bytes` amount of data) or when recording stops in QEMU's audio backend, the buffer is returned to the guest by notifying it. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <e56a17741a24ccadfbbea19d3c60c9406b795b23.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: implement audio output (TX)Manos Pitsidianakis3-5/+332
Handle output IO messages in the transmit (TX) virtqueue. It allocates a VirtIOSoundPCMBuffer for each IO message and copies the data buffer to it. When the IO buffer is written to the host's sound card, the guest will be notified that it has been consumed. The lifetime of an IO message is: 1. Guest sends IO message to TX virtqueue. 2. QEMU adds it to the appropriate stream's IO buffer queue. 3. Sometime later, the host audio backend calls the output callback, virtio_snd_pcm_out_cb(), which is defined with an AUD_open_out() call. The callback gets an available number of bytes the backend can receive. Then it writes data from the IO buffer queue to the backend. If at any time a buffer is exhausted, it is returned to the guest as completed. 4. If the guest releases the stream, its buffer queue is flushed by attempting to write any leftover data to the audio backend and releasing all IO messages back to the guest. This is how according to the spec the guest knows the release was successful. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <b7c6fc458c763d09a4abbcb620ae9b220afa5b8f.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: handle VIRTIO_SND_R_PCM_RELEASEManos Pitsidianakis2-1/+48
Handle the PCM release control request, which is necessary for flushing pending sound IO. No IO is handled yet so currently it only replies to the request. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <ae0afa16461429df1a2f268313d5bfcca27479ec.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: handle VIRTIO_SND_R_PCM_PREPAREManos Pitsidianakis1-0/+24
Handles the PCM prepare control request. It initializes a PCM stream when the guests asks for it. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <c6a9c437ef48e45f083fc957dcf7fe18a028e657.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: handle VIRTIO_SND_R_PCM_SET_PARAMSManos Pitsidianakis2-0/+35
Handle the set parameters control request. It reconfigures a stream based on a guest's preference if the values are valid and supported. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <d0d19928691f9375bfd83388806786cb7b161301.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: handle VIRTIO_SND_R_PCM_{START,STOP}Manos Pitsidianakis2-2/+48
Handle the start and stop control messages for a stream_id. This request does nothing at the moment except for replying to it. Audio playback or capture will be started/stopped here in follow-up commits. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <9657dbfe3cb4a48ceb033ceb5977dc08669dfefd.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: handle VIRTIO_SND_R_PCM_INFO requestManos Pitsidianakis2-0/+83
Respond to the VIRTIO_SND_R_PCM_INFO control request with the parameters of each requested PCM stream. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <5ecea6ba2fb0e3957d7d90bc4dbac521a3d1f678.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07virtio-sound: handle control messages and streamsManos Pitsidianakis3-9/+595
Receive guest requests in the control (CTRL) queue of the virtio sound device and reply with a NOT SUPPORTED error to all control commands. The receiving handler is virtio_snd_handle_ctrl(). It stores all control messages in the queue in the device's command queue. Then it calls virtio_snd_process_cmdq() to handle each message. The handler is process_cmd() which replies with VIRTIO_SND_S_NOT_SUPP. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <3224aff87e7c4f2777bfe1bbbbca93b72525992c.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07Add virtio-sound-pci deviceManos Pitsidianakis4-0/+96
This patch adds a PCI wrapper device for the virtio-sound device. It is necessary to instantiate a virtio-snd device in a guest. All sound logic will be added to the virtio-snd device in the following commits. To add this device with a guest, you'll need a >=5.13 kernel compiled with CONFIG_SND_VIRTIO=y, which at the time of writing most distros have off by default. Use with following flags in the invocation: Pulseaudio: -audio driver=pa,model=virtio or -audio driver=pa,model=virtio,server=/run/user/1000/pulse/native sdl: -audio driver=sdl,model=virtio coreaudio (macos/darwin): -audio driver=coreaudio,model=virtio etc. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <b223598d59f56ead6a6d8d9bb6801e17489ddaa4.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07Add virtio-sound device stubManos Pitsidianakis7-0/+335
Add a new VIRTIO device for the virtio sound device id. Functionality will be added in the following commits. Based-on: https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471 Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com> Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <f9678a41fe97b5886c1b04795f1be046509de866.1698062525.git.manos.pitsidianakis@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost-user-fs: Implement internal migrationHanna Czenczek1-1/+100
A virtio-fs device's VM state consists of: - the virtio device (vring) state (VMSTATE_VIRTIO_DEVICE) - the back-end's (virtiofsd's) internal state We get/set the latter via the new vhost operations to transfer migratory state. It is its own dedicated subsection, so that for external migration, it can be disabled. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-8-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost: Add high-level state save/load functionsHanna Czenczek2-0/+239
vhost_save_backend_state() and vhost_load_backend_state() can be used by vhost front-ends to easily save and load the back-end's state to/from the migration stream. Because we do not know the full state size ahead of time, vhost_save_backend_state() simply reads the data in 1 MB chunks, and writes each chunk consecutively into the migration stream, prefixed by its length. EOF is indicated by a 0-length chunk. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-7-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost-user: Interface for migration state transferHanna Czenczek5-0/+286
Add the interface for transferring the back-end's state during migration as defined previously in vhost-user.rst. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-6-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost-user.rst: Migrating back-end-internal stateHanna Czenczek1-0/+172
For vhost-user devices, qemu can migrate the virtio state, but not the back-end's internal state. To do so, we need to be able to transfer this internal state between front-end (qemu) and back-end. At this point, this new feature is added for the purpose of virtio-fs migration. Because virtiofsd's internal state will not be too large, we believe it is best to transfer it as a single binary blob after the streaming phase. These are the additions to the protocol: - New vhost-user protocol feature VHOST_USER_PROTOCOL_F_DEVICE_STATE - SET_DEVICE_STATE_FD function: Front-end and back-end negotiate a file descriptor over which to transfer the state. - CHECK_DEVICE_STATE: After the state has been transferred through the file descriptor, the front-end invokes this function to verify success. There is no in-band way (through the file descriptor) to indicate failure, so we need to check explicitly. Once the transfer FD has been established via SET_DEVICE_STATE_FD (which includes establishing the direction of transfer and migration phase), the sending side writes its data into it, and the reading side reads it until it sees an EOF. Then, the front-end will check for success via CHECK_DEVICE_STATE, which on the destination side includes checking for integrity (i.e. errors during deserialization). Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-5-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost-user.rst: Introduce suspended stateHanna Czenczek1-1/+19
In vDPA, GET_VRING_BASE does not stop the queried vring, which is why SUSPEND was introduced so that the returned index would be stable. In vhost-user, it does stop the vring, so under the same reasoning, it can get away without SUSPEND. Still, we do want to clarify that if the device is completely stopped, i.e. all vrings are stopped, the back-end should cease to modify any state relating to the guest. Do this by calling it "suspended". Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-4-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost-user.rst: Clarify enabling/disabling vringsHanna Czenczek1-15/+17
Currently, the vhost-user documentation says that rings are to be initialized in a disabled state when VHOST_USER_F_PROTOCOL_FEATURES is negotiated. However, by the time of feature negotiation, all rings have already been initialized, so it is not entirely clear what this means. At least the vhost-user-backend Rust crate's implementation interpreted it to mean that whenever this feature is negotiated, all rings are to put into a disabled state, which means that every SET_FEATURES call would disable all rings, effectively halting the device. This is problematic because the VHOST_F_LOG_ALL feature is also set or cleared this way, which happens during migration. Doing so should not halt the device. Other implementations have interpreted this to mean that the device is to be initialized with all rings disabled, and a subsequent SET_FEATURES call that does not set VHOST_USER_F_PROTOCOL_FEATURES will enable all of them. Here, SET_FEATURES will never disable any ring. This interpretation does not suffer the problem of unintentionally halting the device whenever features are set or cleared, so it seems better and more reasonable. We can clarify this in the documentation by making it explicit that the enabled/disabled state is tracked even while the vring is stopped. Every vring is initialized in a disabled state, and SET_FEATURES without VHOST_USER_F_PROTOCOL_FEATURES simply becomes one way to enable all vrings. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-3-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07vhost-user.rst: Improve [GS]ET_VRING_BASE docHanna Czenczek1-4/+73
GET_VRING_BASE does not mention that it stops the respective ring. Fix that. Furthermore, it is not fully clear what the "base offset" these commands' documentation refers to is; an offset could be many things. Be more precise and verbose about it, especially given that these commands use different payload structures depending on whether the vring is split or packed. Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20231016134243.68248-2-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-06Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi15-1381/+764
target/sparc: Explicitly compute condition codes # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVH9oodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/M8QgAgPTp/wFLVnSRFLaN # fBoelVhM4WTWMQ+SUwZMtCvqcMHaBxIMu+hyk5MI11hFOUi9N+vWvRb+NZ6JbK+1 # sqWcx0NdYfNdOeoi1dgzGgcCkFA8u9zW/K7Ih0W8WuU20uiJ4Zw/qmnEELIl/mZR # 5Ft1mhLMhQSYsH0KSypugLWBxR9SFNH1cV3C1SG2q+6snm/mhKk9NN18zJGFdmmY # 4CQThx159P/DaPUONZbSAMN94opu6K8FSymELPDUZBYwJRq7fyGKYuDUGRvN1kxx # I8p/MF1V5Vcth9lvGyBYulFWjo9BDMpkIdmWzXZLOWfzZVAed8PcglxoQqgMbU5u # eyY/Cw== # =Tv1h # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Nov 2023 04:09:46 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu: (21 commits) target/sparc: Check for invalid cond in gen_compare_reg target/sparc: Implement UDIV inline target/sparc: Implement UDIVX and SDIVX inline target/sparc: Discard cpu_cond at the end of each insn target/sparc: Record entire jump condition in DisasContext target/sparc: Merge gen_op_next_insn into only caller target/sparc: Pass displacement to advance_jump_cond target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond target/sparc: Merge gen_branch2 into advance_pc target/sparc: Do flush_cond in advance_jump_cond target/sparc: Always copy conditions into a new temporary target/sparc: Change DisasCompare.c2 to int target/sparc: Remove DisasCompare.is_bool target/sparc: Remove CC_OP leftovers target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD target/sparc: Remove CC_OP_DIV target/sparc: Remove CC_OP_LOGIC target/sparc: Split psr and xcc into components ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06Merge tag 'migration-20231103-pull-request' of ↵Stefan Hajnoczi10-70/+398
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request (20231103) Hi In this PULL: - dirty limit fixes (hyman) - coverity issues (juan) Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmVE4dgACgkQ9IfvGFhy # 1yPBgxAAvrsCHwU6/m9y+XGokyHTKKKIVysLip/14jAjDL+viLYgxdVyOGQKQGBa # +yV+XHTaEyKdihKG4Z5nWuC0yM+sdZQpWXQAcHJLPaPs5wDGICICpdAFY2LbAWSK # jtX9uq7crywIL4mVKiX+HOjRUPCAYUx/2TcqJf2+0+MKDEVC33ikxNbcx8ZELY+Q # +hGyOws3mkHSQjyaNUVgnnQtGzikYqcNO2efa+zVPdXYd+TUWW2e9I++Qf48r0Hv # OqeZAB7bSAb39PNRuj0I1gt4d3WTHzHt7BSpX1OuFqQnzLw8vS5iDQH943WAyGkY # NblZVb8pyzSg1Jy18H/SmrJDXeufRwqFwD+1NHyxGjsF89KOuVUqGrGpRXhMBtmA # DSzdgn5jqW5lI1po9FqGdlPTFlhstpMH3DSfPQWurvJh42oM38gmSEHLBNpc4tXo # 8udMYI09H/kHUoNMTZNGjnZO9LfarGsag6eOJP1bMMublhRlKCaL9RIyV9oOHycE # IeOeQFeBP/BmYFLWbVPeZej7uiqsEc7VPDJK2QXns210UYanaWmggkmpdAr0I0EV # pEKHSfVv1qlIlFH4d7MhcJzP2/rY62EC5tYQjT0UaBnCRcDInKrNWa3kbDL0akwr # 0aJgpbT5ipknVChtwnMWJlbqpeW/VUF5g0jVpYQ3jbe/Zf+OtmU= # =Pv8z # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Nov 2023 20:04:40 HKT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quintela/qemu: migration: Unlock mutex in error case docs/migration: Add the dirty limit section tests/migration: Introduce dirty-limit into guestperf tests/migration: Introduce dirty-ring-size option into guestperf tests: Add migration dirty-limit capability test system/dirtylimit: Drop the reduplicative check system/dirtylimit: Fix a race situation Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu ↵Stefan Hajnoczi5-81/+134
into staging dump queue Hi The "dump" queue, with: - [PATCH v3 qemu 0/3] Allow dump-guest-memory to output standard kdump format - [PATCH v2 0/5] dump: Minor fixes & improvements # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmVEmsEcHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5YNkD/sFnz+I75mn6+DIdC3x # aSVUU87JxAvWkt+G3KYGS+de2+g2YkRkPwwrIsIceiX7mlL4Es350AVcTl7+fXpu # Jl9k9I32QI+U3pNXo9BStIqjKUMBxmmKs4aLCh9OHJ6oliTCG+aJTUmSl/dABIuw # fAcW9vjhyR4ogAp8x7WhR6PKEAAb6OE/9k0w/z0GV2K09N/R0pPAvObQ36VQJ/Cl # 6DN8tRRytl0IQmC/mZZ+MQPQ5cvamK78X3DmnYCGtyN9HTQERfUFMSSgD/sHLvNi # rMKuwhXiGQfDs/xQ9Z6Vh2AL7JfAwbIQwUstepb78M/5GBLaZfwFYG4+eCohJE82 # s0GOQ45Yks+AOTGj6lNyOfJ8PIf0SocCTbnLWZicpdHIfoEkSmmL0VZ5w+w0EpDO # WOZJRpANJGTLhKNb//X3A3OJ05LoavN3/criokhC19DW/yE/VEGd3dXlP6yvFOku # vGUINGivg1bw7yO0S/rzXNw4+cHCPgBCXbKCNuMI6B+dxL5pUR5Zr4OqcYgwejqE # RWMdqsHA4ohpzc3AfbuHLFilXJNAgLR3jAEiVUXyrz9U1FiYEiq/8RNuupe9Uveq # pO1PDZ9fher0Zda4y28bHl/e5M9hVeCFqElcVk0FQGt97T5olVvSaL/hFUPf65ls # 8A3lN6WaAT9dvM33pkeswZvGxg== # =eSbp # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Nov 2023 15:01:21 HKT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu: dump: Drop redundant check for empty dump dump: Improve some dump-guest-memory error messages dump: Recognize "fd:" protocols on Windows hosts dump: Fix g_array_unref(NULL) in dump-guest-memory dump: Rename qmp_dump_guest_memory() parameter to match QAPI schema dump: Add command interface for kdump-raw formats dump: Allow directly outputting raw kdump format dump: Pass DumpState to write_ functions Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06Merge tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu into ↵Stefan Hajnoczi9-52/+318
staging pull-loongarch-20231103 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZUSQIgAKCRBAov/yOSY+ # 31aIBADj5FzdUxyFB813SouAiEiyMdI4bN98AunomAk3Kt8PF1XPoP8kPzcjxcMI # kCW4eoHb12MVs9OclkqFY3VyaxtSD3YSG/h8W9YxaDyU+L/q89RS+J4r6CAZ8ylg # J4uxs3Lv8nwPEvRb4zITAt8JQllLey1100j/uu4fU0Rx7vUcMA== # =9RMx # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Nov 2023 14:16:02 HKT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu: linux-user/loongarch64: Add LASX sigcontext save/restore linux-user/loongarch64: Add LSX sigcontext save/restore linux-user/loongarch64: Use abi_{ulong,uint} types linux-user/loongarch64: setup_sigframe() set 'end' context size 0 linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context size linux-user/loongarch64: Use traps to track LSX/LASX usage target/loongarch: Support 4K page size target/loongarch: Implement query-cpu-model-expansion target/loongarch: Allow user enable/disable LSX/LASX features target/loongarch: Add cpu model 'max' Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-05target/sparc: Check for invalid cond in gen_compare_regRichard Henderson1-19/+26
Consolidate the test here; drop the "inverted logic". Fix MOVr and FMOVR, which were missing the invalid test. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Implement UDIV inlineRichard Henderson2-14/+56
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Implement UDIVX and SDIVX inlineRichard Henderson4-44/+97
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Discard cpu_cond at the end of each insnRichard Henderson1-0/+27
If the insn raises no exceptions, there will be no path in which cpu_cond is used, and so the computation may be optimized away. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Record entire jump condition in DisasContextRichard Henderson1-11/+16
Use the original condition instead of consuming cpu_cond, which will now only be live along exception paths. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-02-05 17:13:40 +0000