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2018-10-26tests/vm: Add a BaseVM::arch propertyPhilippe Mathieu-Daudé6-1/+8
The 'arch' property gives a hint on which architecture the guest image runs. This can be use to select the correct QEMU binary path. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-6-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Display remaining seconds to wait for a VM to startPhilippe Mathieu-Daudé1-1/+4
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Do not use the -smp option with a single cpuPhilippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Do not abuse parallelism when KVM is not availablePhilippe Mathieu-Daudé1-1/+8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests/vm: Extract the kvm_available() handy functionPhilippe Mathieu-Daudé2-2/+6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20181013004034.6968-2-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-26tests: docker: update test-mingw for GTK+ 2.0 removalPaolo Bonzini1-2/+1
--with-gtkabi does not exist anymore; remove it from the configure invocation. Fixes: 89d85cde75143325205e332dd97bf1bb8402d7c1 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1539886203-33670-1-git-send-email-pbonzini@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-10-25Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' ↵Peter Maydell11-372/+438
into staging First RISC-V Patch Set for the 3.1 Soft Freeze This pull request contains a handful of patches that have been floating around various trees for a while but haven't made it upstream. These patches all appear quite safe. They're all somewhat independent from each other: * One refactors our IRQ management function to allow multiple interrupts to be raised an once. This patch has no functional difference. * Cleaning up the op_helper/cpu_helper split. This patch has no functional difference. * Updates to various constants to keep them in sync with the latest ISA specification and to remove some non-standard bits that snuck in. * A fix for a memory leak in the PLIC driver. * A fix to our device tree handling to avoid provinging a NULL string. I've given this my standard test: building the port, booting a Fedora root filesytem on the latest Linux tag, and then shutting down that image. Essentially I'm just following the QEMU RISC-V wiki page's instructions. Everything looks fine here. We have a lot more outstanding patches so I'll definately be submitting another PR for the soft freeze. # gpg: Signature made Wed 17 Oct 2018 21:17:52 BST # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/riscv/tags/riscv-for-master-3.1-sf0: RISC-V: Don't add NULL bootargs to device-tree RISC-V: Add missing free for plic_hart_config RISC-V: Update CSR and interrupt definitions RISC-V: Move non-ops from op_helper to cpu_helper RISC-V: Allow setting and clearing multiple irqs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24Merge remote-tracking branch ↵Peter Maydell3-173/+402
'remotes/berrange/tags/qcrypto-next-pull-request' into staging Improve performance of XTS cipher mode impl The XTS cipher mode performance is approximately doubled and test coverage is improved. # gpg: Signature made Wed 24 Oct 2018 19:05:08 BST # gpg: using RSA key BE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qcrypto-next-pull-request: crypto: add testing for unaligned buffers with XTS cipher mode crypto: refactor XTS cipher mode test suite crypto: annotate xts_tweak_encdec as inlineable crypto: convert xts_mult_x to use xts_uint128 type crypto: convert xts_tweak_encdec to use xts_uint128 type crypto: introduce a xts_uint128 data type crypto: remove code duplication in tweak encrypt/decrypt crypto: expand algorithm coverage for cipher benchmark Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24crypto: add testing for unaligned buffers with XTS cipher modeDaniel P. Berrangé1-0/+86
Validate that the XTS cipher mode will correctly operate with plain text, cipher text and IV buffers that are not 64-bit aligned. Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: refactor XTS cipher mode test suiteDaniel P. Berrangé1-60/+80
The current XTS test overloads two different tests in a single function making the code a little hard to follow. Split it into distinct test cases. Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: annotate xts_tweak_encdec as inlineableDaniel P. Berrangé1-5/+5
Encouraging the compiler to inline xts_tweak_encdec increases the performance for xts-aes-128 when built with gcrypt: Encrypt: 545 MB/s -> 580 MB/s Decrypt: 568 MB/s -> 602 MB/s Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: convert xts_mult_x to use xts_uint128 typeDaniel P. Berrangé1-12/+28
Using 64-bit arithmetic increases the performance for xts-aes-128 when built with gcrypt: Encrypt: 355 MB/s -> 545 MB/s Decrypt: 362 MB/s -> 568 MB/s Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: convert xts_tweak_encdec to use xts_uint128 typeDaniel P. Berrangé1-26/+58
Using 64-bit arithmetic increases the performance for xts-aes-128 when built with gcrypt: Encrypt: 272 MB/s -> 355 MB/s Decrypt: 275 MB/s -> 362 MB/s Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: introduce a xts_uint128 data typeDaniel P. Berrangé1-20/+26
The new type is designed to allow use of 64-bit arithmetic instead of operating 1-byte at a time. The following patches will use this to improve performance. Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: remove code duplication in tweak encrypt/decryptDaniel P. Berrangé1-49/+15
The tweak encrypt/decrypt functions are identical except for the comments, so can be merged. Profiling data shows that the compiler is in fact already merging the two merges in the object files. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24crypto: expand algorithm coverage for cipher benchmarkDaniel P. Berrangé1-23/+126
Add testing coverage for AES with XTS, ECB and CTR modes Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-10-24Merge remote-tracking branch ↵Peter Maydell11-19/+1281
'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging MIPS queue for October 2018 - part 2 - v2 # gpg: Signature made Wed 24 Oct 2018 14:22:54 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits) target/mips: Fix decoding of ALIGN and DALIGN instructions target/mips: Fix the title of translate.c linux-user/mips: Recognize the R5900 CPU model target/mips: Define the R5900 CPU tests/tcg/mips: Add tests for R5900 DIVU1 tests/tcg/mips: Add tests for R5900 DIV1 tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1 tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1 tests/tcg/mips: Add tests for R5900 three-operand MULTU1 tests/tcg/mips: Add tests for R5900 three-operand MULT1 tests/tcg/mips: Add tests for R5900 three-operand MULTU tests/tcg/mips: Add tests for R5900 three-operand MULT target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV target/mips: Support R5900 DIV1 and DIVU1 instructions target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions target/mips: Support R5900 three-operand MULT and MULTU instructions target/mips: Add a placeholder for R5900 MMI3 instruction subclass target/mips: Add a placeholder for R5900 MMI2 instruction subclass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24Merge remote-tracking branch ↵Peter Maydell8-9/+33
'remotes/huth-gitlab/tags/pull-request-2018-10-24' into staging - Disable migration-test with TCG on s390x (since there are known problems) - Small Makefile improvements - More modern shell scripting changes (use $() instead of ``) - Add a configure option to disable AVX2 # gpg: Signature made Wed 24 Oct 2018 08:04:33 BST # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" # gpg: aka "Thomas Huth <thuth@redhat.com>" # gpg: aka "Thomas Huth <huth@tuxfamily.org>" # gpg: aka "Thomas Huth <th.huth@posteo.de>" # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2018-10-24: configure: Provide option to explicitly disable AVX2 po/Makefile: Modern shell scripting (use $() instead of ``) debian-bootstrap.pre: Modern shell scripting (use $() instead of ``) configs: Add a CONFIG_SMC37C669 switch for the "smc37c669-superio" device hw/core: Move null-machine into the common-obj list tests/migration-test: Disable s390x test when running with TCG Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24target/mips: Fix decoding of ALIGN and DALIGN instructionsAleksandar Markovic1-8/+32
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to allow paremeter 'bp' to occupy two and three bits, respectively. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Fix the title of translate.cAleksandar Markovic1-1/+1
Replace MIPS32 with MIPS, since the file covers all generations of MIPS architectures. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24linux-user/mips: Recognize the R5900 CPU modelFredrik Noring1-0/+3
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU. The R5900 FPU hardware is noncompliant and it is therefore emulated in software by the Linux kernel. QEMU emulates a compliant FPU accordingly. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define the R5900 CPUFredrik Noring1-0/+59
The primary purpose of this change is to support programs compiled by GCC for the R5900 target and thereby run R5900 Linux distributions, for example Gentoo. GCC in version 7.3, by itself, by inspection of the GCC source code and inspection of the generated machine code, for the R5900 target, only emits two instructions that are specific to the R5900: the three- operand MULT and MULTU. GCC and libc also emit certain MIPS III instructions that are not part of the R5900 ISA. They are normally trapped and emulated by the Linux kernel, and therefore need to be treated accordingly by QEMU. A program compiled by GCC is taken to mean source code compiled by GCC under the restrictions above. One can, with the apparent limitations, with a bit of effort obtain a fully functioning operating system such as R5900 Gentoo. Strictly speaking, programs need not be compiled by GCC to make use of this change. Instructions and other facilities of the R5900 not implemented by this change are intended to signal provisional exceptions. One such example is the FPU that is not compliant with IEEE 754-1985 in system mode. It is therefore provisionally disabled. In user space the FPU is trapped and emulated by IEEE 754-1985 compliant software in the kernel, and this is handled accordingly by QEMU. Another example is the 93 multimedia instructions specific to the R5900 that generate provisional reserved instruction exception signals. One of the benefits of running a Linux distribution under QEMU is that programs can be compiled with a native compiler, where the host and target are the same, as opposed to a cross-compiler, where they are not the same. This is especially important in cases where the target hardware does not have the resources to run a native compiler. Problems with cross-compilation are often related to host and target differences in integer sizes, pointer sizes, endianness, machine code, ABI, etc. Sometimes cross-compilation is not even supported by the build script for a given package. One effective way to avoid those problems is to replace the cross-compiler with a native compiler. This change of compilation methods does not resolve the inherent problems with cross-compilation. The native compiler naturally replaces the cross-compiler, because one typically uses one or the other, and preferably the native compiler when the circumstances admit this. The native compiler is also a good test case for the R5900 QEMU user mode. Additionally, Gentoo is well- known for compiling and installing its packages from sources. This change has been tested with Gentoo compiled for R5900, including native compilation of several packages under QEMU. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 DIVU1Fredrik Noring2-0/+49
Add a test for DIVU1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 DIV1Fredrik Noring2-1/+75
Add a test for DIV1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1Fredrik Noring2-0/+41
Add a test for MTLO1 and MTHI1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1Fredrik Noring2-1/+37
Add a test for MFLO1 and MFHI1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULTU1Fredrik Noring1-7/+36
Add a test for MULTU1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULT1Fredrik Noring1-8/+37
Add a test for MULT1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULTUFredrik Noring2-0/+40
Add a test for MULTU. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24tests/tcg/mips: Add tests for R5900 three-operand MULTFredrik Noring2-0/+72
Add a test for MULT. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user onlyFredrik Noring1-1/+22
The Linux kernel traps certain reserved instruction exceptions to emulate the corresponding instructions. QEMU plays the role of the kernel in user mode, so those traps are emulated by accepting the instructions. This change adds the function check_insn_opc_user_only to signal a reserved instruction exception for flagged CPUs in QEMU system mode. The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not implemented in R5900 hardware. They are trapped and emulated by the Linux kernel and, accordingly, therefore QEMU user only instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IVFredrik Noring1-2/+3
The R5900 is taken to be MIPS III with certain modifications. From MIPS IV it implements the instructions MOVN, MOVZ and PREF. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 DIV1 and DIVU1 instructionsFredrik Noring1-3/+9
Add support for DIV1 and DIVU1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructionsFredrik Noring1-6/+17
Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 three-operand MULT1 and MULTU1 instructionsFredrik Noring1-3/+14
Add support for MULT1 and MULTU1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 three-operand MULT and MULTU instructionsFredrik Noring1-0/+74
The three-operand MULT and MULTU are the only R5900-specific instructions emitted by GCC 7.3. The R5900 also implements the three- operand MADD and MADDU instructions, but they are omitted in QEMU for now since they are absent in programs compiled by current GCC versions. Likewise, the R5900-specific pipeline 1 instruction variants MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are omitted here as well. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI3 instruction subclassFredrik Noring1-1/+30
Add a placeholder for MMI3 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI2 instruction subclassFredrik Noring1-1/+39
Add a placeholder for MMI2 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI1 instruction subclassFredrik Noring1-1/+35
Add a placeholder for MM1 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI0 instruction subclassFredrik Noring1-1/+42
Add a placeholder for MMI0 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI instruction classFredrik Noring1-1/+44
Add a placeholder for MMI class. This is the main palceholder for MMI ASE. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 LQFredrik Noring1-2/+11
Add a placeholder for LQ instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWRFredrik Noring1-1/+52
Add placeholder for SQ instruction, handle RDHWR. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI3 opcode constantsFredrik Noring1-0/+39
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI2 opcode constantsFredrik Noring1-0/+48
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI1 opcode constantsFredrik Noring1-0/+44
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI0 opcode constantsFredrik Noring1-0/+51
Add definition of MI0 opcodes. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constantsFredrik Noring1-0/+51
Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of instructions in MMI class. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI class, and LQ and SQ opcode constantsFredrik Noring1-0/+40
Define MMI class, LQ, and SQ R5900 opdoces. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add R5900 Multimedia Instruction overview noteFredrik Noring1-0/+161
Add a comment on R5900 MMI ASE (short overview). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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