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2024-11-07target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_usMax Chou1-1/+4
Because the real vl (evl) of vext_ldst_us may be different (e.g. vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function should be replaced by checking evl in vext_ldst_us. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07target/riscv: Set vdata.vm field for vector load/store whole register ↵Max Chou1-0/+3
instructions The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() checkDaniel Henrique Barboza1-1/+1
'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the 'switch' right before it if 'mode' isn't 0, 8, 9 or 10. 'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32. Reported by Coverity via a "DEADCODE" ticket. Resolves: Coverity CID 1564781 Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104123839.533442-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07hw/riscv/riscv-iommu: change 'depth' to intDaniel Henrique Barboza1-1/+1
Coverity reports an unsigned overflow when doing: for (; depth-- > 0; ) { When depth = 0 inside riscv_iommu_ctx_fetch(). Building it with a recent GCC the code doesn't actually break with depth = 0, i.e. the comparison "0-- > 0" will exit the loop instead of proceeding, but 'depth' will retain the overflow value afterwards. This behavior can be compiler dependent, so change 'depth' to int to remove this potential ambiguity. Resolves: Coverity CID 1564783 Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104123839.533442-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07hw/char/sifive_uart: Fix broken UART on big endian hostsThomas Huth1-1/+2
Casting a "uint32_t *" to a "uint8_t *" to get to the lowest 8-bit part of the value does not work on big endian hosts. We've got to take the proper detour through an 8-bit variable. Fixes: 53c1557b23 ("hw/char: sifive_uart: Print uart characters async") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241104163504.305955-1-thuth@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-06Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into stagingPeter Maydell29-347/+625
Misc HW patch queue - Deprecate a pair of untested microblaze big-endian machines (Philippe) - Arch-agnostic CPU topology checks at machine level (Zhao) - Cleanups on PPC E500 (Bernhard) - Various conversions to DEFINE_TYPES() macro (Bernhard) - Fix RISC-V _pext_u64() name clashing (Pierrick) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcqqycACgkQ4+MsLN6t # wN7TfhAAkAjpWxFGptNw28LPpnZY/NTGKyXQrIEHu3XnJsZ28c/KZeCAYUUC6/q7 # tAnBMb5GIn2VTyt+ElORseFtHStThoR8WMrcQSlGvCZei9lRNKCW0pVIEUgLZEtT # u8lChpaVAn8gXb885xlaCBBP4SuFHEpASSfWy0mYDIqZL3oRhr9AQ/KwzHFqenbK # Uva4BCWRVnYju6MhfA/pmVP011SUTdCu/fsBTIJT3Xn7Sp7fRNShIzt+1rbmPnR2 # hhRl5bMKUgDUjX5GxeP0LOj/XdX9svlqL42imNQT5FFUMIR6qbrwj4U841mt0uuI # FcthAoILvA2XUJoTESq0iXUoN4FQLtc01onY6k06EoZAnn8WRZRp2dNdu8fYmHMX # y3pcXBK6wEhBVZ2DcGVf1txmieUc4TZohOridU1Xfckp+XVl6J3LtTKJIE56Eh68 # S9OJW1Sz2Io/8FJFvKStX0bhV0nBUyUXmi5PjV4vurS6Gy1aVodiiq3ls6baX05z # /Y8DJGpPByA+GI2prdwq9oTIhEIU2bJDDz32NkwHM99SE25h+iyh21Ap5Ojkegm7 # 1squIskxX3QLtEMxBCe+XIKzEZ51kzNZxmLXvCFW5YetypNdhyULqH/UDWt7hIDN # BSh2w1g/lSw9n6DtEN3rURYAR/uV7/7IMEP8Td2wvcDX4o95Fkw= # =q0cF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits) hw/riscv/iommu: fix build error with clang hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro hw/rtc/ds1338: Prefer DEFINE_TYPES() macro hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro hw/sd/sdhci: Prefer DEFINE_TYPES() macro hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/miim: Reuse MII constants hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access hw/ppc/mpc8544_guts: Populate POR PLL ratio status register hw/ppc/e500: Add missing device tree properties to i2c controller node hw/ppc/e500: Remove unused "irqs" parameter hw/ppc/e500: Prefer QOM cast hw/core: Add a helper to check the cache topology level hw/core: Check smp cache topology support for machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-06Merge tag 'crypto-fixes-pull-request' of https://gitlab.com/berrange/qemu ↵Peter Maydell18-166/+146
into staging * Remove deprecated 'loaded' property from crypto objects * Fix error checking of hash function in gcrypt * Perform runtime check for hash functions in gcrypt * Add SM3 hash function to pbkdf # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2vOm/bJrYpEtDo4/vobrtBUQT98FAmcqZpkACgkQvobrtBUQ # T992Gg//TMfrdS8CtjzCMSDbPuGu4NSkNa0nm3vnz6KOyOoZ7MYDjhWFXux0xckG # cetuWBPQR/prQorzVje2ojEa3aUWQ4AxOn6xbHg1bXl+nCLB2iu9RcKy0vc/pZ2i # mFI3HIFyZjETJ/9NXgy7fZFTNmiMAucYwtxfHXwcvRXHH8cBGIwiXpAWpAOo2pXd # iS90PDxxd20anykuHBmN9RSXcLTaEqT5pIMCowqPVh0vwdnLVi+5UpYrwR6JYIG7 # GxsnoXXl5aB786gEL0M2p4XTfJs0zESVMAt2sjxD8gtVDERd87x1cCHLkuVnb3GS # HtHdxRT4TeUjwvYStU9lNpHT3wC1vGaU8x7SBKZ9VensbR+OERWlkdJGRixXc9FT # 1RyRfJzUbCk7wjJFfNmhMvEaE8sSvhxIc1JVQVCDBxqpMYTFOmLZqhD0vpcxkyot # go1+y0+6wlxjw2/JlOG0CDDDnYwOpRCETYTHm0G0/Gm4izu/YQOGqCC/0YA+mOhX # Gkg230gj2BzWYFvU7iGotEY3yWN6qRN06+GRlImDSNmFr6FdEzc8u5ZvDtVuq3++ # SwvbKQ7N0sJbzmWCyB9/rNiJMu5723VW9phCmRwcUBp79fVYJpH+QOHmZixoqBf7 # oKUYxhRhzCiQQaxWG7E8Um7sDjk0LTYf29W0tebCSZuRqSnVHGM= # =tzW1 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 18:40:25 GMT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * tag 'crypto-fixes-pull-request' of https://gitlab.com/berrange/qemu: crypto: perform runtime check for hash/hmac support in gcrypt crypto: fix error check on gcry_md_open crypto: Introduce SM3 hash hmac pbkdf algorithm crypto: purge 'loaded' property that was not fully removed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-06Merge tag 'pull-vfio-20241105' of https://github.com/legoater/qemu into stagingPeter Maydell3-0/+23
vfio queue: * Added migration trace events # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcqTnQACgkQUaNDx8/7 # 7KEzmxAAjEsI1CtImaVP8CWXUihatn8myZiHHA0E/KIjiRF+6ZUrNtrHZaid9Bk8 # 4DAYO15k1PFQVCcd9zlrwZvFx6AsI/4Y0TjP/KkQSW8p5kQ5paYRXuiAcRUVO4YU # tFxHStAHW5K47Xrpun97WzDhpMWI8PTLQwQT0LSoxZwCdl80Hs0i/UneRZtYR/ov # bQLRz7A69ruddfNWrTXxIVhWd0ZSVj7uP8eaBzoOUNtsq2BD96B8T3golb95KO5x # A/hGGQhXsHhDKNoWOTwcQeTnCJpnOXmzIlflCBHFcnhT1EHGXLtGlDv6lfHjH6A+ # pUd7tWw/6gOvBay2AO+2/hR0C9Hb88MxIcAApFLneKEVbTuejWanR1EH8EFVsM0q # ywIYPwx47x68QJfwBT8cpdKjV0Dq0hY/5/8ifISmeFzDLRNmG0WT6ZKibF/q4t0c # W6/B65EvQ5jJLA7q4aK68Hoz6JGCPHEnhOb6PYeFqaMHXkCBU1tCL0imrSLsMD/v # EH/PJNQiU2ZC0K4fyelYeSy8WizscpwpAqYZZAO0JdxJ+qHnKFlZAFyGa+0cQ/g+ # LCJCLrnSikWyWqlCCHORT+pQXLEKKJ2MZYoUn1dUU7MrdmvFUFQPDkQVM0uvJo+x # JyXXTtai9a/EmxS3qWFaHmeLEuuwvauF7pqMonYarhVGjMt76Gs= # =L0Ks # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 16:57:24 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20241105' of https://github.com/legoater/qemu: vfio/migration: Add vfio_save_block_precopy_empty_hit trace event vfio/migration: Add save_{iterate, complete_precopy}_start trace events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-06Merge tag 'pull-lu-20241105' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell10-76/+269
tests/tcg: Replace -mpower8-vector with -mcpu=power8 linux-user: Fix GDB complaining about system-supplied DSO string table index linux-user: Allow custom rt signal mappings # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmcqM2wdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV86KQgAhR1OmVAhPYTJiYH6 # Bhp9s+PbdFw/UbxConf9+WFoa/vM1x/QvX1ybzNDl9aOeiH9RIX4hFWUH5WR8xu+ # gZrzplHDcsrUEs5Q7/GWGJaCbd92Rn6g5wcXyoVebMaVP1g/m+NJoxo2XOpZvY06 # G0BcNj4Ib/D0FgkgZrUJcf3DBWaW/9WCd17fBXLo1bpahdKvqV4PbmhhH+QZCVXr # GHg03F+/35U85kNVnPcUg4PJARQHdK4ZmfE4etgGvVkTdS8r43qfO1nMT0ul8aOD # uATdMQrbwKA0XLjWVOVxe4165c+luHpUweKNgiOie+s849YUM3TsFpunKoPBIEpQ # Gu0ejw== # =wipF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 15:02:04 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-lu-20241105' of https://gitlab.com/rth7680/qemu: tests/tcg: Add SIGRTMIN/SIGRTMAX test linux-user: Allow custom rt signal mappings linux-user: Fix GDB complaining about system-supplied DSO string table index tests/tcg: Replace -mpower8-vector with -mcpu=power8 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-06Merge tag 'bsd-user-2024q4-pull-request' of gitlab.com:bsdimp/qemu into stagingPeter Maydell2-1/+11
bsd-user: Minor fixes These patches have been in my queue pending too long (I have a bunch of others that haven't been reviewd, but those will be done clsoe to the end of the release to not get in the way of the release). The patches align the stack properly on x86_64, implements setting the tb-size and properly setting the ts_tid for initial threads. They have all been reviewed. # -----BEGIN PGP SIGNATURE----- # Comment: GPGTools - https://gpgtools.org # # iQIzBAABCgAdFiEEIDX4lLAKo898zeG3bBzRKH2wEQAFAmcpkl0ACgkQbBzRKH2w # EQADmRAAl301TtPNsGmrjq74qHgFWPNHc4SSQlK8oIIBgM2Mco/sva5N8ZsCIo4K # G6uHRbDn3AXUzi7N72ZRKFxQMDQfthtQDskGvsg3zD96pYXkWF6dB3FwSs0Kg0QW # ow3jj7qiP8NWlbAnMq4fXdtkLGD7S1Og606BYUvk13ILHLY6kwvSWJv53Cq+lDXg # IQkHGWckG5Xvn/OY3KoLbw77APBCn/fbH6e2yAnBgS8STzEPf2I8xWEiwP6gMpc/ # /BdWkEmqJn5hM//Nf+Yz0uTVMh7egwP8+NjTqYMzWCU3kV0Gtk1cTvpJX3wyzZvZ # exLOMjL4C+BClA7EJtBvsRrnvv+8ytxn7F3VCeqFR5nAZiU4L3+WfpSjVe8oYCAw # DL8LYKQA0Abwt6F8EPHwxPxO7HWAKJ4Wxrwlz66juA8gOyuRp+ueVH11ztds6yeh # rWEgwdXMBOuBcNCGgkuTOajFTRK8hmQNcf/okwODMa5Gj2ayyNmFTnD/bFPe7CbA # GzJERU+Xtz1wFg+c5LRqqrOnDqD3wDXDrcOuHRhdRWbAl0rLCdH1CLORXZ3XTuF4 # m9JxmaRiCs++a5XswRrSzxb6BM6hKmKX3baGZUeVW6lKyGyyqvY+uUVKkv4U8KqP # jLPPHE4dicl0/1QbGHZY52gkLYRFXdKa/xKhc8NHXtaWSFACzmo= # =8H2C # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 03:34:53 GMT # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * tag 'bsd-user-2024q4-pull-request' of gitlab.com:bsdimp/qemu: bsd-user: Set TaskState ts_tid for initial threads bsd-user/main: Allow setting tb-size bsd-user/x86_64/target_arch_thread.h: Align stack Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-05hw/riscv/iommu: fix build error with clangPierrick Bouvier1-3/+20
Introduced in 0c54acb8243, "hw/riscv: add RISC-V IOMMU base emulation". ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64' 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext) | ^ D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note: previous definition is here 217 | _pext_u64(unsigned long long __X, unsigned long long __Y) | ^ After a conversation on the mailing list, it was decided to rename and add a comment for this function. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241104222225.1523751-1-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macroBernhard Beschow1-68/+50
The naming of the TypeInfo array is inspired by hcd-ohci-sysbus. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-25-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/rtc/ds1338: Prefer DEFINE_TYPES() macroBernhard Beschow1-12/+8
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-24-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macroBernhard Beschow1-11/+8
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-ID: <20241103133412.73536-23-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macroBernhard Beschow1-13/+8
Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-22-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/sd/sdhci: Prefer DEFINE_TYPES() macroBernhard Beschow1-36/+26
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-21-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macroBernhard Beschow1-12/+8
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-19-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macroBernhard Beschow1-13/+9
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-18-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macroBernhard Beschow1-13/+9
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-17-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/net/fsl_etsec/miim: Reuse MII constantsBernhard Beschow1-13/+6
Instead of defining redundant constants and using magic numbers reuse the existing MII constants. Signed-off-by: Bernhard Beschow <shentey@gmail.com> cc: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241103133412.73536-16-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/pci-host/ppce500: Prefer DEFINE_TYPES() macroBernhard Beschow1-24/+18
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-15-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE defineBernhard Beschow1-1/+1
Prefer a macro rather than a string literal when instantiaging device models. Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macroBernhard Beschow1-12/+8
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-ID: <20241103133412.73536-13-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register accessBernhard Beschow2-4/+10
Reviewed-by: Cédric Le Goater <clg@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/ppc/mpc8544_guts: Populate POR PLL ratio status registerBernhard Beschow1-0/+12
Populate this read-only register with some arbitrary values which avoids U-Boot's get_clocks() to hang(). Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-11-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/ppc/e500: Add missing device tree properties to i2c controller nodeBernhard Beschow1-0/+2
When compiling a decompiled device tree blob created with dumpdtb, dtc complains with: /soc@e0000000/i2c@3000: incorrect #address-cells for I2C bus /soc@e0000000/i2c@3000: incorrect #size-cells for I2C bus Fix this by adding the missing device tree properties. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/ppc/e500: Remove unused "irqs" parameterBernhard Beschow1-2/+2
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/ppc/e500: Prefer QOM castBernhard Beschow1-2/+2
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/core: Add a helper to check the cache topology levelZhao Liu2-0/+49
Currently, we have no way to expose the arch-specific default cache model because the cache model is sometimes related to the CPU model (e.g., i386). Since the user might configure "default" level, any comparison with "default" is meaningless before the machine knows the specific level that "default" refers to. We can only check the correctness of the cache topology after the arch loads the user-configured cache model from MachineState.smp_cache and consumes the special "default" level by replacing it with the specific level. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-ID: <20241101083331.340178-6-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/core: Check smp cache topology support for machineZhao Liu2-0/+44
Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-ID: <20241101083331.340178-5-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05qapi/qom: Define cache enumeration and properties for machineZhao Liu4-0/+143
The x86 and ARM need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topology is closer to the physical topology than a default topology would be. * For ARM, QEMU can't get the cache topology information from the CPU registers, then user configuration is necessary. Additionally, the cache information is also needed for MPAM emulation (for TCG) to build the right PPTT. Define smp-cache related enumeration and properties in QAPI, so that user could configure cache properties for SMP system through -machine in the subsequent patch. Cache enumeration (CacheLevelAndType) is implemented as the combination of cache level (level 1/2/3) and cache type (data/instruction/unified). Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache with smp-cache object to add the basic cache topology support. Other kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be added directly into CacheLevelAndType if necessary. Cache properties (SmpCacheProperties) currently only contains cache topology information, and other cache properties can be added in it if necessary. Note, define cache topology based on CPU topology level with two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. With smp-cache QAPI support, add smp cache topology for machine by parsing the smp-cache object list. Also add the helper to access/update cache topology level of machine. Suggested-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-ID: <20241101083331.340178-4-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/core: Make CPU topology enumeration arch-agnosticZhao Liu5-96/+123
Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and socket. Also, enumerate additional topology levels for non-i386 arches, and add a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work with compatibility requirement of arch-specific cache topology models. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241101083331.340178-3-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05i386/cpu: Don't enumerate the "invalid" CPU topology levelZhao Liu2-6/+10
In the follow-up change, the CPU topology enumeration will be moved to QAPI. And considerring "invalid" should not be exposed to QAPI as an unsettable item, so, as a preparation for future changes, remove "invalid" level from the current CPU topology enumeration structure and define it by a macro instead. Due to the removal of the enumeration of "invalid", bit 0 of CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid" level, but will start at the SMT level. Therefore, to honor this change, update the encoding rule for CPUID[0x1F]. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-ID: <20241101083331.340178-2-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/core/machine: Add missing 'units.h' and 'error-report.h' headersPhilippe Mathieu-Daudé1-0/+2
Include the missing "qemu/units.h" to fix when refactoring code: ../hw/core/machine.c:743:34: error: use of undeclared identifier 'MiB' 743 | mc->default_ram_size = 128 * MiB; | ^ ../hw/core/machine.c:750:44: error: use of undeclared identifier 'TiB' 750 | mc->smbios_memory_device_size = 2047 * TiB; | ^ and "qemu/error-report.h" to fix: ../hw/core/machine.c:1029:13: error: call to undeclared function 'error_report' [-Wimplicit-function-declaration] 1029 | error_report("NUMA node %" PRIu16 " is missing, use " | ^ ../hw/core/machine.c:1240:9: error: call to undeclared function 'warn_report' [-Wimplicit-function-declaration] 1240 | warn_report("CPU model %s is deprecated -- %s", | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240930221900.59525-2-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macroPhilippe Mathieu-Daudé1-2/+15
Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the class_init() handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241105130431.22564-6-philmd@linaro.org>
2024-11-05hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpioPhilippe Mathieu-Daudé1-1/+1
The machine datasheet mentions the GPIO device as 'xps_gpio'. Rename it accordingly to easily find its documentation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241105130431.22564-5-philmd@linaro.org>
2024-11-05hw/microblaze/s3adsp1800: Explicit CPU endiannessPhilippe Mathieu-Daudé1-0/+2
By default the machine's CPU endianness is 'big' order ('little-endian' property set to %false). This corresponds to the default when this machine was added; see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800dsp MMU linux ref-design." and 72b675caacf "microblaze: Hook into the build-system." which added: [ "$target_cpu" = "microblaze" ] && target_bigendian=yes Later commit 877fdc12b1a ("microblaze: Allow targeting little-endian mb") added little-endian support, forgetting to set the CPU endianness to little-endian. Not an issue since this property was never used, but we will use it soon, so explicit the endianness to get the expected behavior. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241105130431.22564-4-philmd@linaro.org>
2024-11-05hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmuPhilippe Mathieu-Daudé5-6/+22
The petalogix-ml605 machine was explicitly added as little-endian only machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU little-endian ref design"). Mark the big-endian version as deprecated. When the xlnx-zynqmp-pmu machine's CPU was added in commit 133d23b3ad1 ("xlnx-zynqmp-pmu: Add the CPU and memory"), its 'endianness' property was set to %true, thus wired in little endianness. Both machine are included in the big-endian system binary, while their CPU is working in little-endian. Unlikely to work as it. Deprecate now as broken config so we can remove soon. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241105130431.22564-3-philmd@linaro.org>
2024-11-05target/microblaze: Alias CPU endianness property as 'little-endian'Philippe Mathieu-Daudé3-2/+12
Alias the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and unset in big order. Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20241105130431.22564-2-philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <3f61b85c-9382-4520-a1ce-5476eb16fb56@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-05Merge tag 'pull-target-arm-20241105' of ↵Peter Maydell55-239/+516
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix MMU indexes for AArch32 Secure PL1&0 in a less complex and buggy way * Fix SVE SDOT/UDOT/USDOT (4-way, indexed) * softfloat: set 2-operand NaN propagation rule at runtime * disas: Fix build against Capstone v6 (again) * hw/rtc/ds1338: Trace send and receive operations * hw/timer/imx_gpt: Convert DPRINTF to trace events * hw/watchdog/wdt_imx2: Remove redundant assignment * hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access * hw/net/npcm_gmac: Change error log to trace event * target/arm: Enable FEAT_CMOW for -cpu max # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmcp/yoZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ucMD/9pWk2ETLjdviPxlacs5IoM # HvGn8Ll2BSMbeb4YdJc7oZ4YJchGpgHhocEwZuaU9HheWjSg+ZEbyhZgN4DdkT8J # pYr+Rl0MgDNN219kYnO/yqnqlgHbtUpE7y57Li3ApoGNbWAVxsH0xoT45Lpi7DOd # uvJfIy/xdaT3zu/4uBjj7c2VrD8wntEayLM8hpqlgeQZKRG3Wtlk/xrQFKOHPDPO # MDbsGoc2FyogRQoo6WH+J6gkkR9PhqXe6Hbf6WIr1/uffZUZU4M8leSw2DgxrYHo # Zf36AzttwO4GHyML/5SR7uvzfXl7OkGyjedLGCUa7INc3br2+GvLMltdLGGPM9cc # ckMHOWd9ZQuSxcpbtPkSYRG0McRE1GLT+KV3BNOLnN9AJl3qv5Qa55iPrtpB08vX # 3jN6H964w99+NoSB2tTHszpep+M7SRuw5QLsuk3tC/qnBMpzKRwZjGVUegNUtfi/ # Lg5ExF8B62K+xb5j5FmODbbXZmb5AD0rV2MGRIVHjiHdnf7J2FmWUJCe2sYFRnRm # nzszhdOKw4PBhC2fb6Vb/DwCqdQy9vcITWpWBtcjkV5mAPhcBo/VNKNeKoc/tPNS # H8FIFIJbtv5aIixqtKcUBUmrBCYy4EoiRMLkqfC09VW60wtWswAP4KBQxi1ogehV # jJw8AgSLCl2MsVmyzgleZQ== # =Woag # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 11:19:06 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20241105' of https://git.linaro.org/people/pmaydell/qemu-arm: (31 commits) target/arm: Enable FEAT_CMOW for -cpu max hw/net/npcm_gmac: Change error log to trace event hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access hw/watchdog/wdt_imx2: Remove redundant assignment hw/timer/imx_gpt: Convert DPRINTF to trace events hw/rtc/ds1338: Trace send and receive operations disas: Fix build against Capstone v6 (again) target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed) target/arm: Add new MMU indexes for AArch32 Secure PL1&0 Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32" softfloat: Remove fallback rule from pickNaN() target/rx: Explicitly set 2-NaN propagation rule target/openrisc: Explicitly set 2-NaN propagation rule target/microblaze: Explicitly set 2-NaN propagation rule target/microblaze: Move setting of float rounding mode to reset target/alpha: Explicitly set 2-NaN propagation rule target/i386: Set 2-NaN propagation rule explicitly target/xtensa: Explicitly set 2-NaN propagation rule target/xtensa: Factor out calls to set_use_first_nan() target/sparc: Explicitly set 2-NaN propagation rule ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-05Merge tag 'pull-plugin-tweaks-051124-1' of https://gitlab.com/stsquad/qemu ↵Peter Maydell6-118/+35
into staging final plugin updates for 9.2 - fix a warning in cflow plugin - replace Makefile with meson.build # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmcp4uoACgkQ+9DbCVqe # KkRj5gf/ZAULfTPipM4HhGpCT/cw5MPJrlK9LDGg5dasWQpZcKBjAjDUkAaizXTe # anv+/TeXb1ybbQbUvmdVUi4HNXd6xpVfX2ippQWsOXYXqSzQLbBjsoM9pCeFZ+Yu # G1M5vvCxnu77nfMMvILBz71eSNj9/HYrr5IPGBnualoBDYfkGgVkjxhC6fb00g52 # jcfabqMEvmn/SEi3kQK4t4BzrZcIIRJdTm5A4sS5Y8mHwQSt56PXoFt+wB0ycfNZ # SWBXsUtYP5DtcQ9GSbxi3POoWGQY3Qa998GlyZIRUBVYhGbZHIi+mDR4eCX3cv+6 # s0xmjquu6aky269EprZhbiO+osZB7Q== # =c48A # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 09:18:34 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-plugin-tweaks-051124-1' of https://gitlab.com/stsquad/qemu: contrib/plugins: remove Makefile for contrib/plugins meson: build contrib/plugins with meson contrib/plugins/cflow: fix warning Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-05crypto: perform runtime check for hash/hmac support in gcryptDaniel P. Berrangé2-2/+2
gcrypto has the ability to dynamically disable hash/hmac algorithms at runtime, so QEMU must perform a runtime check. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-11-05crypto: fix error check on gcry_md_openDaniel P. Berrangé1-2/+2
Gcrypt does not return negative values on error, it returns non-zero values. This caused QEMU not to detect failure to open an unsupported hash, resulting in a later crash trying to use a NULL context. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-11-05crypto: Introduce SM3 hash hmac pbkdf algorithmliequan che13-1/+135
Introduce the SM3 cryptographic hash algorithm (GB/T 32905-2016). SM3 (GB/T 32905-2016) is a cryptographic standard issued by the Organization of State Commercial Cryptography Administration (OSCCA) as an authorized cryptographic algorithm for use within China. Detect the SM3 cryptographic hash algorithm and enable the feature silently if it is available. Signed-off-by: cheliequan <cheliequan@inspur.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-11-05crypto: purge 'loaded' property that was not fully removedDaniel P. Berrangé6-161/+7
The 'loaded' property on TLS creds and secret objects was marked as deprecated in 6.0.0. In 7.1.0 the deprecation info was moved into the 'removed-features.rst' file, but the property was not actually removed, just made read-only. This was a highly unusual practice, so finish the long overdue removal job. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-11-05Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell90-426/+1117
into staging virtio,pc,pci: features, fixes, cleanups CXL now can use Generic Port Affinity Structures. CXL now allows control of link speed and width vhost-user-blk now supports live resize, by means of a new device-sync-config command amd iommu now supports interrupt remapping pcie devices now report extended tag field support intel_iommu dropped support for Transient Mapping, to match VTD spec arch agnostic ACPI infrastructure for vCPU Hotplug Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmcpNqUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRp/2oH/0qO33prhDa48J5mqT9NuJzzYwp5QHKF9Zjv # fDAplMUEmfxZIEgJchcyDWPYTGX2geT4pCFhRWioZMIR/0JyzrFgSwsk1kL88cMh # 46gzhNVD6ybyPJ7O0Zq3GLy5jo7rlw/n+fFxKAuRCzcbK/fmH8gNC+RwW1IP64Na # HDczYilHUhnO7yKZFQzQNQVbK4BckrG1bu0Fcx0EMUQBf4V6x7GLOrT+3hkKYcr6 # +DG5DmUmv20or/FXnu2Ye+MzR8Ebx6JVK3A3sXEE4Ns2CCzK9QLzeeyc2aU13jWN # OpZ6WcKF8HqYprIwnSsMTxhPcq0/c7TvrGrazVwna5RUBMyjjvc= # =zSX4 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 21:03:33 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (65 commits) intel_iommu: Add missed reserved bit check for IEC descriptor intel_iommu: Add missed sanity check for 256-bit invalidation queue intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL hw/acpi: Update GED with vCPU Hotplug VMSD for migration tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35} hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states qtest: allow ACPI DSDT Table changes hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug hw/pci: Add parenthesis to PCI_BUILD_BDF macro hw/cxl: Ensure there is enough data to read the input header in cmd_get_physical_port_state() hw/cxl: Ensure there is enough data for the header in cmd_ccls_set_lsa() hw/cxl: Check that writes do not go beyond end of target attributes hw/cxl: Ensuring enough data to read parameters in cmd_tunnel_management_cmd() hw/cxl: Avoid accesses beyond the end of cel_log. hw/cxl: Check the length of data requested fits in get_log() hw/cxl: Check enough data in cmd_firmware_update_transfer() hw/cxl: Check input length is large enough in cmd_events_clear_records() hw/cxl: Check input includes at least the header in cmd_features_set_feature() hw/cxl: Check size of input data to dynamic capacity mailbox commands hw/cxl/cxl-mailbox-util: Fix output buffer index update when retrieving DC extents ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-05vfio/migration: Add vfio_save_block_precopy_empty_hit trace eventMaciej S. Szmigiero3-0/+10
This way it is clearly known when there's no more data to send for that device. Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
2024-11-05vfio/migration: Add save_{iterate, complete_precopy}_start trace eventsMaciej S. Szmigiero3-0/+13
This way both the start and end points of migrating a particular VFIO device are known. Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
2024-11-05Merge tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu into stagingPeter Maydell6-10/+79
nvme queue # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmcpDm8ACgkQTeGvMW1P # DenpLQgAjpk5tN8oYQKxJVu8qO3RUDatlIXgaZ8ljDSZVIB3cg/qh36qByt2iZNK # FC7oLl/Yl44FHF+6ScWJBcSjXuVkQ/aT8UA1pYbTb9wcURB8atMG9IJxmQuhjlnl # hgvDbpLwyHb4eVuWwA2aKukGZtYyhUcJIoP2RN8wugwg5T7I6R/eaiBG3kCCqIHB # xshgEPIWModzGKR8i6NawhIhFFc3icOabB15QHYwA69BuAK69O9XNlVut2oMLquS # Lv9INkAtYQtqHHvUJGsgcQcTS8vxBGR+TFk05heiThgu2f9kGLu+lV1Ud3WBWeW1 # 6Kt4N1WF9hw6Y4I8pGzEs8C49marFg== # =0S/1 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 18:11:59 GMT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [full] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [full] # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu: hw/nvme: remove dead code hw/nvme: add NPDAL/NPDGL hw/nvme: i/o cmd set independent namespace data structure Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-05Merge tag 'qga-pull-2024-11-4' of https://github.com/kostyanf14/qemu into ↵Peter Maydell5-8/+15
staging qga-pull-2024-11-4 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEwsLBCepDxjwUI+uE711egWG6hOcFAmcozUUACgkQ711egWG6 # hOeSgQ/9FJNPfiGyhbh9RqvAr3DJ8kUskEy7HFedJN0KQJW1U4+0QeMPot9A6Kju # y+1KNKnLPRNSwB6HtbOKwiWGEg37cl0EeEwwxV8kteVlXLHTRguIHK7EXRahOq57 # oU+y2nZEaZeooHOfWsLgIXqxo3OtsYr1v7HZEvuBGakjJ5irSSdDXoZHzPIOJ36K # JY7QdAbEgAfmoLP6LRIMQwbUkhColRPy3mVg5RUOjgYhFbLgCLpr56E5JlLu+J0z # XWrUc8rvpiUYuXqNSNPSrkwhhkb6Wa1g99YA0yJLvnXVp1fG7Utm2Q+QIsKeUuTp # p9jRVvX27dkfHMIQfG+s90NHt9SGCXGoTPVvd3ACpbZy9hCyFh48FzkyRAhrLiF0 # iZ4xAv5gjnne8i+RFJeAtMPh5N32LcnFOODnEbM17xAXWOMKvHqXVHGTiAF6I1mr # iyNdPwfZ9rFH81SbsgAjhs5rjXSNIlwoJq2y7jyoNB0Z1/sGMzy/DlLGP+Xyw2Td # snDXswQ62qgFl2Ea7Vd+adhAbjFkjqt+L5i+8I2c640w2tbTE3Q6v8QZuKCR/I+t # N6nmiifCv0dq90yeBxP5Lq7vIowVKWJegMGSfWokts0UKMXTvYe3EA0LjtWB1zLS # D0dHPtj5/iYrc6Hvu6Ciizb+kJVv5GBk1FAz7kz1AxkW366zSr8= # =O2+e # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 13:33:57 GMT # gpg: using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7 # gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign) <kkostiuk@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7 * tag 'qga-pull-2024-11-4' of https://github.com/kostyanf14/qemu: qemu-ga: Fix a SIGSEGV in ga_run_command() helper qga: fix missing static and prototypes windows warnings qga: fix -Wsometimes-uninitialized windows warning Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-03-06 17:57:36 +0000