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2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng2-0/+15
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng2-0/+28
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng3-0/+78
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng2-0/+21
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: count bits setFrank Chang3-0/+21
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng4-1/+93
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng1-5/+5
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei1-39/+50
Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz is still zero(as we don't use this field), simd_desc will trigger an assert. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation. Here we pass the value to maxsz and oprsz to bypass the assert. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv/pmp: Add assert for ePMP operationsAlistair Francis1-0/+4
Although we construct epmp_operation in such a way that it can only be between 0 and 15 Coverity complains that we don't handle the other possible cases. To fix Coverity and make it easier for humans to read add a default case to the switch statement that calls g_assert_not_reached(). Fixes: CID 1453108 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-id: ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
2021-06-08target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du1-2/+5
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns the output of CSR mtval/stval. Signed-off-by: Changbin Du <changbin.du@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210519155738.20486-1-changbin.du@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2-4/+2
riscv_excp_names[] and riscv_intr_names[] are only referenced by target/riscv/cpu.c locally. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
Physical Memory Protection is a system feature. Avoid polluting the user-mode emulation by its definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210516205333.696094-1-f4bug@amsat.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08docs/system: Move the RISC-V -bios information to removedAlistair Francis3-20/+17
QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt and sifive_u machines. This patch moves that change from the deprecated.rst file to the removed-features.rst file and the target-riscv.rst. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
2021-06-08target/riscv: fix wfi exception behaviorJose Martins2-3/+9
The wfi exception trigger behavior should take into account user mode, hstatus.vtw, and the fact the an wfi might raise different types of exceptions depending on various factors: If supervisor mode is not present: - an illegal instruction exception should be generated if user mode executes and wfi instruction and mstatus.tw = 1. If supervisor mode is present: - when a wfi instruction is executed, an illegal exception should be triggered if either the current mode is user or the mode is supervisor and mstatus.tw is set. Plus, if the hypervisor extensions are enabled: - a virtual instruction exception should be raised when a wfi is executed from virtual-user or virtual-supervisor and hstatus.vtw is set. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210420213656.85148-1-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng2-8/+103
At present the Microchip Icicle Kit machine only supports using '-bios' to load the HSS, and does not support '-kernel' for direct kernel booting just like other RISC-V machines do. One has to use U-Boot which is chain-loaded by HSS, to load a kernel for testing. This is not so convenient. Adding '-kernel' support together with the existing '-bios', we follow the following table to select which payload we execute: -bios | -kernel | payload ------+------------+-------- N | N | HSS Y | don't care | HSS N | Y | kernel This ensures backwards compatibility with how we used to expose '-bios' to users. When '-kernel' is used for direct boot, '-dtb' must be present to provide a valid device tree for the board, as we don't generate device tree. When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload like U-Boot or OS kernel directly. Documentation is updated to describe the direct kernel boot. Note as of today there is still no PolarFire SoC support in the upstream Linux kernel hence the document does not include instructions for that. It will be updated in the future. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng4-12/+11
The OpenSBI BIOS image names are used by many RISC-V machines. Let's define macros for them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08docs/system/riscv: sifive_u: Document '-dtb' usageBin Meng1-6/+41
Update the 'sifive_u' machine documentation to mention the '-dtb' option that can be used to pass a custom DTB to QEMU. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08docs/system/riscv: Correct the indentation level of supported devicesBin Meng2-25/+25
The supported device bullet list has an additional space before each entry, which makes a wrong indentation level. Correct it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng2-2/+10
The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the compatible string in the upstream Linux kernel. "riscv,plic0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng3-3/+15
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-2/+5
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the compatible strings for the SiFive test device node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-3/+3
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the clock name for the ethernet controller node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-07Merge remote-tracking branch ↵Peter Maydell19-28/+30
'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial branch pull request 20210607 # gpg: Signature made Mon 07 Jun 2021 19:56:43 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: vhost-vdpa: Remove redundant declaration of address_space_memory scripts/oss-fuzz: Fix typo in documentation target/mips: Fix 'Uncoditional' typo target/hppa: Remove unused 'memory.h' header hw/display/macfb: Classify the "nubus-macfb" as display device target/nios2: fix page-fit instruction count docs: fix broken reference linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[] misc: Correct relative include path i386/kvm: The value passed to strerror should be positive target/riscv: Do not include 'pmp.h' in user emulation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-07Merge remote-tracking branch ↵Peter Maydell11-14/+203
'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging A few testing and configure updates: - add the multiarch signals stress test - fix display of multi-word compiler stanzas in meson - fix quoting of multi-word compiler stazas in configure.sh - tag some acceptance tests as TCG only - make checkpatch test work harder to find clean diffs - split gprof/gconv job to avoid timeouts - fix centos8 VM build by adding --source-path - make checkpatch aware of .h.inc and .c.inc paths # gpg: Signature made Mon 07 Jun 2021 14:51:12 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-updates-070621-2: scripts/checkpatch.pl: process .c.inc and .h.inc files as C source tests/vm: expose --source-path to scripts to find extra files gitlab-ci: Split gprof-gcov job gitlab: work harder to avoid false positives in checkpatch tests/acceptance: tag various arm tests as TCG only tests/tcg/configure.sh: tweak quoting of target_compiler meson.build: fix cosmetics of compiler display tests/tcg: add a multiarch signals test to stress test signal delivery Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-07scripts/checkpatch.pl: process .c.inc and .h.inc files as C sourceMatheus Ferst1-2/+2
Change the regex used to determine whether a file should be processed as C source to include .c.inc and .h.inc extensions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210520195142.941261-1-matheus.ferst@eldorado.org.br> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-06-07tests/vm: expose --source-path to scripts to find extra filesAlex Bennée3-1/+6
Currently the centos8 image expects to run an in-src build to find the kick starter file. Fix this. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210602103527.32021-1-alex.bennee@linaro.org>
2021-06-07gitlab-ci: Split gprof-gcov jobPhilippe Mathieu-Daudé1-3/+14
This job is hitting the 70min limit, so split it in 2 tasks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210525082556.4011380-7-f4bug@amsat.org>
2021-06-07gitlab: work harder to avoid false positives in checkpatchAlex Bennée1-1/+5
This copies the behaviour of patchew's configuration to make the diff algorithm generate a minimal diff. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210602153247.27651-1-alex.bennee@linaro.org>
2021-06-07tests/acceptance: tag various arm tests as TCG onlyAlex Bennée1-0/+18
We should never be trying to run most of these models under a KVM environment. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210527160319.19834-7-alex.bennee@linaro.org>
2021-06-07tests/tcg/configure.sh: tweak quoting of target_compilerAlex Bennée1-3/+3
If you configure the host compiler with a multi-command stanza like: --cc="ccache gcc" then the configure.sh machinery falls over with confusion. Work around this by ensuring we correctly quote so where we need a complete evaluation we get it. Of course the has() check needs single variable so we need to unquote that. This does mean it essentially checks that just the ccache command exits but if we got past that step we still check the compiler actually does something. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Message-Id: <20210527160319.19834-4-alex.bennee@linaro.org>
2021-06-07meson.build: fix cosmetics of compiler displayAlex Bennée1-4/+4
If you specify something like --cc="ccache gcc" on your configure line the summary output misses the rest of the cmd_array. Do some string joining to make it complete. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527160319.19834-3-alex.bennee@linaro.org>
2021-06-07tests/tcg: add a multiarch signals test to stress test signal deliveryAlex Bennée2-0/+151
This adds a simple signal test that combines the POSIX timer_create with signal delivery across multiple threads. The aim is to provide a bit more of a stress test to flush out signal handling issues for easily than the occasional random crash we sometimes see in linux-test or threadcount. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527160319.19834-2-alex.bennee@linaro.org>
2021-06-05vhost-vdpa: Remove redundant declaration of address_space_memoryXie Yongji2-1/+1
The symbol address_space_memory are already declared in include/exec/address-spaces.h. So let's add this header file and remove the redundant declaration in include/hw/virtio/vhost-vdpa.h. Signed-off-by: Xie Yongji <xieyongji@bytedance.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20210517123246.999-1-xieyongji@bytedance.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05scripts/oss-fuzz: Fix typo in documentationPhilippe Mathieu-Daudé1-1/+1
While we only use stdin, the chardev is named 'stdio'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20210602170759.2500248-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05target/mips: Fix 'Uncoditional' typoPhilippe Mathieu-Daudé1-3/+3
Fix Uncoditional -> Unconditional typo. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210602170759.2500248-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05target/hppa: Remove unused 'memory.h' headerPhilippe Mathieu-Daudé1-1/+0
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517101558.1040191-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05hw/display/macfb: Classify the "nubus-macfb" as display deviceThomas Huth1-0/+1
The "nubus-macfb" currently shows up as uncategorized device in the output of "-device help". Put it into the display category to fix this ugliness. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210531073255.46286-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05target/nios2: fix page-fit instruction countPavel Dovgalyuk1-1/+1
This patch fixes calculation of number of the instructions that fit the current page. It prevents creation of the translation blocks that cross the page boundaries. It is required for deterministic exception generation in icount mode. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <162072241046.823357.10485774346114851009.stgit@pasha-ThinkPad-X280> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05docs: fix broken referenceJohn Snow1-1/+1
Long story short, we need a space here for the reference to work correctly. Longer story: Without the space, kerneldoc generates a line like this: one of :c:type:`MemoryListener.region_add\(\) <MemoryListener>`,:c:type:`MemoryListener.region_del\(\) Sphinx does not process the role information correctly, so we get this (my pseudo-notation) construct: <text>,:c:type:</text> <reference target="MemoryListener">MemoryListener.region_del()</reference> which does not reference the desired entity, and leaves some extra junk in the rendered output. See https://qemu-project.gitlab.io/qemu/devel/memory.html#c.MemoryListener member log_start for an example of the broken output as it looks today. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210511192950.2061326-1-jsnow@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[]Philippe Mathieu-Daudé1-2/+2
Keep bitmask_transtbl in .rodata by marking the arrays const. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210517055243.830491-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05misc: Correct relative include pathPhilippe Mathieu-Daudé4-6/+6
Headers should be included from the 'include/' directory, not from the root directory. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210516205034.694788-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05i386/kvm: The value passed to strerror should be positiveDmitry Voronetskiy5-12/+12
Signed-off-by: Dmitry Voronetskiy <vda1999@yandex.ru> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210519113528.12474-1-davoronetskiy@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
Physical Memory Protection is a system feature. Avoid polluting the user-mode emulation by its definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210516205333.696094-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' ↵Peter Maydell14-79/+1001
into staging Host vector support for arm neon. # gpg: Signature made Fri 04 Jun 2021 19:56:59 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210604: tcg/arm: Implement TCG_TARGET_HAS_rotv_vec tcg/arm: Implement TCG_TARGET_HAS_roti_vec tcg/arm: Implement TCG_TARGET_HAS_shv_vec tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec tcg/arm: Implement TCG_TARGET_HAS_minmax_vec tcg/arm: Implement TCG_TARGET_HAS_sat_vec tcg/arm: Implement TCG_TARGET_HAS_mul_vec tcg/arm: Implement TCG_TARGET_HAS_shi_vec tcg/arm: Implement andc, orc, abs, neg, not vector operations tcg/arm: Implement minimal vector operations tcg/arm: Implement tcg_out_dup*_vec tcg/arm: Implement tcg_out_mov for vector types tcg/arm: Implement tcg_out_ld/st for vector types tcg/arm: Add host vector framework tcg: Change parameters for tcg_target_const_match Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_rotv_vecRichard Henderson1-1/+34
Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_roti_vecRichard Henderson3-0/+17
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_shv_vecRichard Henderson2-1/+63
The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson3-3/+22
NEON has 3 instructions implementing this 4 argument operation, with each insn overlapping a different logical input onto the destination register. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2-1/+25
This is minimum and maximum, signed and unsigned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04tcg/arm: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2-1/+25
This is saturating add and subtract, signed and unsigned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-16 10:48:14 +0000