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2020-01-12test: Move qtests to a separate directoryThomas Huth109-158/+157
The tests directory itself is pretty overcrowded, and it's hard to see which test belongs to which test subsystem (unit, qtest, ...). Let's move the qtests to a separate folder for more clarity. Message-Id: <20191218103059.11729-6-thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-01-12tests/Makefile: Separate unit test dependencies from qtest dependenciesThomas Huth1-5/+5
Some of the unit test dependencies are declared right in the block of the qtest dependencies. Let's move them to the other unit tests instead. Message-Id: <20191218103059.11729-5-thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-01-12tests/Makefile: Remove 'tests/' and '$(EXESUF)' from the check-qtest variablesThomas Huth1-126/+130
It's much easier if we simply add the folder prefix and the exe suffix later via a substitution instead. Message-Id: <20191218103059.11729-4-thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-01-12tests/ptimer: Remove unnecessary inclusion of libqtest.hThomas Huth1-1/+0
ptimer-test is a unit test, not a qtest, so libqtest.h is not required here. Message-Id: <20191218103059.11729-3-thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-01-12tests/Makefile: test-char does not need libqtestThomas Huth1-1/+1
No need to link the libqtest objects here. Message-Id: <20191218103059.11729-2-thuth@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-01-10Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200108' ↵Peter Maydell28-161/+345
into staging ppc patch queue 2020-01-08 Here's another pull request for qemu-5.0 of ppc related changes. Highlights are: * First parts of support for POWER Secure VMs * Rework to clean up how we pass context information to the various components of the pnv machine (reduces usage of qdev_get_machine()) * Assorted cleanups and bugfixes # gpg: Signature made Wed 08 Jan 2020 05:22:08 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.0-20200108: (26 commits) ppc/pnv: fix check on return value of blk_getlength() ppc/pnv: check return value of blk_pwrite() pnv/psi: Consolidate some duplicated code in pnv_psi_realize() pnv/psi: Add device reset hook pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr xive: Add a "presenter" link property to the TCTX object ppc/pnv: Add a "pnor" const link property to the BMC internal simulator ppc/pnv: Add an "nr-threads" property to the base chip class xive: Use the XIVE fabric link under the XIVE router spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router pnv/xive: Use device_class_set_parent_realize() ppc/pnv: Introduce a "xics" property under the POWER8 chip ppc/pnv: Introduce a "xics" property alias under the PSI model spapr/xive: remove redundant check in spapr_match_nvt() ppc/pnv: Drop "num-chips" machine property ppc440_bamboo.c: remove label from bamboo_load_device_tree() spapr.c: remove 'out' label in spapr_dt_cas_updates() ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG spapr/xive: Use device_class_set_parent_realize() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-10Merge remote-tracking branch ↵Peter Maydell26-56/+328
'remotes/stsquad/tags/pull-testing-and-semihosting-090120-2' into staging Testing fixes and semiconsole support: - build fix (missing x86-iommu stubs) - python fixes for freebsd and OSX - nicer reporting of acceptance failures - fix build nesting of fp-test (breaks bsds) - semihosting clean-ups - support for blocking semihosting console # gpg: Signature made Thu 09 Jan 2020 11:42:51 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-semihosting-090120-2: tests/tcg: add user version of dumb-as-bricks semiconsole test tests/tcg: extract __semi_call into a header and expand tests/tcg: add a dumb-as-bricks semihosting console test semihosting: add qemu_semihosting_console_inc for SYS_READC target/arm: only update pc after semihosting completes target/arm: remove unused EXCP_SEMIHOST leg testing: don't nest build for fp-test travis.yml: install homebrew python for OS X travis.yml: duplicate before_script for MacOSX travis.yml: Detach build and test steps travis.yml: avocado: Print logs of non-pass tests only freebsd: use python37 tests/vm: update openbsd to release 6.6 hw/i386/x86-iommu: Add missing stubs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-10configure: check for gdbus-codegen presenceMarc-André Lureau1-0/+3
Some distros ship gdbus-codegen separately for gio headers/pc... Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20200110112725.689401-1-marcandre.lureau@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-09tests/tcg: add user version of dumb-as-bricks semiconsole testAlex Bennée3-0/+53
There are linux-user users of semihosting so we'd better check things work for them as well. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09tests/tcg: extract __semi_call into a header and expandAlex Bennée3-20/+45
There are two types of ARM semicall - lets test them both. Putting the logic in a header will make re-using the functions easier later. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09tests/tcg: add a dumb-as-bricks semihosting console testAlex Bennée2-1/+48
We don't run this during check-tcg as we would need to check stuff is echoed back. However we can still build the binary so people can test it manually. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09semihosting: add qemu_semihosting_console_inc for SYS_READCKeith Packard7-2/+134
Provides a blocking call to read a character from the console using semihosting.chardev, if specified. This takes some careful command line options to use stdio successfully as the serial ports, monitor and semihost all want to use stdio. Here's a sample set of command line options which share stdio between semihost, monitor and serial ports: qemu \ -chardev stdio,mux=on,id=stdio0 \ -serial chardev:stdio0 \ -semihosting-config enable=on,chardev=stdio0 \ -mon chardev=stdio0,mode=readline This creates a chardev hooked to stdio and then connects all of the subsystems to it. A shorter mechanism would be good to hear about. Signed-off-by: Keith Packard <keithp@keithp.com> Message-Id: <20191104204230.12249-1-keithp@keithp.com> [AJB: fixed up deadlock, minor commit title reword] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09target/arm: only update pc after semihosting completesAlex Bennée6-4/+9
Before we introduce blocking semihosting calls we need to ensure we can restart the system on semi hosting exception. To be able to do this the EXCP_SEMIHOST operation should be idempotent until it finally completes. Practically this means ensureing we only update the pc after the semihosting call has completed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com>
2020-01-09target/arm: remove unused EXCP_SEMIHOST legAlex Bennée1-6/+0
All semihosting exceptions are dealt with earlier in the common code so we should never get here. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com>
2020-01-09testing: don't nest build for fp-testAlex Bennée2-9/+7
Re-calling the main make is counter-productive and really messes up with parallel builds. Just ensure we have built the pre-requisites before we build the fp-test bits. If the user builds manually just complain if the parent build hasn't got the bits we need. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org>
2020-01-09travis.yml: install homebrew python for OS XAlex Bennée1-7/+10
Our python3 requirements now outstrip those of the build. While we are at it we can move more of the special casing for Mac into the one build we have. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2020-01-09travis.yml: duplicate before_script for MacOSXAlex Bennée1-1/+5
Rather than keep the hack in the global code lets "Think Different" and have a special copy for MacOSX. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2020-01-09travis.yml: Detach build and test stepsWainer dos Santos Moschetta1-1/+2
Currently build and test commands are a single step in a Travis's `script` block. In order to see the output of the tests one needs to scroll down the log to find where the build messages ended and the limit is not clear. If they were in different steps then Travis would print the result build command, which can be easily grep'ed. So this change is made to detach those commands to ease the visualization of the output. Note that all steps on the `script` block is executed regardless if one previous has failed. To overcome it, let's save the return code of the build then check whether succeed or failed on the test step. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20191230184327.2800-3-wainersm@redhat.com>
2020-01-09travis.yml: avocado: Print logs of non-pass tests onlyWainer dos Santos Moschetta1-2/+2
The acceptance tests build on Travis is configured to print the entire Avocado's job log in case any test fail. Usually one is interested on failed tests only though. So this change the Travis configuration in order to show the log of tests which status is different from 'PASS' and 'SKIP' only. Note that 'CANCEL'-ed tests will have the log printed too because it can help to debug some condition on CI environment which is not being fulfilled. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20191230184327.2800-2-wainersm@redhat.com>
2020-01-09freebsd: use python37Gerd Hoffmann1-1/+2
FreeBSD seems to use python37 by default now, which breaks the build script. Add python to the package list, to explicitly pick the version, and also adapt the configure command line. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200106123746.18201-1-kraxel@redhat.com>
2020-01-09tests/vm: update openbsd to release 6.6Gerd Hoffmann1-2/+2
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20191018102443.26469-1-kraxel@redhat.com>
2020-01-09hw/i386/x86-iommu: Add missing stubsPhilippe Mathieu-Daudé1-0/+9
In commit 6c730e4af9 we introduced a stub to build the MicroVM machine without Intel IOMMU. This stub is incomplete for the other PC machines. Add the missing stubs. Fixes: 6c730e4af9 Reported-by: Travis-CI Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20191220154225.25879-1-philmd@redhat.com>
2020-01-08ppc/pnv: fix check on return value of blk_getlength()Cédric Le Goater2-2/+2
blk_getlength() returns an int64_t but the result is stored in a uint32_t. Errors (negative values) won't be caught by the check in pnv_pnor_realize() and blk_blockalign() will allocate a very large buffer in such cases. Fixes Coverity issue CID 1412226. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200107171809.15556-3-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: check return value of blk_pwrite()Cédric Le Goater1-2/+6
When updating the PNOR file contents, we should check for a possible failure of blk_pwrite(). Fixes Coverity issue CID 1412228. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200107171809.15556-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08pnv/psi: Consolidate some duplicated code in pnv_psi_realize()Greg Kurz1-7/+12
The proper way to do that would be to use device_class_set_parent_realize(), but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_realize pointer adds a fair amount of code. Calling pnv_psi_realize() explicitely is fine for now. This should probably be achieved with a device realize hook in the PSI base class and device_class_set_parent_realize() in the children classes. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <157841476667.66386.13659183399113837990.stgit@bahia.tlslab.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08pnv/psi: Add device reset hookGreg Kurz1-4/+11
And call it from a QEMU reset handler. This allows each PNV child class to override the reset hook if needed, eg. POWER8 doesn't but POWER9 does. The proper way to do that would be to use device_class_set_parent_reset(), but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_reset pointer adds a fair amount of code. Calling pnv_psi_reset() explicitely is fine for now. A subsequent patch will consolidate the call to qemu_register_reset() in a single place. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <157841476035.66386.17838417527621752518.stgit@bahia.tlslab.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptrGreg Kurz3-22/+2
And use it instead of reaching out to the machine. This allows to get rid of pnv_get_chip(). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106145645.4539-11-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptrGreg Kurz1-5/+4
And use it instead of reaching out to the machine. This allows to get rid of a call to qdev_get_machine() and to reduce the scope of another one so that it is only used within the argument list of error_append_hint(). This is an acceptable tradeoff compared to all it would require to know about the maximum number of CPUs here without calling qdev_get_machine(). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106145645.4539-10-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08xive: Add a "presenter" link property to the TCTX objectCédric Le Goater4-6/+13
This will be used in subsequent patches to access the XIVE associated to a TCTX without reaching out to the machine through qdev_get_machine(). Signed-off-by: Cédric Le Goater <clg@kaod.org> [ groug: - split patch - write subject and changelog ] Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106145645.4539-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: Add a "pnor" const link property to the BMC internal simulatorGreg Kurz3-5/+7
This allows to get rid of a call to qdev_get_machine(). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106145645.4539-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: Add an "nr-threads" property to the base chip classGreg Kurz2-3/+6
Set it at chip creation and forward it to the cores. This allows to drop a call to qdev_get_machine(). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200106145645.4539-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08xive: Use the XIVE fabric link under the XIVE routerGreg Kurz1-3/+11
Now that the spapr and pnv machines do set the "xive-fabric" link, the use of the XIVE fabric pointer becomes mandatory. This is checked with an assert() in a new realize hook. Since the XIVE router is realized at machine init for the all the machine's life time, no risk to abort an already running guest (ie. not a hotplug path). This gets rid of a qdev_get_machine() call. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106145645.4539-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08spapr, pnv, xive: Add a "xive-fabric" link to the XIVE routerGreg Kurz4-2/+19
In order to get rid of qdev_get_machine(), first add a pointer to the XIVE fabric under the XIVE router and make it configurable through a QOM link property. Configure it in the spapr and pnv machine. In the case of pnv, the XIVE routers are under the chip, so this is done with a QOM alias property of the POWER9 pnv chip. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106145645.4539-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08pnv/xive: Use device_class_set_parent_realize()Greg Kurz2-0/+20
The XIVE router base class currently inherits an empty realize hook from the sysbus device base class, but it will soon implement one of its own to perform some sanity checks. Do the preliminary plumbing to have it called. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200106145645.4539-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: Introduce a "xics" property under the POWER8 chipCédric Le Goater2-5/+21
POWER8 is the only chip using the XICS interface. Add a "xics" link and a XICSFabric attribute under this chip to remove the use of qdev_get_machine() Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200106145645.4539-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: Introduce a "xics" property alias under the PSI modelCédric Le Goater2-11/+4
This removes the need of the intermediate link under PSI to pass the XICS link to the underlying ICSState object. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20200106145645.4539-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08spapr/xive: remove redundant check in spapr_match_nvt()Cédric Le Goater1-4/+4
spapr_match_nvt() is a XIVE operation and is used by the machine to look for a matching target when an event notification is being delivered. An assert checks that spapr_match_nvt() is called only when the machine has selected the XIVE interrupt mode but it is redundant with the XIVE_PRESENTER() dynamic cast. Apply the cast to spapr->active_intc and remove the assert. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200106163207.4608-1-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: Drop "num-chips" machine propertyGreg Kurz1-50/+12
The number of CPU chips of the powernv machine is configurable through a "num-chips" property. This doesn't fit well with the CPU topology, eg. some configurations can come up with more CPUs than the maximum of CPUs set in the toplogy. This causes assertion to be hit with mttcg: -machine powernv,num-chips=2 -smp cores=2 -accel tcg,thread=multi ERROR: tcg/tcg.c:789:tcg_register_thread: assertion failed: (n < ms->smp.max_cpus) Aborted (core dumped) Mttcg mandates the CPU topology to be dimensioned to the actual number of CPUs, depending on the number of chips the user asked for. That is, '-machine num-chips=N' should always have a '-smp' companion with a topology that meats the resulting number of CPUs, typically '-smp sockets=N'. It thus seems that "num-chips" doesn't bring anything but forcing the user to specify the requested number of chips on the command line twice. Simplify the command line by computing the number of chips based on the CPU topology exclusively. The powernv machine isn't a production thing ; it is mostly used by developpers to prepare the bringup of real HW. Because of this and for simplicity, this deliberately ignores the official deprecation process and dumps "num-chips" right away : '-smp sockets=N' is now the only way to control the number of CPU chips. This is done at machine init because smp_parse() is called after instance init. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157830658266.533764.2214183961444213947.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc440_bamboo.c: remove label from bamboo_load_device_tree()Daniel Henrique Barboza1-6/+2
'out' label can be replaced by 'return -1' in all cases. CC: David Gibson <david@gibson.dropbear.id.au> CC: qemu-ppc@nongnu.org Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200106182425.20312-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08spapr.c: remove 'out' label in spapr_dt_cas_updates()Daniel Henrique Barboza1-6/+3
'out' can be replaced by 'return' with the appropriate return value. CC: David Gibson <david@gibson.dropbear.id.au> CC: qemu-ppc@nongnu.org Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200106182425.20312-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCGBharata B Rao1-2/+5
Invoking KVM_SVM_OFF ioctl for TCG guests will lead to a QEMU crash. Fix this by ensuring that we don't call KVM_SVM_OFF ioctl on TCG. Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru> Fixes: 4930c1966249 ("ppc/spapr: Support reboot of secure pseries guest") Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20200102054155.13175-1-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08spapr/xive: Use device_class_set_parent_realize()Greg Kurz2-1/+21
The XIVE router base class currently inherits an empty realize hook from the sysbus device base class, but it will soon implement one of its own to perform some sanity checks. Do the preliminary plumbing to have it called. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191219181155.32530-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08mos6522: remove anh registerLaurent Vivier2-9/+8
Register addr 1 is defined as buffer A with handshake (vBufAH), register addr 15 is also defined as buffer A without handshake (vBufA). As both addresses access the same register, remove the definition of 'anh' and use only 'a' (with VIA_REG_ANH and VIA_REG_A). Fixes: 51f233ec92cd ("misc: introduce new mos6522 VIA device and enable it for ppc builds") Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20191220214054.76525-1-laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/pnv: Modify the powerdown notifier to get the PowerNV machineCédric Le Goater1-1/+1
Use container_of() instead of qdev_get_machine() Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191219181155.32530-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08ppc/spapr: Support reboot of secure pseries guestBharata B Rao3-0/+22
A pseries guest can be run as a secure guest on Ultravisor-enabled POWER platforms. When such a secure guest is reset, we need to release/reset a few resources both on ultravisor and hypervisor side. This is achieved by invoking this new ioctl KVM_PPC_SVM_OFF from the machine reset path. As part of this ioctl, the secure guest is essentially transitioned back to normal mode so that it can reboot like a regular guest and become secure again. This ioctl has no effect when invoked for a normal guest. If this ioctl fails for a secure guest, the guest is terminated. Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20191219031445.8949-3-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08linux-headers: UpdateBharata B Rao7-4/+132
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2") Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20191219031445.8949-2-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08target/ppc: Handle AIL=0 in ppc_excp_vector_offsetFabiano Rosas1-0/+2
The exception vector offset calculation was moved into a function but the case when AIL=0 was not checked. The reason we got away with this is that the sole caller of ppc_excp_vector_offset checks the AIL before calling the function: /* Handle AIL */ if (ail) { ... vector |= ppc_excp_vector_offset(cs, ail); } Fixes: 2586a4d7a0 ("target/ppc: Move exception vector offset computation into a function") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20191217142512.574075-1-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-08target/ppc: Remove unused PPC_INPUT_INT definesFabiano Rosas1-6/+0
They were added in "16415335be Use correct input constant" with a single use in kvm_arch_pre_run but that function's implementation was removed by "1e8f51e856 ppc: remove idle_timer logic". Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20191218014616.686124-1-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-07Merge remote-tracking branch 'remotes/elmarco/tags/prop-ptr-pull-request' ↵Peter Maydell47-391/+509
into staging Clean-ups: qom-ify serial and remove QDEV_PROP_PTR Hi, QDEV_PROP_PTR is marked in multiple places as "FIXME/TODO/remove me". In most cases, it can be easily replaced with QDEV_PROP_LINK when the pointer points to an Object. There are a few places where such substitution isn't possible. For those places, it seems reasonable to use a specific setter method instead, and keep the user_creatable = false. In other places, proper usage of qdev or other facilies is the solution. The serial code wasn't converted to qdev, which makes it a bit more archaic to deal with. Let's convert it first, so we can more easily embed it from other devices, and re-export some properties and drop QDEV_PROP_PTR usage. # gpg: Signature made Tue 07 Jan 2020 15:01:26 GMT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/prop-ptr-pull-request: (37 commits) qdev/qom: remove some TODO limitations now that PROP_PTR is gone qdev: remove QDEV_PROP_PTR qdev: remove PROP_MEMORY_REGION omap-gpio: remove PROP_PTR omap-i2c: remove PROP_PTR omap-intc: remove PROP_PTR smbus-eeprom: remove PROP_PTR cris: improve passing PIC interrupt vector to the CPU mips/cps: fix setting saar property qdev: use g_strcmp0() instead of open-coding it leon3: use qdev gpio facilities for the PIL leon3: use qemu_irq framework instead of callback as property dp8393x: replace PROP_PTR with PROP_LINK etraxfs: remove PROP_PTR usage lance: replace PROP_PTR with PROP_LINK vmmouse: replace PROP_PTR with PROP_LINK sm501: make SerialMM a child, export chardev property mips: use sysbus_mmio_get_region() instead of internal fields mips: use sysbus_add_io() mips: baudbase is 115200 by default ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-07Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request' ↵Peter Maydell7-93/+348
into staging m68k: fix CACR valid bits q800: add a fake mac rom reset (used by linux) fix and improve PRAM emulation # gpg: Signature made Tue 07 Jan 2020 13:25:50 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/q800-for-5.0-pull-request: target/m68k: only change valid bits in CACR q800: implement mac rom reset function for BIOS-less mode q800: add a block backend to the PRAM q800: fix mac_via RTC PRAM commands Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-12-27 20:36:31 +0000