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2021-12-21scripts: teach modinfo to skip non-C sourcesMarc-André Lureau1-0/+3
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21console: save current scanout detailsMarc-André Lureau2-54/+138
Add a new DisplayScanout structure to save the current scanout details. This allows to attach later UI backends and set the scanout. Introduce displaychangelistener_display_console() helper function to handle the dpy_gfx_switch/gl_scanout() & dpy_gfx_update() calls. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: move qemu_spice_fill_device_address to ui/util.cMarc-André Lureau7-56/+92
Other backends can use it. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: split the GL context in a different objectMarc-André Lureau14-76/+119
This will allow to have one GL context but a variable number of listeners. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: dispatch GL events to all listenersMarc-André Lureau1-16/+42
For now, only one listener can receive GL events. Let's dispatch to all listeners. (preliminary check ensure there is a single listener now during regitration, and in next patches, compatible listeners only) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: simplify gl unblock & flushMarc-André Lureau10-32/+8
GraphicHw.gl_flushed was introduced to notify the device (vhost-user-gpu) that the GL resources (the display scanout) are no longer needed. It was decoupled from QEMU own gl-blocking mechanism, but that difference isn't helping. Instead, we can reuse QEMU gl-blocking and notify virtio_gpu_gl_flushed() when unblocking (to unlock vhost-user-gpu). An extra block/unblock is added arount dpy_gl_update() so existing backends that don't block will have the flush event handled. It will also help when there are no backends associated. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: add a gl-unblock warning timerMarc-André Lureau1-0/+17
Similar to the one that exists for Spice, so we can investigate if something is locked. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: make gl_block use a counterMarc-André Lureau1-4/+13
Track multiple callers blocking requests. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: associate GL context outside of display listener registrationMarc-André Lureau5-2/+15
Consoles can have an associated GL context, without listeners (they may be added or removed later on). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: factor out qemu_console_set_display_gl_ctx()Marc-André Lureau2-8/+17
The next patch will make use of this function to dissociate DisplayChangeListener from GL context. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-12-21ui: do not delay further remote resizeMarc-André Lureau7-8/+9
A remote client, such as Spice, will already avoid flooding the stream by delaying the resize requests. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21virtio-gpu: use VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOPMarc-André Lureau1-1/+1
It's part of Linux headers for a while now. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-12-21hw/display: report an error if virgl initialization failedMarc-André Lureau1-0/+1
Currently, virgl initialization error is silent. Make it verbose instead. (this is likely going to bug later on, as the device isn't fully initialized) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-12-21ui/clipboard: add a clipboard reset serial eventMarc-André Lureau6-0/+37
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui/clipboard: add qemu_clipboard_check_serial()Marc-André Lureau2-0/+25
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui/vdagent: add serial capability supportMarc-André Lureau3-1/+43
The Spice agent implements a simple serial mechanism to avoid clipboard races between client & guest. See: https://gitlab.freedesktop.org/spice/spice-protocol/-/commit/045a6978d6dbbf7046affc5c321fa8177c8cce56 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui: generalize clipboard notifierMarc-André Lureau7-29/+101
Use a QemuClipboardNotify union type for extendable clipboard events. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui/vdagent: replace #if 0 with protocol version checkMarc-André Lureau1-3/+5
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-21ui/vdagent: add CHECK_SPICE_PROTOCOL_VERSIONMarc-André Lureau2-0/+13
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2021-12-20Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson80-930/+1097
Move errno processing from safe_syscall() to safe_syscall_base(). Move safe_syscall() from linux-user to common-user. Add FreeBSD support to safe_syscall_base(). Tidy top-level meson.build wrt {bsd,linux}-user. # gpg: Signature made Mon 20 Dec 2021 11:46:11 AM PST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu: meson: Move bsd_user_ss to bsd-user/ meson: Move linux_user_ss to linux-user/ linux-user: Move thunk.c from top-level common-user: Adjust system call return on FreeBSD common-user: Move safe-syscall.* from linux-user bsd-user: Create special-errno.h linux-user: Create special-errno.h linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h linux-user/host/sparc64: Add safe-syscall.inc.S linux-user/host/mips: Add safe-syscall.inc.S linux-user: Move syscall error detection into safe_syscall_base linux-user: Untabify all safe-syscall.inc.S Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu ↵Richard Henderson16-3099/+4997
into staging First RISC-V PR for QEMU 7.0 - Add support for ratified 1.0 Vector extension - Drop support for draft 0.7.1 Vector extension - Support Zfhmin and Zfh extensions - Improve kernel loading for non-Linux platforms # gpg: Signature made Sun 19 Dec 2021 08:56:08 PM PST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu: (88 commits) hw/riscv: Use load address rather than entry point for fw_dynamic next_addr target/riscv: Enable bitmanip Zb[abcs] instructions riscv: Set 5.4 as minimum kernel version for riscv32 target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions target/riscv: rvv-1.0: update opivv_vadc_check() comment target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm target/riscv: rvv-1.0: add vector unit-stride mask load/store insns target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() target/riscv: rvv-1.0: add vsetivli instruction target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 target/riscv: rvv-1.0: floating-point reciprocal estimate instruction target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction target/riscv: gdb: support vector registers for rv64 & rv32 target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid target/riscv: rvv-1.0: implement vstart CSR target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits target/riscv: rvv-1.0: narrowing floating-point/integer type-convert target/riscv: add "set round to odd" rounding mode helper function target/riscv: rvv-1.0: widening floating-point/integer type-convert target/riscv: rvv-1.0: floating-point/integer type-convert instructions ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20meson: Move bsd_user_ss to bsd-user/Richard Henderson2-3/+4
We have no need to reference bsd_user_ss outside of bsd-user. Go ahead and merge it directly into specific_ss. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20meson: Move linux_user_ss to linux-user/Richard Henderson2-3/+4
We have no need to reference linux_user_ss outside of linux-user. Go ahead and merge it directly into specific_ss. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20linux-user: Move thunk.c from top-levelRichard Henderson4-2/+1
So far, linux-user is the only user of these functions. Clean up the build machinery by restricting it to linux-user. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20common-user: Adjust system call return on FreeBSDRichard Henderson4-1/+44
FreeBSD system calls return positive errno. On the 4 hosts for which we have support, error is indicated by the C bit set or clear. Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20common-user: Move safe-syscall.* from linux-userRichard Henderson19-15/+42
Move linux-user safe-syscall.S and safe-syscall-error.c to common-user so that bsd-user can also use it. Also move safe-syscall.h to include/user/. Since there is nothing here that is related to the guest, as opposed to the host, build it once. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke1-3/+10
The original BBL boot method had the kernel embedded as an opaque blob that was blindly jumped to, which OpenSBI implemented as fw_payload. OpenSBI then implemented fw_jump, which allows the payload to be loaded elsewhere, but still blindly jumps to a fixed address at which the kernel is to be loaded. Finally, OpenSBI introduced fw_dynamic, which allows the previous stage to inform it where to jump to, rather than having to blindly guess like fw_jump, or embed the payload as part of the build like fw_payload. When used with an opaque binary (i.e. the output of objcopy -O binary), it matches the behaviour of the previous methods. However, when used with an ELF, QEMU currently passes on the ELF's entry point address, which causes a discrepancy compared with all the other boot methods if that entry point is not the first instruction in the binary. This difference specific to fw_dynamic with an ELF is not apparent when booting Linux, since its entry point is the first instruction in the binary. However, FreeBSD has a separate ELF entry point, following the calling convention used by its bootloader, that differs from the first instruction in the binary, used for the legacy SBI entry point, and so the specific combination of QEMU's default fw_dynamic firmware with booting FreeBSD as an ELF rather than a raw binary does not work. Thus, align the behaviour when loading an ELF with the behaviour when loading a raw binary; namely, use the base address of the loaded kernel in place of the entry point. The uImage code is left as-is in using the U-Boot header's entry point, since the calling convention for that entry point is the same as the SBI one and it mirrors what U-Boot will do. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211214032456.70203-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta1-4/+4
The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20riscv: Set 5.4 as minimum kernel version for riscv32Khem Raj1-1/+2
5.4 is first stable API as far as rv32 is concerned see [1] [1] https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989 Signed-off-by: Khem Raj <raj.khem@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <alistair.francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Message-Id: <20211216073111.2890607-1-raj.khem@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2-6/+13
SEW has the limitation which cannot exceed ELEN. Widening instructions have a destination group with EEW = 2*SEW and narrowing instructions have a source operand with EEW = 2*SEW. Both of the instructions have the limitation of: 2*SEW <= ELEN. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-78-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang1-1/+1
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-77-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and ↵Frank Chang4-8/+8
vmorn.mm Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang4-0/+67
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang1-18/+18
Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2-0/+29
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang1-2/+2
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang4-0/+197
Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-71-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate ↵Frank Chang4-0/+189
instruction Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-70-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang3-0/+187
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-69-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang1-0/+22
If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trigger illegal instruction exception if frm field contains invalid value at run-time for vector floating-point instructions. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-68-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang5-103/+199
* Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads) to raise the memory access exception at the exact processed vector element. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang3-4/+4
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-66-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang4-44/+97
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-65-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang4-0/+14
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-64-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang4-14/+63
Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-63-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2-36/+59
Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-62-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang3-15/+24
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-61-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang1-12/+12
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-60-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2-24/+0
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-59-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang4-17/+0
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-58-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2025-02-05 06:35:12 +0000