| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
The xbzrel and vcpu_dirty_limit are the two slowest tests from
migration-test. Move them under g_test_slow() to save about 40s per
run.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Link: https://lore.kernel.org/r/20240911145204.17692-1-farosas@suse.de
Signed-off-by: Peter Xu <peterx@redhat.com>
|
|
Pull request
An integer overflow fix for the last zone on a zoned block device whose
capacity is not a multiple of the zone size.
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmbpa0sACgkQnKSrs4Gr
# c8hdAwgAgp6AJVXHiPo43GbhdSsKJ2bq8DIPrsqgwAxD3rgxxRVwsWzENQgzF8O9
# qoXPmU0eqPp0zTsKTxNrlIgCpsJ3X4Oeg89u4N1xUOAJtADZGlbucUQEkAgIhWMl
# IFLjtFc7EbhWn57FmQGzANeOJOB+OumfQGeC7wbeAtUCn7g08rXtq+5I5GRKqkkP
# u1FlSassd7fyVnlVc+BT2aKANBITKhJGhYqwndvxXzMIi0L54/bQRrarLoy7oJuG
# 1k8zYLi6giUINNwYMtzn5ooXNnOSoxHKKfwcFT8hGZixwBBnCnYHjNkfs/QyvZQ7
# ZuR9mY6pqp/lg5127UlpOR7d6HADLQ==
# =709Z
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 17 Sep 2024 12:43:07 BST
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full]
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
hw/block: fix uint32 overflow
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
staging
* Make all qtest targets work with "--without-default-devices"
* Replace assert(0) and assert(false) in qtests and s390x code
* Enable the device aliases for or1k
* Some other small test improvements
# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmbpWwwRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbUj2A//VQwwbbuQa4FO/fu8mX0/iL43IZPLkVvC
# XPesidMwEsaNlfnUGLwjr9/F9sU7NXSkEdBWshU69ER9D4FPvRlZ6xOc0GB2HHEm
# 2zYBaQoMvB/g5/FMkp5/YqPc/FvYMxePTX0syJCUkdf9hbM3YJagUgSKaz/2ZJRu
# +wztsRMSGx9WBeabTWgbAtGlfEqtfSGdfFHbNtoEVmO/K3rvcAHJhPXZpSmdq4CV
# ymwYQ3Ul1Sdz/34TzshhkY9VvYU6n1zuB+kGrjPcQrOdBV/ukJuBiFkHfSZm/2ch
# zTqbdXvkds867vHMo9s3JeVKPa8ZytKn4ycXXgVS5AZtrnEnyHztlVHWbwbHSafF
# rVGXnE3FabzKL4sEKGzOjMegnwdWtpBNwMVKUZIgURqDXAVVR2m+lf2pW/Niz2WR
# m0LNIcg0NPvxPwuq1xLVHc3CLNSCszu4Ao5YRhKimf3hb+FvzHty3dxn+DDg4+Q4
# hHqQRcbWILhYJEwcAVkfaMTtCh/RESiNi0U7Teqvr+aqBsJP8kdCkE5rY7cqzrqn
# aDaompDZ8QG1QA1c3NaxtmNsvTvpm8gBySrqbMizo8UHQd85HDdXFkAZfI4HWKDi
# jhZAEyh1HLeXrgDT/D0WBWQdPLjDZewTvqgqT/A5XbdR1u4XYXcxwMCpIN1iKFoY
# 8qu0hIcsILM=
# =DXEK
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 17 Sep 2024 11:33:48 BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2024-09-17' of https://gitlab.com/thuth/qemu:
.gitlab-ci.d/crossbuilds.yml: Force 'make check' to -j2 for cross-i686-tci
tests/functional: Move the mips64el fuloong2e test into the thorough category
docs/fuzz: fix outdated mention to enable-sanitizers
system: Enable the device aliases for or1k, too
system: Sort QEMU_ARCH_VIRTIO_PCI definition
tests/qtest: remove break after g_assert_not_reached()
tests/qtest: replace assert(false) with g_assert_not_reached()
include/hw/s390x: replace assert(false) with g_assert_not_reached()
tests/unit: replace assert(0) with g_assert_not_reached()
tests/qtest: replace assert(0) with g_assert_not_reached()
gitlab: fix logic for changing docker tag on stable branches
.gitlab-ci.d/buildtest: Build most targets in the build-without-defaults job
tests/qtest: Disable numa-test if the default machine is not available
tests/qtest/meson.build: Add more CONFIG switches checks for the x86 tests
tests/qtest/hd-geo-test: Check for availability of "pc" machine before using it
tests/qtest/boot-order-test: Make the machine name mandatory in this test
tests/qtest/cdrom-test: Improve the machine detection in the cdrom test
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
vfio queue:
* Support for IGDs of gen 11 and later
* Coverity fixes
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmbpWl0ACgkQUaNDx8/7
# 7KFYJhAAu8Dyf96RUr4ucu/VaSlTi/rk/i5sivD4EXiCOf2qpQtyoo+C8DJmjAZg
# nC+4IpD2vu2C/xaZoQ4o6uQL7c45dOup59jcbKO+6NekF521Y6aq9OvE5v55CAwu
# R38UWI6ZX5qqyU/tA39/s7migIvCtK7VgTzEs2Lpzw8WetCFattvrEiKHt09fNdX
# kSPdFVV6FymOowAekQtI2JACr8C5nm8x9npzyL1SjauvWA70aOU9h1iHoIxHGKFF
# jlotd6v16c0Z260AUP/RDBwf8wqg2MtwBOI3qVGYD20Xd7tRQkLlFp8X5lNw4pHr
# eylqqxW3E4LJ4vSWpi4Jj2tZN5tZl8X927ew79D2gf69R8f1l+5CG/qqynMRbZ0b
# gE1E5UNfEkXYX9PMuf2uenoiahMxh7ZHwzJmtFcTLGyHGudSaUu3S7Yu5a1R0ZDf
# 8OyzE1E1X/8uCABvSgPphtSfYD9kXKiwNJSPrj3PZ1nXgNoA6BDi5sOeTPm0POBA
# IfB10VEXDd61KPFKGQqZ1Qqrvb0LsCTvFTwCHRHBEB/F/ykwTX9dzrTInkTBTiQU
# OyDjKZvR2ACjysuFxvpA2fhhF7KCmCwg7M/YsKyVLKq2r3TdBnDS1DHm7Z5ebNu4
# vgV4fsPCnjaQxOHEHZmh+rxG0E2dOGMiCieY9ooJ6jeomKQ+d60=
# =cIWS
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 17 Sep 2024 11:30:53 BST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-vfio-20240917' of https://github.com/legoater/qemu:
vfio/igd: correctly calculate stolen memory size for gen 9 and later
vfio/igd: don't set stolen memory size to zero
vfio/igd: add ID's for ElkhartLake and TigerLake
vfio/igd: add new bar0 quirk to emulate BDSM mirror
vfio/igd: use new BDSM register location and size for gen 11 and later
vfio/igd: support legacy mode for all known generations
vfio/igd: return an invalid generation for unknown devices
hw/vfio/pci.c: Use correct type in trace_vfio_msix_early_setup()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
https://gitlab.com/kraxel/qemu into staging
edk2: update to 2024-08 stable tag.
acpi: update test data (address changed due to firmware size change).
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmbpP4kACgkQTLbY7tPo
# cTjurg//WYI/pofJzsYaeYdMhFwuw1b64Hj0r50fjoOGEHiPQFLHGU9RpFmpEAKd
# lUfP+b3CztWDbK3gjRMt+1ah845SVG5VxdMPVL/F3eqKs2/eKD9ujcqIpNRGyX69
# x0e+FkohmrjCEyHNHBJjKOuqfkdqbQLtIvW1fLt8OzfsKGKvz9Kd4nZdIBX4PmDx
# sM7U44qnyLvM4AGf0QJY+v6vsqCSCy6LmgqF3vNdvnNeV09by4JvICXit486FqNK
# DrhFX16oJ/fSrJ03FSd/gps8o+YCSW7pm4Yo4GNAFX02XHCoO/lS+QraA9vs4raC
# 1FduQgV6pceR667SjuAiHsCyewVUlz7bdXgCCUtFFUzPmcBzYyOcwmEh4d15quD0
# kTiopy3Q52v2t688Se2iv08vs3sVLVCtti2UAntvhSTjVOOFUhMuNRuA4gbAk+2K
# 71sixGgbVv5+woLV1YHqJR3swSXUMD/4RglJMKjC829CWCHOOQ1lY6qgjFlj8U8+
# uSW4Kq9Mq2ORnH/8egr3ctV6uPZHq6uQt+zyzYVm5m2DmnJMFCrlMt7ABOzsVWKs
# N1Q3QEbUXqotzicCu9JHisKwp90kVp+rWgy+98xxk2P3JbiYrla31HeJPVRw4BM+
# uhphdzzUKGLrtWP8PCw+alSfW+Yt3olD87IBXOKlviah2fW9qWg=
# =4kSg
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 17 Sep 2024 09:36:25 BST
# gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* tag 'edk2-stable202408-20240917-pull-request' of https://gitlab.com/kraxel/qemu:
tests/acpi: disallow acpi test data updates
tests/acpi: update aarch64/virt/SSDT.memhp
add loongarch binaries for edk2-stable202408
roms: Support compile the efi bios for loongarch
update binaries to edk2-stable202408
update submodule and version file to edk2-stable202408
tests/acpi: allow acpi test data updates
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
staging
aspeed queue:
* I2C support for AST2700
* Coverity fixes
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmbofzEACgkQUaNDx8/7
# 7KHo4g//RtzY1oM+5xbX7LA4Nb45EJtAs9+UvbvDF7++NF9Nd4VThdoyBSvzyqd8
# 9Z35Mfoh1xce7+Qz/QtobbRkPLKtq7rfmj4lCkXZRGR/0nbDteqyLOqDM/E/GSBc
# mEaMG9sT2L1t9SrKOYIhgoPSpS0kpJ0YHfMLt5DcTjLQ1g8OB7ByzOPoPSBzTPAf
# QLL/v0GTxdqQPRhcZJKGclkjeVwBtFpo1rbDe/tHfFKC51g3cROGyQEswuPxRqDB
# Y3CQ0WC7awqSg7WAUwTfyb6LNSmYoiycGKv/gi06kc/mxjpf2qQ2khX4diiPoOj0
# Ak1b/dv2DWKE8LDYw7ew44UdPyIhGhgFeYeJ1olz5oLUcdcd4PuBWBvLUgpJKEfk
# HRXcJyhat3rwWGYzrdCJbBPN6CPncWjyifg1X6jK6Eu4wnfdpB9m64xFg8TpALaz
# SRZGg0ahldBwU6jjDO3x/RMWzKCtzwAjDuLfxSlqDGPx5OL+0dDDEa+xj45VzzBZ
# aT5Kcy9ga9DgRUw4wds3NHz9uCxwXoktDkW3vKMeMdftAf6er+Inhe8FHer/JSh4
# wuCxUDYIUSate5QoVucHAAM3DqOCQ1ascugufluXAR4StJ/u2b3SXU881C7v4crP
# NDncQEsWgya+Ykv9lXgulDxZrc8qsSmj4aoRNtJHaGsxmb4RwSY=
# =NyK5
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 16 Sep 2024 19:55:45 BST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20240916' of https://github.com/legoater/qemu:
machine_aspeed.py: Update to test I2C for AST2700
aspeed: Add tmp105 in i2c bus 0 for AST2700
aspeed/soc: Support I2C for AST2700
aspeed/soc: Introduce a new API to get the device irq
hw/i2c/aspeed: Add support for 64 bit addresses
hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses
hw/i2c/aspeed: Add AST2700 support
hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus
hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus
hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus
hw/i2c/aspeed: Support discontinuous register memory region of I2C bus
hw/gpio/aspeed_gpio: Avoid shift into sign bit
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
In commit 1374ed49e1453c300 we forced the cross-i686-tci job to -j1 to
see if this helped with test timeouts. It seems to help with that but
on the other hand we now sometimes run into the overall 60 minute
job timeout. Try -j2 instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240916134913.2540486-1-peter.maydell@linaro.org
|
|
The product bs->bl.zone_size * (bs->bl.nr_zones - 1) may overflow
uint32.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Dmitry Frolov <frolov@swemel.ru>
Message-id: 20240917080356.270576-2-frolov@swemel.ru
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
|
|
In commit 1374ed49e1453c300 we forced the cross-i686-tci job to -j1 to
see if this helped with test timeouts. It seems to help with that but
on the other hand we now sometimes run into the overall 60 minute
job timeout. Try -j2 instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240916134913.2540486-1-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
Commit d2fce37597c2 added a test that downloads an asset from the
internet, so this test should not be run by default anymore and be
put into the thorough category instead.
Message-ID: <20240913175140.3329083-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This options has been removed at cb771ac1f5 (meson: Split
--enable-sanitizers to --enable-{asan, ubsan}, 2024-08-13), so let's
update its last standing mention in the docs.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-ID: <0ecf4e1ab26771009d74a2ce61e7c17ddc586ef7.1726226316.git.quic_mathbern@quicinc.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
Now that we've got a "virt" machine for or1k that supports PCI
too (commit 40fef82c4e "hw/openrisc: Add PCI bus support to virt")
we can also enable the virtio device aliases like we do on other
similar platforms. This will e.g. help to run the iotests with
qemu-system-or1k later.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240705090808.1305765-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240705124528.97471-3-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
Sort the QEMU_ARCH_VIRTIO_PCI to simplify adding/removing entries.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240705124528.97471-2-philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This patch is part of a series that moves towards a consistent use of
g_assert_not_reached() rather than an ad hoc mix of different
assertion mechanisms.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20240912073921.453203-36-pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This patch is part of a series that moves towards a consistent use of
g_assert_not_reached() rather than an ad hoc mix of different
assertion mechanisms.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20240912073921.453203-24-pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This patch is part of a series that moves towards a consistent use of
g_assert_not_reached() rather than an ad hoc mix of different
assertion mechanisms.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Message-ID: <20240912073921.453203-15-pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This patch is part of a series that moves towards a consistent use of
g_assert_not_reached() rather than an ad hoc mix of different
assertion mechanisms.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20240912073921.453203-14-pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This patch is part of a series that moves towards a consistent use of
g_assert_not_reached() rather than an ad hoc mix of different
assertion mechanisms.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20240912073921.453203-13-pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
This fixes:
commit e28112d00703abd136e2411d23931f4f891c9244
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: Thu Jun 8 17:40:16 2023 +0100
gitlab: stable staging branches publish containers in a separate tag
Due to a copy+paste mistake, that commit included "QEMU_JOB_SKIPPED"
in the final rule that was meant to be a 'catch all' for staging
branches.
As a result stable branches are still splattering dockers from the
primary development branch.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Tested-by: Michael Tokarev <mjt@tls.msk.ru>
Message-ID: <20240906140958.84755-1-berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
Now that all the qtests are able to deal with builds that use the
"--without-default-devices" configuration switch, we can add all
targets to the build-without-defaults job. But to avoid burning too
much CI cycles in this job, exclude some targets where we already
have similar test coverage by a related target.
Message-ID: <20240905191434.694440-9-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
We have to update the calculation of the stolen memory size because
we've seen devices using values of 0xf0 and above for the graphics mode
select field. The new calculation was taken from the linux kernel [1].
[1] https://github.com/torvalds/linux/blob/7c626ce4bae1ac14f60076d00eafe71af30450ba/arch/x86/kernel/early-quirks.c#L455-L460
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
The stolen memory is required for the GOP (EFI) driver and the Windows
driver. While the GOP driver seems to work with any stolen memory size,
the Windows driver will crash if the size doesn't match the size
allocated by the host BIOS. For that reason, it doesn't make sense to
overwrite the stolen memory size. It's true that this wastes some VM
memory. In the worst case, the stolen memory can take up more than a GB.
However, that's uncommon. Additionally, it's likely that a bunch of RAM
is assigned to VMs making use of GPU passthrough.
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
ElkhartLake and TigerLake devices were tested in legacy mode with Linux
and Windows VMs. Both are working properly. It's likely that other Intel
GPUs of gen 11 and 12 like IceLake device are working too. However,
we're only adding known good devices for now.
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
The BDSM register is mirrored into MMIO space at least for gen 11 and
later devices. Unfortunately, the Windows driver reads the register
value from MMIO space instead of PCI config space for those devices [1].
Therefore, we either have to keep a 1:1 mapping for the host and guest
address or we have to emulate the MMIO register too. Using the igd in
legacy mode is already hard due to it's many constraints. Keeping a 1:1
mapping may not work in all cases and makes it even harder to use. An
MMIO emulation has to trap the whole MMIO page. This makes accesses to
this page slower compared to using second level address translation.
Nevertheless, it doesn't have any constraints and I haven't noticed any
performance degradation yet making it a better solution.
[1] https://github.com/projectacrn/acrn-hypervisor/blob/5c351bee0f6ae46250eefc07f44b4a31e770f3cf/devicemodel/hw/pci/passthrough.c#L650-L653
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
Intel changed the location and size of the BDSM register for gen 11
devices and later. We have to adjust our emulation for these devices to
properly support them.
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
We're soon going to add support for legacy mode to ElkhartLake and
TigerLake devices. Those are gen 11 and 12 devices. At the moment, all
devices identified by our igd_gen function do support legacy mode. This
won't change when adding our new devices of gen 11 and 12. Therefore, it
makes more sense to accept legacy mode for all known devices instead of
maintaining a long list of known good generations. If we add a new
generation to igd_gen which doesn't support legacy mode for some reason,
it'll be easy to advance the check to reject legacy mode for this
specific generation.
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
Intel changes it's specification quite often e.g. the location and size
of the BDSM register has change for gen 11 devices and later. This
causes our emulation to fail on those devices. So, it's impossible for
us to use a suitable default value for unknown devices. Instead of
returning a random generation value and hoping that everthing works
fine, we should verify that different devices are working and add them
to our list of known devices.
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
|
|
The tracepoint trace_vfio_msix_early_setup() uses "int" for the type
of the table_bar argument, but we use this to print a uint32_t.
Coverity warns that this means that we could end up treating it as a
negative number.
We only use this in printing the value in the tracepoint, so
mishandling it as a negative number would be harmless, but it's
better to use the right type in the tracepoint. Use uint64_t to
match how we print the table_offset in the vfio_msix_relo()
tracepoint.
Resolves: Coverity CID 1547690
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
Address (and checksum) change due to firmware image size change.
DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001)
[ ... ]
- Name (MEMA, 0x43C80000)
+ Name (MEMA, 0x43DA0000)
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
Added loongarch UEFI BIOS support to compiled scripts.
UEFI code images require 16M alignment, flash images require
16M alignment, under the loongarch architecture.This is agreed
upon when the firmware is loaded in QEMU under Loongarch.
The naming of UEFI under loongarch refers to the x86 and arm naming methods,
and the UEFI image names in x86 and arm are:
edk2-i386-code.fd
edk2-i386-vars.fd
edk2-arm-code.fd
edk2-arm-vars.fd
So on loongarch, we named it:
edk2-loongarch64-code.fd
edk2-loongarch64-vars.fd
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Message-ID: <20240724022245.1317884-1-lixianglai@loongson.cn>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
The numa-test needs a default machine in the target binary to work
successfully, so don't try to run this test if the corresponding
machine has not been enabled, e.g. when QEMU has been configured with
"--without-default-devices".
Message-ID: <20240905191434.694440-7-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
When configuring QEMU with "--without-default-devices", currently a lot
of the x86 qtests are failing since they silently assume that a certain
device or the i440fx pc machine is available. Add more checks for CONFIG
switches here to not run those tests in case the corresponding device is
not available.
Message-ID: <20240905191434.694440-6-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
In case QEMU has been configured with "--without-default-devices", the
"pc" machine type might be missing in the binary. We should check for
its availability before using it.
Message-ID: <20240905191434.694440-5-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
Let's make sure that we always pass a machine name to the test_boot_orders()
function, so we can check whether the machine is available in the binary
and skip the test in case it is not included in the build.
Message-ID: <20240905191434.694440-4-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
When configuring QEMU with the --without-default-devices switch, these
tests are currently failing since they assume that the "pc" and "q35"
machines are always available. Add some proper checks to make the test
work without these machines, too.
Message-ID: <20240905191434.694440-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
|
|
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
Add I2C model for AST2700 I2C support.
The I2C controller registers base address is start at
0x14C0_F000 and its address space is 0x2000.
The AST2700 I2C controller has one source INTC per bus.
I2C buses interrupt are connected to GICINT130_INTC
from bit 0 to bit 15.
I2C bus 0 is connected to GICINT130_INTC at bit 0.
I2C bus 15 is connected to GICINT130_INTC at bit 15.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
Currently, users can set the INTC mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous source numbers in the
same INTC orgate. To reduce the enumerated device id definition,
create a new API to get the INTC orgate input pin
if users only provide the device id with its bus number index.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 00000000" which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4_0000_0000" to
"0x5_FFFF_FFFF".
The DRAM offset range is from "0x0_0000_0000" to
"0x1_FFFF_FFFF" and it is enough to use bits [33:0]
saving the dram offset.
Therefore, save the high part physical address bit[1:0]
of Tx/Rx buffer address as dma_dram_offset bit[33:32].
It does not need to decrease the dram physical
high part address for DMA operation.
(high part physical address bit[7:0] – 4)
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 00000000" which
is 64bits address.
It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)"
registers to save the high part physical address of Tx/Rx
buffer address for master mode.
It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and
"Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers
to save the high part physical address of Tx/Rx buffer address
for slave mode.
Ex: Tx buffer address for master mode [39:0]
The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
bits [7:0] which corresponds the bits [39:32] of the 64 bits address of
the Tx buffer address.
The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0]
which corresponds the bits [31:0] of the 64 bits address
of the Tx buffer address.
Introduce a new has_dma64 class attribute and new registers for the
new mode to support DMA 64 bits dram address.
Update new mode register number to 28.
The aspeed_i2c_bus_vmstate is changed again and
version is not increased because it was done earlier in the same series.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
|
|
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus register and pool buffer from the datasheet.
An I2C controller registers owns 8KB address space.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
The "Current DMA Operating Address Status(0x50)" register of
I2C new mode has been removed in AST2700.
This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new
dma_dram_offset class attribute in AspeedI2Cbus to save the
current DMA operating address.
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 00000000" which
is 64bits address.
Set the dma_dram_offset data type to uint64_t for
64 bits dram address DMA support.
Both "DMA Mode Buffer Address Register(I2CD24 old mode)" and
"DMA Operating Address Status (I2CC50 new mode)" are used for showing the
low part dram offset bits [31:0], so change to read/write both register bits [31:0] in
bus register read/write functions.
The aspeed_i2c_bus_vmstate is changed again and version is not increased
because it was done earlier in the same series.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: Device 1 buffer
0x3A0 - 0x3BF: Device 2 buffer
0x4A0 - 0x4BF: Device 3 buffer
0x5A0 - 0x5BF: Device 4 buffer
0x6A0 - 0x6BF: Device 5 buffer
0x7A0 - 0x7BF: Device 6 buffer
0x8A0 - 0x8BF: Device 7 buffer
0x9A0 - 0x9BF: Device 8 buffer
0xAA0 - 0xABF: Device 9 buffer
0xBA0 - 0xBBF: Device 10 buffer
0xCA0 - 0xCBF: Device 11 buffer
0xDA0 - 0xDBF: Device 12 buffer
0xEA0 - 0xEBF: Device 13 buffer
0xFA0 – 0xFBF: Device 14 buffer
0x10A0 – 0x10BF: Device 15 buffer
Introduce a new class attribute to make user set each I2C bus
pool buffer gap size. Update formula to create all I2C bus
pool buffer memory regions.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
|
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
Besides, using a share pool buffer only support
pool buffer memory regions are continuous for all I2C bus.
To make this model more readable and support discontinuous
bus pool buffer memory regions, changes to introduce
a new bus pool buffer attribute in AspeedI2Cbus and
new memops. So, it does not need to calculate
the pool buffer offset for different I2C bus.
Introduce a new has_share_pool class attribute in AspeedI2CClass and
use it to create either a share pool buffer or bus pool buffers
in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500
and 0x20 for AST2600 and AST1030.
Incrementing the version of aspeed_i2c_bus_vmstate to 6.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
