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2014-06-10configure: duplicate/incorrect order of -lrtRick Liu1-3/+3
'-lrt' flag duplication/incorrect order would cause 'undefined reference to clock_gettime' error during compilation time. Before fix: ... -o qemu-bridge-helper qemu-bridge-helper.o -lrt -pthread -lgthread-2.0 -lrt -lglib-2.0 After fix: ... -o qemu-bridge-helper qemu-bridge-helper.o -pthread -lgthread-2.0 -lrt -lglib-2.0 Reference: http://hi.baidu.com/sanitywolf/item/7a8b69c1e76dd220a0b50ab1 Signed-off-by: Rick Liu <yrliu.ca@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-10libcacard: improve documentationPaolo Bonzini1-17/+63
Using the file-backed smartcard backend is black magic, but it can be useful if your only smartcard bricks itself if it is accessed the wrong way too many times. Complete the documentation to include the art of creating certificates and using them with QEMU, based on Ray Strode's useful tutorial at https://blogs.gnome.org/halfline/2013/09/08/another-smartcard-post/ but with ccid-card-emulated or vscclient instead of SPICE. Cc: Ray Strode <rstrode@redhat.com> Reviewed-by: Alon Levy <alevy@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-10libcacard: actually use symbols fileMichael Tokarev1-1/+1
libtool has an argument for .syms file, which is -export-symbols. There's no argument `-export-syms', and it looks like at least on linux, -export-syms is just ignored. Use the correct argument, -export-symbols, to actually get the right export list. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Alon Levy <alevy@redhat.com> Tested-by: Alon Levy <alevy@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-10libcacard: replace qemu thread primitives with glib onesMichael Tokarev3-30/+19
Replace QemuMutex with GMutex and QemuCond with GCond (with corresponding function changes), to make libcacard independent of qemu internal functions. After this step, none of libcacard internals use any qemu-provided symbols. Maybe it's a good idea to stop including qemu-common.h internally too. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Alon Levy <alevy@redhat.com> Tested-by: Alon Levy <alevy@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-10vscclient: use glib thread primitives not qemuMichael Tokarev1-33/+37
Use glib-provided thread primitives in vscclient instead of qemu ones, and do not use qemu sockets in there (open-code call to WSAStartup() for windows to initialize things). This way, vscclient becomes more stand-alone, independent on qemu internals. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Alon Levy <alevy@redhat.com> Tested-by: Alon Levy <alevy@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-10glib-compat.h: add new thread API emulation on top of pre-2.31 APIMichael Tokarev3-60/+138
Thread API changed in glib-2.31 significantly. Before that version, conditionals and mutexes were only allocated dynamically, using _new()/_free() interface. in 2.31 and up, they're allocated statically as regular variables, and old interface is deprecated. (Note: glib docs says the new interface is available since version 2.32, but it was actually introduced in version 2.31). Create the new interface using old primitives, by providing non-opaque definitions of the base types (GCond and GMutex) using GOnces. Replace #ifdeffery around GCond and GMutex in trace/simple.c and coroutine-gthread.c too because it does not work anymore with the new glib-compat.h. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> [Use GOnce to support lazy initialization; introduce CompatGMutex and CompatGCond. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-09Merge remote-tracking branch ↵Peter Maydell14-127/+731
'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging ---------------------------------------------------------------- target-arm queue: * support -bios option in vexpress boards * register the Cortex-A57 impdef system registers * fix handling of UXN bit in ARMv8 page tables * complete support of crypto insns in A32/T32 * implement CRC and crypto insns in A64 * fix bugs in generic timer control register ---------------------------------------------------------------- # gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140609-1: target-arm: Delete unused iwmmxt_msadb helper target-arm: Fix errors in writes to generic timer control registers target-arm: A64: Implement two-register SHA instructions target-arm: A64: Implement 3-register SHA instructions target-arm: A64: Implement AES instructions target-arm: A32/T32: Mask CRC value in calling code, not helper target-arm: A64: Implement CRC instructions target-arm: VFPv4 implies half-precision extension target-arm: Clean up handling of ARMv8 optional feature bits target-arm: Remove unnecessary setting of feature bits target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 target-arm: A64: Use PMULL feature bit for PMULL target-arm: add support for v8 VMULL.P64 instruction target-arm: Allow 3reg_wide undefreq to encode more bad size options target-arm: add support for v8 SHA1 and SHA256 instructions target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables target-arm: Prepare cpreg writefns/readfns for EL3/SecExt target-arm/cpu64.c: Actually register Cortex-A57 impdef registers vexpress: Add support for the -bios flag to provide firmware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell21-263/+195
into staging Tracing pull request # gpg: Signature made Mon 09 Jun 2014 14:44:18 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/tracing-pull-request: trace: Replace fprintf with error_report and print location trace: Multi-backend tracing trace: Replace error with warning if event is not defined simpletrace: add support for trace record pid field trace: add pid field to simpletrace record Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell3-13/+0
The iwmmxt_msadb helper and its corresponding gen function are unused; delete them. (This function appears to have never been used right back to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq, and is presumably an accidental remnant from the initial development.) Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401822125-1822-1-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell1-3/+3
The code for handling writes to the generic timer control registers had several bugs: * ISTATUS (bit 2) is read-only but we forced it to zero on any write * the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where it should be '^' * the handling of IMASK was inverted: we should set the IRQ if ISTATUS is set and IMASK is clear, not if both are set The combination of these bugs meant that when running a Linux guest that uses the generic timers we would fairly quickly end up either forgetting that the timer output should be asserted, or failing to set the IRQ when the timer was unmasked. The result is that the guest never gets any more timer interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell2-1/+46
Implement the two-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-10-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement 3-register SHA instructionsPeter Maydell1-1/+58
Implement the 3-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-9-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement AES instructionsPeter Maydell2-1/+51
Implement the AES instructions from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-8-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2-19/+16
Bring the 32-bit CRC helper functions into line with the A64 ones, by masking the high bytes of the value in the calling code rather than the helper. This is more efficient since we can determine the mask at translation time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-7-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell4-1/+86
Implement the optional A64 CRC instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-6-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell2-4/+1
VFPv4 implies the presence of the half-precision floating point extension (which is optional in VFPv3). Add this implied rule to arm_cpu_realizefn() and remove some no-longer-needed explicit setting of the bit in initfns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-5-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2-4/+14
CRC and crypto are both optional v8 extensions, so FEATURE_V8 should not imply them. Instead we should set these bits in the initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-4-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell2-4/+0
FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so we don't need to set them explicitly in initfns which set the V8 feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-3-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell1-3/+0
The arm_any_initfn() is used only for the 32-bit linux-user "cpu any", so it only gets called in builds where TARGET_AARCH64 is not defined. Remove the unreachable line which sets ARM_FEATURE_AARCH64. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-2-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell2-2/+2
Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for the A64 PMULL, not the AES feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell8-33/+61
Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication instruction in the A32/T32 instruction sets; this is part of the v8 Crypto Extensions. To do this we have to move the neon_pmull_64_{lo,hi} helpers from helper-a64.c into neon_helper.c so they can be used by the AArch32 translator. Inspired-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-4-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell1-12/+12
The current undefreq field in the neon_3reg_wide handling allows us to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is no longer sufficient with the advent of 64-bit polynomial VMULL, which means we want to UNDEF if size == 1. Change the undefreq encoding to use separate bits for all of "UNDEF if size == 0", "UNDEF if size == 1" and "UNDEF if size == 2". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-3-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel6-7/+349
This adds support for the SHA1 and SHA256 instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org [PMM: * rebase * fix bad indent * add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case * use g_assert_not_reached() * don't re-extract bit 6 for the 2-reg-misc encodings * set the ELF HWCAP2 bits for the new features ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell1-9/+8
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can just treat this bit as UXN whenever we are in v8 mode. Also correctly extract the upper attributes from the PTE entry, the v8 version tried to avoid extracting the CONTIG bit and ended up with the upper bits being off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG bit. This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f" seen when modprobing modules under Linux. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Claudio Fontana <claudio.fontana@huawei.com> Cc: Rob Herring <robherring2@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler1-14/+14
This patch changes some readfns/writefns to use raw_write and raw_read functions, which use the fieldoffset specified in ARMCPRegInfo instead of directly accessing the field. This will simplify patches for EL3 & Security Extensions. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1401962428-14749-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell1-0/+1
cpu64.c contains a reginfo list for the impdef registers on the Cortex-A57; however we forgot to actually call define_arm_cp_regs(), so it was sitting there doing nothing. Remedy this omission. Message-id: 1401226259-23121-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09vexpress: Add support for the -bios flag to provide firmwareGrant Likely1-0/+13
Right now to run firmware inside the QEMU VExpress model requires padding out the firmware image to the size of the virtual flash and passing it in via the -pflash argument. If the firmware image is passed without padding, then QEMU will fail. Also, when passed as a -pflash argument, QEMU treats the file as persistent storage and will modify the file. The -bios flag provides the semantics that we want for providing a firmware image. This patch maps the contents of the -bios file into the address space at the boot flash location. Tested with the vexpress-a15 model and the Tianocore port. Signed-off-by: Grant Likely <grant.likely@linaro.org> Tested-by: Roy Franz <roy.franz@linaro.org> [PMM: folded long line, removed stray \n from error message, use correct variable for printing image name, exit(1) rather than 0] Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into ↵Peter Maydell5-37/+117
staging Net patches # gpg: Signature made Mon 09 Jun 2014 14:41:34 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/net-pull-request: e1000: remove broken support for 82573L tests: e1000: test additional device IDs e1000: allow command-line selection of card model vmxnet3: fix msix vectors unuse net: xilinx_ethlite: Fix Rx-pong interrupt Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09trace: Replace fprintf with error_report and print locationAlexey Kardashevskiy1-13/+18
This replaces fprintf(stderr) with error_report. This moves local variables to the beginning of the function to comply with QEMU's coding style. Suggested-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09trace: Multi-backend tracingLluís Vilanova20-234/+153
Adds support to compile QEMU with multiple tracing backends at the same time. For example, you can compile QEMU with: $ ./configure --enable-trace-backends=ftrace,dtrace Where 'ftrace' can be handy for having an in-flight record of events, and 'dtrace' can be later used to extract more information from the system. This patch allows having both available without recompiling QEMU. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09trace: Replace error with warning if event is not definedAlexey Kardashevskiy1-7/+7
At the moment QEMU exits if trace point is not defined which makes a developer life harder if he has to switch between branches with different traces implemented. This replaces error+exit wit WARNING if the tracepoint does not exist or not traceable. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09simpletrace: add support for trace record pid fieldStefan Hajnoczi1-11/+15
Extract the pid field from the trace record and print it. Change the trace record tuple from: (event_num, timestamp, arg1, ..., arg6) to: (event_num, timestamp, pid, arg1, ..., arg6) Trace event methods now support 3 prototypes: 1. <event-name>(arg1, arg2, arg3) 2. <event-name>(timestamp, arg1, arg2, arg3) 3. <event-name>(timestamp, pid, arg1, arg2, arg3) Existing script continue to work without changes, they only know about prototypes 1 and 2. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09trace: add pid field to simpletrace recordStefan Hajnoczi1-2/+6
It is useful to know the QEMU process ID when working with traces from multiple VMs. Although the trace filename may contain the pid, tools that aggregate traces or even trace globally need somewhere to record the pid. There is a reserved field in the trace event header struct that we can use. It is not necessary to bump the simpletrace file format version number because it has already been incremented for the QEMU 2.1 release cycle in commit "trace: [simple] Bump up log version number". Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09e1000: remove broken support for 82573LGabriel L. Somlo2-19/+0
Currently, e1000 support is based on the manual for the 8254xx model series. 82573x models are documented in a separate manual (see http://www.intel.com/content/dam/www/public/us/en/documents/manuals/pcie-gbe-controllers-open-source-manual.pdf) and the 82573L device ID no longer works correctly on either Linux (3.14.*) or Windows 7. This patch removes stale code claiming to support 82573L, cleaning up the code base for the remaining 8254xx model series. Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09tests: e1000: test additional device IDsGabriel L. Somlo1-7/+27
Update e1000-test.c to check all currently supported devices. Suggested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09e1000: allow command-line selection of card modelGabriel L. Somlo2-24/+102
Allow selection of different card models from the qemu command line, to better accomodate a wider range of guests. Signed-off-by: Romain Dolbeau <romain@dolbeau.org> Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09vmxnet3: fix msix vectors unuseJiri Pirko1-1/+1
In vmxnet3_cleanup_msix(), there is called msix_vector_unuse() with VMXNET3_MAX_INTRS. That is not correct since vector of value VMXNET3_MAX_INTRS was never used. Also all the used vectors are not un-used. So call vmxnet3_unuse_msix_vectors() instead which does the correct job. Signed-off-by: Jiri Pirko <jiri@resnulli.us> Acked-by: Dmitry Fleytman <dmitry@daynix.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09net: xilinx_ethlite: Fix Rx-pong interruptPeter Crosthwaite1-1/+2
There is no CTRL_I bit in the pong buffer control register. The CTRL_I bit from the ping buffer masks both ping and pong buffers. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell42-2401/+2826
staging Block pull request # gpg: Signature made Fri 06 Jun 2014 17:08:50 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: (42 commits) qapi: Extract qapi/block.json definitions qapi: Extract qapi/block-core.json definitions qapi: create two block related json modules qapi: Extract qapi/common.json definitions sheepdog: reload only header in a case of live snapshot sheepdog: fix vdi object update after live snapshot rbd: Fix leaks in rbd_start_aio() error path qemu-img: Document check exit codes block: fix wrong order in live block migration setup blockdev: acquire AioContext in block_set_io_throttle throttle: add detach/attach test case throttle: add throttle_detach/attach_aio_context() dataplane: Support VIRTIO_BLK_T_SCSI_CMD virtio-blk: Factor out virtio_blk_handle_scsi_req from virtio_blk_handle_scsi virtio-blk: Allow config-wce in dataplane block: Move declaration of bdrv_get_aio_context to block.h raw-posix: drop raw_get_aio_fd() since it is no longer used dataplane: implement async flush dataplane: delete IOQueue since it is no longer used dataplane: use the QEMU block layer for I/O ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09slirp/arp: do not special-case bogus IP addressesSamuel Thibault2-9/+6
Do not special-case addresses with zero host part, as we do not necessarily know how big it is, and the guest can fake them anyway. Silently avoid having 0.0.0.0 as a destination, however. Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org> [Edgar: Minor change to subject] Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-06-09target-cris/translate.c: Remove _t_gen_mov_TN_env and _t_gen_mov_env_TNPeter Maydell1-17/+2
The wrapper functions _t_gen_mov_TN_env and _t_gen_mov_env_TN are only used via their accompanying non-underscore macros. The check they add on offset is thus pointless, since the compiler will complain if the struct field passed to the macro is not part of the struct. Remove the functions and make the macros directly expand to the appropriate tcg_gen_{ld,st}_tl calls. This conveniently avoids a warning due to _t_gen_mov_TN_env() being unused. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09target-cris/translate.c: Remove t_gen_mov_TN_reg and t_gen_mov_reg_TNPeter Maydell2-19/+4
Remove the t_gen_mov_TN_reg and t_gen_mov_reg_TN wrappers: the latter is completely unused, and the former only used in a few places (which are thus inconsistent with the rest of the decoder which directly accesses cpu_R[]). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09intc: xilinx_uartlite: Convert SBD::init -> instance_initPeter Crosthwaite1-10/+7
SysBusDevice::init is depracated. Convert to Object::init as prescribed by QOM conventions. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09char: xilinx_uartlite: Convert to realize()Peter Crosthwaite1-10/+14
SysBusDevice::init is depracated. Convert to Object::init and Device::realize as prescribed by QOM conventions. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09char: xilinx_uartlite: Don't reset from initPeter Crosthwaite1-1/+7
This refresh of the device state is intended to be a reset side effect. Move it to a proper reset handler rather than do it at init time. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09net: xilinx_ethlite: Convert to realize()Peter Crosthwaite1-11/+14
SysBusDevice::init is depracated. Convert to Object::init and Device::realize as prescribed by QOM conventions. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09net: xilinx_ethlite: Don't reset from initPeter Crosthwaite1-1/+8
This zeroing-out of the rxbuf variable (ping pong state) is a reset side effect. Extract into a proper reset. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-09timer: xilinx_timer: Convert to realize()Peter Crosthwaite1-8/+12
SysBusDevice::init is depracated. Convert to Object::init and Device::realize as prescribed by QOM conventions. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2014-06-06qapi: Extract qapi/block.json definitionsBenoît Canet2-159/+159
Signed-off-by: Benoit Canet <benoit@irqsave.net> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-06qapi: Extract qapi/block-core.json definitionsBenoît Canet2-1406/+1406
Signed-off-by: Benoit Canet <benoit@irqsave.net Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
generated by cgit v1.1 at 2024-11-19 23:41:36 +0000