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2017-03-06spapr: ensure that all threads within core are on the same NUMA nodeIgor Mammedov1-8/+15
Threads within a core shouldn't be on different NUMA nodes, so if user has misconfgured command line, fail QEMU at start up to force user fix it. For now use the first thread on the core as source of core's node-id. Later when cpu-numa refactoring lands it will be switched to core's node-id from possible_cpus[]. This prevents the same problems as commit 20bb648d "spapr: Fix default NUMA node allocation for threads", but for the case of manually configured NUMA node mappings, instead of just the default case. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-06ppc/xics: register reset handlers for the ICP and ICS objectsCédric Le Goater3-11/+16
The recent changes on the XICS layer removed the XICSState object to let the sPAPR machine handle the ICP and ICS directly. The reset of these objects was previously handled by XICSState, which was a SysBus device, and to keep the same behavior, the ICP and ICS were assigned to SysbBus. But that broke the 'info qtree' command in the monitor. 'qtree' performs a loop on the children of a bus to print their properties and SysBus devices are expected to be found under SysBus, which is not the case anymore. The fix for this problem is to register reset handlers for the ICP and ICS objects and stop using SysBus for such devices. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-04Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170303' ↵Peter Maydell22-495/+735
into staging ppc patch queuye for 2017-03-03 This will probably be my last pull request before the hard freeze. It has some new work, but that has all been posted in draft before the soft freeze, so I think it's reasonable to include in qemu-2.9. This batch has: * A substantial amount of POWER9 work * Implements the legacy (hash) MMU for POWER9 * Some more preliminaries for implementing the POWER9 radix MMU * POWER9 has_work * Basic POWER9 compatibility mode handling * Removal of some premature tests * Some cleanups and fixes to the existing MMU code to make the POWER9 work simpler * A bugfix for TCG multiply adds on power * Allow pseries guests to access PCIe extended config space This also includes a code-motion not strictly in ppc code - moving getrampagesize() from ppc code to exec.c. This will make some future VFIO improvements easier, Paolo said it was ok to merge via my tree. # gpg: Signature made Fri 03 Mar 2017 03:20:36 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.9-20170303: target/ppc: rewrite f[n]m[add,sub] using float64_muladd spapr: Small cleanup of PPC MMU enums spapr_pci: Advertise access to PCIe extended config space target/ppc: Rework hash mmu page fault code and add defines for clarity target/ppc: Move no-execute and guarded page checking into new function target/ppc: Add execute permission checking to access authority check target/ppc: Add Instruction Authority Mask Register Check hw/ppc/spapr: Add POWER9 to pseries cpu models target/ppc/POWER9: Add cpu_has_work function for POWER9 target/ppc/POWER9: Add POWER9 pa-features definition target/ppc/POWER9: Add POWER9 mmu fault handler target/ppc: Don't gen an SDR1 on POWER9 and rework register creation target/ppc: Add patb_entry to sPAPRMachineState target/ppc/POWER9: Add POWERPC_MMU_V3 bit powernv: Don't test POWER9 CPU yet exec, kvm, target-ppc: Move getrampagesize() to common code target/ppc: Add POWER9/ISAv3.00 to compat_table Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-04ppc: avoid typedef redefinitionsPaolo Bonzini2-3/+2
These cause compilation failures on CentOS 6 or other operating systems with older GCCs. Cc: David Gibson <dgibson@redhat.com> Cc: qemu-ppc@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1488558530-21016-3-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-04nios2: avoid anonymous unions in designated initializers.Paolo Bonzini1-18/+18
These cause compilation failures on CentOS 6 or other operating systems with older GCCs. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-04hppa: avoid anonymous unions in designated initializers.Paolo Bonzini1-33/+33
These cause compilation failures on CentOS 6 or other operating systems with older GCCs. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1488558530-21016-1-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell32-392/+428
* kernel header update (requested by David and Vijay) * GuestPanicInformation fixups (Anton) * record/replay icount fixes (Pavel) * cpu-exec cleanup, unification of icount_decr with tcg_exit_req (me) * KVM_CAP_IMMEDIATE_EXIT support (me) * vmxcap update (me) * iscsi locking fix (me) * VFIO ram device fix (Yongji) * scsi-hd vs. default CD-ROM (Hervé) * SMI migration fix (Dave) * spice-char segfault (Li Qiang) * improved "info mtree -f" (me) # gpg: Signature made Fri 03 Mar 2017 15:43:04 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (21 commits) iscsi: fix missing unlock memory: show region offset and ROM/RAM type in "info mtree -f" x86: Work around SMI migration breakages spice-char: fix segfault in char_spice_finalize vl: disable default cdrom when using explicitely scsi-hd memory: Introduce DEVICE_HOST_ENDIAN for ram device qmp-events: fix GUEST_PANICKED description formatting qapi: flatten GuestPanicInformation union vmxcap: update for September 2016 SDM vmxcap: port to Python 3 KVM: use KVM_CAP_IMMEDIATE_EXIT kvm: use atomic_read/atomic_set to access cpu->exit_request KVM: move SIG_IPI handling to kvm-all.c KVM: do not use sigtimedwait to catch SIGBUS KVM: remove kvm_arch_on_sigbus cpus: reorganize signal handling code KVM: x86: cleanup SIGBUS handlers cpus: remove ugly cast on sigbus_handler cpu-exec: remove unnecessary check of cpu->exit_request replay: check icount in cpu exec loop ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03iscsi: fix missing unlockPaolo Bonzini1-0/+4
Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03memory: show region offset and ROM/RAM type in "info mtree -f"Paolo Bonzini1-7/+18
"info mtree -f" output is currently hard to use for large RAM regions, because there is no hint as to what part of the region is being mapped. Add the offset if it is nonzero. Secondly, FlatView has a readonly field, that can override the MemoryRegion in the presence of aliases. Take it into account. Together, with this patch this: address-space (flat view): KVM-SMRAM 0000000000000000-00000000000bffff (prio 0, ram): pc.ram 00000000000c0000-00000000000c9fff (prio 0, ram): pc.ram 00000000000ca000-00000000000ccfff (prio 0, ram): pc.ram 00000000000cd000-00000000000ebfff (prio 0, ram): pc.ram 00000000000ec000-00000000000effff (prio 0, ram): pc.ram 00000000000f0000-00000000000fffff (prio 0, ram): pc.ram 0000000000100000-00000000bfffffff (prio 0, ram): pc.ram 00000000fd000000-00000000fdffffff (prio 1, ram): vga.vram 00000000febc0000-00000000febdffff (prio 1, i/o): e1000-mmio 00000000febf0400-00000000febf041f (prio 0, i/o): vga ioports remapped 00000000febf0500-00000000febf0515 (prio 0, i/o): bochs dispi interface 00000000febf0600-00000000febf0607 (prio 0, i/o): qemu extended regs 00000000fec00000-00000000fec00fff (prio 0, i/o): kvm-ioapic 00000000fed00000-00000000fed003ff (prio 0, i/o): hpet 00000000fee00000-00000000feefffff (prio 4096, i/o): kvm-apic-msi 00000000fffc0000-00000000ffffffff (prio 0, rom): pc.bios 0000000100000000-000000013fffffff (prio 0, ram): pc.ram becomes this: address-space (flat view): KVM-SMRAM 0000000000000000-00000000000bffff (prio 0, ram): pc.ram 00000000000c0000-00000000000c9fff (prio 0, rom): pc.ram @00000000000c0000 00000000000ca000-00000000000ccfff (prio 0, ram): pc.ram @00000000000ca000 00000000000cd000-00000000000ebfff (prio 0, rom): pc.ram @00000000000cd000 00000000000ec000-00000000000effff (prio 0, ram): pc.ram @00000000000ec000 00000000000f0000-00000000000fffff (prio 0, rom): pc.ram @00000000000f0000 0000000000100000-00000000bfffffff (prio 0, ram): pc.ram @0000000000100000 00000000fd000000-00000000fdffffff (prio 1, ram): vga.vram 00000000febc0000-00000000febdffff (prio 1, i/o): e1000-mmio 00000000febf0400-00000000febf041f (prio 0, i/o): vga ioports remapped 00000000febf0500-00000000febf0515 (prio 0, i/o): bochs dispi interface 00000000febf0600-00000000febf0607 (prio 0, i/o): qemu extended regs 00000000fec00000-00000000fec00fff (prio 0, i/o): kvm-ioapic 00000000fed00000-00000000fed003ff (prio 0, i/o): hpet 00000000fee00000-00000000feefffff (prio 4096, i/o): kvm-apic-msi 00000000fffc0000-00000000ffffffff (prio 0, rom): pc.bios 0000000100000000-000000013fffffff (prio 0, ram): pc.ram @00000000c0000000 This should make it easier to understand what's going on. Cc: Peter Xu <peterx@redhat.com> Cc: "William Tambe" <tambewilliam@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03x86: Work around SMI migration breakagesDr. David Alan Gilbert4-1/+15
Migration from a 2.3.0 qemu results in a reboot on the receiving QEMU due to a disagreement about SM (System management) interrupts. 2.3.0 didn't have much SMI support, but it did set CPU_INTERRUPT_SMI and this gets into the migration stream, but on 2.3.0 it never got delivered. ~2.4.0 SMI interrupt support was added but was broken - so that when a 2.3.0 stream was received it cleared the CPU_INTERRUPT_SMI but never actually caused an interrupt. The SMI delivery was recently fixed by 68c6efe07a, but the effect now is that an incoming 2.3.0 stream takes the interrupt it had flagged but it's bios can't actually handle it(I think partly due to the original interrupt not being taken during boot?). The consequence is a triple(?) fault and a reboot. Tested from: 2.3.1 -M 2.3.0 2.7.0 -M 2.3.0 2.8.0 -M 2.3.0 2.8.0 -M 2.8.0 This corresponds to RH bugzilla entry 1420679. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170223133441.16010-1-dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03spice-char: fix segfault in char_spice_finalizeLi Qiang1-1/+4
In 'qemu_chr_open_spice_vmc' if the 'psubtype' is NULL, it will call 'char_spice_finalize'. But as the SpiceChardev is not inserted in the 'spice_chars' list, the 'QLIST_REMOVE' will cause a segfault. Add a detect to avoid it. Signed-off-by: Li Qiang <liqiang6-s@360.cn> Message-Id: <1487665107-88004-1-git-send-email-liqiang6-s@360.cn> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Li Qiang <liq3ea@gmail.com>
2017-03-03vl: disable default cdrom when using explicitely scsi-hdHervé Poussineau1-0/+1
In commit af6bf1328ef90fae617857c02697e0174b84d596 (May 2011), ide-hd, ide-cd and scsi-cd have been added to disable default cdrom, "or else you can't put one on secondary master without -nodefaults". Make it the same for scsi-hd, so you can put one on scsi-id 2 without using -nodefaults. scsi-hd has probably been forgotten, as it has been added in the preceding commit (b443ae67130d32ad06b06fc9aa6d04d05ccd93ce). Affected users are the ones using a machine with SCSI devices and start QEMU with -device scsi-hd but without -device scsi-cd or -cdrom In that case, the default cdrom device will disappear instead of being empty. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <1487623279-29930-1-git-send-email-hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03memory: Introduce DEVICE_HOST_ENDIAN for ram deviceYongji Xie2-1/+7
At the moment ram device's memory regions are DEVICE_NATIVE_ENDIAN. It's incorrect. This memory region is backed by a MMIO area in host, so the uint64_t data that MemoryRegionOps read from/write to this area should be host-endian rather than target-endian. Hence, current code does not work when target and host endianness are different which is the most common case on PPC64. To fix it, this introduces DEVICE_HOST_ENDIAN for the ram device. This has been tested on PPC64 BE/LE host/guest in all possible combinations including TCG. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yongji Xie <xyjxie@linux.vnet.ibm.com> Message-Id: <1488171164-28319-1-git-send-email-xyjxie@linux.vnet.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03qmp-events: fix GUEST_PANICKED description formattingAnton Nefedov1-2/+2
Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Eric Blake <eblake@redhat.com> Message-Id: <1487614915-18710-4-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03qapi: flatten GuestPanicInformation unionAnton Nefedov3-15/+24
Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Eric Blake <eblake@redhat.com> Message-Id: <1487614915-18710-3-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03vmxcap: update for September 2016 SDMPaolo Bonzini1-0/+9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03vmxcap: port to Python 3Paolo Bonzini1-7/+7
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03KVM: use KVM_CAP_IMMEDIATE_EXITPaolo Bonzini1-4/+42
The purpose of the KVM_SET_SIGNAL_MASK API is to let userspace "kick" a VCPU out of KVM_RUN through a POSIX signal. A signal is attached to a dummy signal handler; by blocking the signal outside KVM_RUN and unblocking it inside, this possible race is closed: VCPU thread service thread -------------------------------------------------------------- check flag set flag raise signal (signal handler does nothing) KVM_RUN However, one issue with KVM_SET_SIGNAL_MASK is that it has to take tsk->sighand->siglock on every KVM_RUN. This lock is often on a remote NUMA node, because it is on the node of a thread's creator. Taking this lock can be very expensive if there are many userspace exits (as is the case for SMP Windows VMs without Hyper-V reference time counter). KVM_CAP_IMMEDIATE_EXIT provides an alternative, where the flag is placed directly in kvm_run so that KVM can see it: VCPU thread service thread -------------------------------------------------------------- raise signal signal handler set run->immediate_exit KVM_RUN check run->immediate_exit The previous patches changed QEMU so that the only blocked signal is SIG_IPI, so we can now stop using KVM_SET_SIGNAL_MASK and sigtimedwait if KVM_CAP_IMMEDIATE_EXIT is available. On a 14-VCPU guest, an "inl" operation goes down from 30k to 6k on an unlocked (no BQL) MemoryRegion, or from 30k to 15k if the BQL is involved. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03kvm: use atomic_read/atomic_set to access cpu->exit_requestPaolo Bonzini1-3/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03KVM: move SIG_IPI handling to kvm-all.cPaolo Bonzini4-76/+63
This lets us remove a bunch of CONFIG_LINUX defines. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03KVM: do not use sigtimedwait to catch SIGBUSPaolo Bonzini8-44/+53
Call kvm_on_sigbus_vcpu asynchronously from the VCPU thread. Information for the SIGBUS can be stored in thread-local variables and processed later in kvm_cpu_exec. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03KVM: remove kvm_arch_on_sigbusPaolo Bonzini7-58/+13
Build it on kvm_arch_on_sigbus_vcpu instead. They do the same for "action optional" SIGBUSes, and the main thread should never get "action required" SIGBUSes because it blocks the signal. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03cpus: reorganize signal handling codePaolo Bonzini3-44/+43
Move the KVM "eat signals" code under CONFIG_LINUX, in preparation for moving it to kvm-all.c; reraise non-MCE SIGBUS immediately, without passing it to KVM. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03KVM: x86: cleanup SIGBUS handlersPaolo Bonzini1-39/+42
This patch should have no semantic change. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03cpus: remove ugly cast on sigbus_handlerPaolo Bonzini6-56/+65
The cast is there because sigbus_handler is invoked via sigfd_handler. But it feels just wrong to use struct qemu_signalfd_siginfo in the prototype of a function that is passed to sigaction. Instead, do a simple-minded conversion of qemu_signalfd_siginfo to siginfo_t. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03Merge branch 'icount-update' into HEADPaolo Bonzini7-100/+79
Merge the original development branch due to breakage caused by the MTTCG merge. Conflicts: cpu-exec.c translate-common.c Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-03-03Merge remote-tracking branch 'remotes/ehabkost/tags/numa-pull-request' into ↵Peter Maydell1-10/+28
staging NUMA documentation update # gpg: Signature made Fri 03 Mar 2017 13:11:25 GMT # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/numa-pull-request: qemu-options: Rewrite -numa documentation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03Merge remote-tracking branch ↵Peter Maydell4-1/+1
'remotes/dgibson/tags/submodule-update-20170303' into staging submodule updates (SLOF & dtc) 2017-03-03 This set of patches updates the SLOF and dtc submodules for qemu-2.9. The SLOF update could have gone in my ppc pull request earlier today, but I forgot it. It should be safe to apply in either order with that set though. The dtc (and libfdt) update brings us up to dtc 1.4.3 which includes some things that will be useful in future. # gpg: Signature made Fri 03 Mar 2017 06:29:31 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/submodule-update-20170303: Update dtc submodule to v1.4.3 pseries: Update SLOF firmware image Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03qemu-options: Rewrite -numa documentationEduardo Habkost1-10/+28
Rewrite the -numa documentation to clarify what exactly it does. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170123180632.28942-3-ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-03-03Merge remote-tracking branch 'remotes/berrange/tags/pull-qio-2017-02-27-2' ↵Peter Maydell1-56/+208
into staging Merge qio 2017/02/27 v2 # gpg: Signature made Thu 02 Mar 2017 16:09:27 GMT # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qio-2017-02-27-2: io: fully parse & validate HTTP headers for websocket protocol handshake tests: fix leaks in test-io-channel-command io: fix decoding when multiple websockets frames arrive at once Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03dtc: Revert unintentional submodule downgrade from commit 077dd74239a99Peter Maydell1-0/+0
Commit 077dd74239a99 inadvertently downgraded the 'dtc' submodule, undoing the increment added in commit 6e85fce0225f. Revert this, returning the submodule state to where we should be. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell31-133/+901
virtio, pc: fixes, features virtio support for region caches broke a bunch of stuff - fixing most of it though it's not ideal. Still pondering the right way to fix it. New: VM gen ID and hotplug for PXB. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 02 Mar 2017 06:19:17 GMT # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: hw/pxb-pcie: fix PCI Express hotplug support tests/acpi: update DSDT after last patch acpi: simplify _OSC virtio: unbreak virtio-pci with IOMMU after caching ring translations virtio: add missing region cache init in virtio_load() virtio: invalidate memory in vring_set_avail_event() virtio: guard vring access when setting notification virtio: check for vring setup in virtio_queue_empty MAINTAINERS: Add VM Generation ID entries tests: Move reusable ACPI code into a utility file qmp/hmp: add query-vm-generation-id and 'info vm-generation-id' commands ACPI: Add Virtual Machine Generation ID support ACPI: Add vmgenid blob storage to the build tables docs: VM Generation ID device description linker-loader: Add new 'write pointer' command Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-03Update dtc submodule to v1.4.3David Gibson1-0/+0
Since the last submodule update (which was v1.4.2) dtc and libfdt have gained some features which would be useful in qemu. There's now a v1.4.3 upstream release, so update our submodule to point to it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03pseries: Update SLOF firmware imageAlexey Kardashevskiy3-1/+1
Various fixes in this update, the full list is: > qemu-bootlist: Take the "-boot strict=off" setting properly into account > virtio-scsi: initialize vring avail queue buffers > virtio: Remove global variables in block and 9p driver > Remove superfluous checkpoints in tree.fs > Provide "write" function in the disk-label package > virtio: Implement block write support > scsi: Add SCSI block write support > deblocker: Add a 'write' function > virtio-scsi: Fix descriptor order for SCSI WRITE commands > board-qemu: Add a possibility to use hvterm input instead of USB keyboard > Do not try to use virtio-gpu in VGA mode > virtio: Fix stack comment of virtio-blk-read > envvar: Do not read default values for /options from the NVRAM anymore > envvar: Set properties in /options during "(set-defaults)" Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: rewrite f[n]m[add,sub] using float64_muladdNikunj A Dadhania1-167/+46
Use the softfloat api for fused multiply-add. Introduce routine to set the FPSCR flags VXNAN, VXIMZ nad VMISI. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03spapr: Small cleanup of PPC MMU enumsSam Bobroff6-72/+55
The PPC MMU types are sometimes treated as if they were a bit field and sometime as if they were an enum which causes maintenance problems: flipping bits in the MMU type (which is done on both the 1TB segment and 64K segment bits) currently produces new MMU type values that are not handled in every "switch" on it, sometimes causing an abort(). This patch provides some macros that can be used to filter out the "bit field-like" bits so that the remainder of the value can be switched on, like an enum. This allows removal of all of the "degraded" types from the list and should ease maintenance. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03spapr_pci: Advertise access to PCIe extended config spaceDavid Gibson1-0/+4
The (paravirtual) PCI host bridge on the 'pseries' machine in most regards acts like a regular PCI bus, rather than a PCIe bus. Despite this, though, it does allow access to the PCIe extended config space. We already implemented the RTAS methods to allow this access.. but forgot to put the markers into the device tree so that guest's know it is there. This adds them in. With this, a pseries guest is able to view extended config space on (for example an e1000e device. This should be enough to allow guests to use at least some PCIe devices. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: Rework hash mmu page fault code and add defines for claritySuraj Jitindar Singh2-14/+24
The hash mmu page fault handling code is responsible for generating ISIs and DSIs when access permissions cause an access to fail. Part of this involves setting the srr1 or dsisr registers to indicate what causes the access to fail. Add defines for the bit fields of these registers and rework the code to use these new defines in order to improve readability and code clarity. While we're here, update what is logged when an access fails to include information as to what caused to access to fail for debug purposes. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [dwg: Moved constants to cpu.h since they're not MMUv3 specific] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: Move no-execute and guarded page checking into new functionSuraj Jitindar Singh2-9/+17
A pte entry has bit fields which can be used to make a page no-execute or guarded, if either of these bits are set then an instruction access to this page will fail. Currently these bits are checked with the pp_prot function however the ISA specifies that the access authority controlled by the key-pp value pair should only be checked on an instruction access after the no-execute and guard bits have already been verified to permit the access. Move the no-execute and guard bit checking into a new separate function. Note that we can remove the check for the no-execute bit in the slb entry since this check was already performed above when we obtained the slb entry. In the event that the no-execute or guard bits are set, an ISI should be generated with the SRR1_NOEXEC_GUARD (0x10000000) bit set in srr1. Add a define for this for clarity. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [dwg: Move constants to cpu.h since they're not MMUv3 specific] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: Add execute permission checking to access authority checkSuraj Jitindar Singh1-5/+4
Basic storage protection defines various access authority permissions based on a slb storage key and pte pp value pair. This access authority defines read, write and execute permissions however currently we only use this to control read and write permissions and ignore the execute control. Fix the code to allow execute permissions based on the key-pp value pair. Execute is allowed under the same conditions which enable reads. (i.e. read permission -> execute permission) Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: Add Instruction Authority Mask Register CheckSuraj Jitindar Singh2-1/+45
The instruction authority mask register (IAMR) can be used to restrict permissions for instruction fetch accesses on a per key basis for each of 32 different key values. Access permissions are derived based on the specific key value stored in the relevant page table entry. The IAMR was introduced in, and is present in processors since, POWER8 (ISA v2.07). Thus introduce a function to check access permissions based on the pte key value and the contents of the IAMR when handling a page fault to ensure sufficient access permissions for an instruction fetch. A hash pte contains a key value in bits 2:3|52:54 of the second double word of the pte, this key value gives an index into the IAMR which contains 32 2-bit access masks. If the least significant bit of the 2-bit access mask corresponding to the given key value is set (IAMR[key] & 0x1 == 0x1) then the instruction fetch is not permitted and an ISI is generated accordingly. While we're here, add defines for the srr1 bits to be set for the ISI for clarity. e.g. pte: dw0 [XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX] dw1 [XX01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXXX] ^^ ^^^ key = 01010 (0x0a) IAMR: [XXXXXXXXXXXXXXXXXXXX01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX] ^^ Access mask = 0b01 Test access mask: 0b01 & 0x1 == 0x1 Least significant bit of the access mask is set, thus the instruction fetch is not permitted. We should generate an instruction storage interrupt (ISI) with bit 42 of SRR1 set to indicate access precluded by virtual page class key protection. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [dwg: Move new constants to cpu.h, since they're not MMUv3 specific] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03hw/ppc/spapr: Add POWER9 to pseries cpu modelsSuraj Jitindar Singh1-0/+3
Add POWER9 cpu to list of spapr core models which allows it to be specified as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9). This now allows a POWER9 cpu to boot to userspace in tcg emulation for a pseries machine with a legacy kernel. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc/POWER9: Add cpu_has_work function for POWER9Suraj Jitindar Singh1-0/+45
The cpu has work function is used to mask interrupts used to determine if there is work for the cpu based on the LPCR. Add a function to do this for POWER9 and add it to the POWER9 cpu definition. This is similar to that for POWER8 except using the LPCR bits as defined for POWER9. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc/POWER9: Add POWER9 pa-features definitionSuraj Jitindar Singh1-0/+18
Add a pa-features definition which includes all of the new fields which have been added, note we don't claim support for any of these new features at this stage. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc/POWER9: Add POWER9 mmu fault handlerSuraj Jitindar Singh6-2/+113
Add a new mmu fault handler for the POWER9 cpu and add it as the handler for the POWER9 cpu definition. This handler checks if the guest is radix or hash based on the value in the partition table entry and calls the correct fault handler accordingly. The hash fault handling code has also been updated to check if the partition is using segment tables. Currently only legacy hash (no segment tables) is supported. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: Don't gen an SDR1 on POWER9 and rework register creationSuraj Jitindar Singh2-120/+203
POWER9 doesn't have a storage description register 1 (SDR1) which is used to store the base and size of the hash table. Thus we don't need to generate this register on the POWER9 cpu model. While we're here, the register generation code for 970, POWER5+, POWER<7/8/9> in general is a mess where we call a generic function from a model specific function which then attempts to call model specific functions, so rework this for readability. We update ppc_cpu_dump_state so that "info registers" will only display the value of sdr1 if the register has been generated. As mentioned above the register generation for the pcc->init_proc function for 970, POWER5+, POWER7, POWER8 and POWER9 has been reworked for improved clarity. Instead of calling init_proc_book3s_64 which then attempts to generate the correct registers through a mess of if statements, we remove this function and instead call the appropriate register generation functions directly. This follows the register generation model used for earlier cpu models (pre-970) whereby cpu specific registers are generated directly in the init_proc function and makes it easier to add/remove specific registers for new cpu models. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: Add patb_entry to sPAPRMachineStateSuraj Jitindar Singh3-0/+31
ISA v3.00 adds the idea of a partition table which is used to store the address translation details for all partitions on the system. The partition table consists of double word entries indexed by partition id where the second double word contains the location of the process table in guest memory. The process table is registered by the guest via a h-call. We need somewhere to store the address of the process table so we add an entry to the sPAPRMachineState struct called patb_entry to represent the second doubleword of a single partition table entry corresponding to the current guest. We need to store this value so we know if the guest is using radix or hash translation and the location of the corresponding process table in guest memory. Since we only have a single guest per qemu instance, we only need one entry. Since the partition table is technically a hypervisor resource we require that access to it is abstracted by the virtual hypervisor through the get_patbe() call. Currently the value of the entry is never set (and thus defaults to 0 indicating hash), but it will be required to both implement POWER9 kvm support and tcg radix support. We also add this field to be migrated as part of the sPAPRMachineState as we will need it on the receiving side as the guest will never tell us this information again and we need it to perform translation. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc/POWER9: Add POWERPC_MMU_V3 bitDavid Gibson1-1/+3
For easier handling of future processors using the POWER9 or something close to it, add a new bit in the MMU model. This was originally from a revised version of 86cf1e9 "target/ppc/POWER9: Add ISAv3.00 MMU definition" but the older version of the patch was already merged. This makes the change on top of the original version. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03powernv: Don't test POWER9 CPU yetDavid Gibson2-2/+5
A couple of tests for the work-in-progress 'powernv' machine type attempt to test on POWER9 CPUs. However the POWER9 CPU support is incomplete and this doesn't really work. In particular the firmware image we have currently assumes the presence of the SDR1 register, which no longer exists on POWER9. We only got away with this so far, because of a different bug which added SDR1 to POWER9 even though it shouldn't be there. For now, remove POWER9 testing of powernv, POWER8 testing will do for now until the POWER9 support is more complete. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03exec, kvm, target-ppc: Move getrampagesize() to common codeAlexey Kardashevskiy5-104/+115
getrampagesize() returns the largest supported page size and mainly used to know if huge pages are enabled. However is implemented in target-ppc/kvm.c and not available in TCG or other architectures. This renames and moves gethugepagesize() to mmap-alloc.c where fd-based analog of it is already implemented. This renames and moves getrampagesize() to exec.c as it seems to be the common place for helpers like this. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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