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2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra2-5/+0
The imsic DT binding[1] has changed and no longer require an ipi-id. The latest IMSIC driver dynamically allocates ipi id if slow-ipi is not defined. Get rid of the unused dt property which may lead to confusion. [1] https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/ Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel1-1/+1
We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot1-2/+2
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when using numa configuration, e.g.: ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \ -m 2G -smp cpus=16 \ -object memory-backend-ram,id=mem0,size=512M \ -object memory-backend-ram,id=mem1,size=512M \ -object memory-backend-ram,id=mem2,size=512M \ -object memory-backend-ram,id=mem3,size=512M \ -numa node,cpus=0-3,memdev=mem0,nodeid=0 \ -numa node,cpus=4-7,memdev=mem1,nodeid=1 \ -numa node,cpus=8-11,memdev=mem2,nodeid=2 \ -numa node,cpus=12-15,memdev=mem3,nodeid=3 leads to: Unexpected error in object_property_find_err() at ../qom/object.c:1304: qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not found This patch makes the nubering of the S irqs identical to what it was before. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei4-2/+20
Avoid calling riscv_itrigger_enabled() when calculate the tbflags. As the itrigger enable status can only be changed when write tdata1, migration load or itrigger fire, update env->itrigger_enabled at these places. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221013062946.7530-5-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei1-0/+72
When QEMU is not in icount mode, execute instruction one by one. The tdata1 can be read directly. When QEMU is in icount mode, use a timer to simulate the itrigger. The tdata1 may be not right because of lazy update of count in tdata1. Thus, We should pack the adjusted count into tdata1 before read it back. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei4-0/+65
The max count in itrigger can be 0x3FFF, which will cause a no trivial translation and execution overload. When icount is enabled, QEMU provides API that can fetch guest instruction number. Thus, we can set an timer for itrigger with the count as deadline. Only when timer expires or priviledge mode changes, do lazy update to count. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221013062946.7530-3-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei9-11/+131
When icount is not enabled, there is no API in QEMU that can get the guest instruction number. Translate the guest code in a way that each TB only has one instruction. After executing the instruction, decrease the count by 1 until it reaches 0 where the itrigger fires. Note that only when priviledge matches the itrigger configuration, the count will decrease. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221013062946.7530-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: generate virtual instruction exceptionMayuresh Chitale1-1/+7
This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale1-7/+80
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221016124726.102129-3-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale4-0/+378
Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa2-0/+4
Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa2-13/+17
This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06tcg/riscv: Fix base register for user-only qemu_ld/stRichard Henderson1-17/+22
When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set base after each step of the address arithmetic instead of before. Return the base register used from tcg_out_tlb_load, so as to keep that register choice localized to that function. Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06tcg/riscv: Fix reg overlap case in tcg_out_addsub2Richard Henderson1-2/+8
There was a typo using opc_addi instead of opc_add with the two registers. While we're at it, simplify the gating test to al == bl to improve dynamic scheduling even when the output register does not overlap the inputs. Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06tcg/riscv: Fix range matched by TCG_CT_CONST_M12Richard Henderson1-3/+16
We were matching a signed 13-bit range, not a 12-bit range. Expand the commentary within the function and be explicit about all of the ranges. Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei3-70/+42
Only the pmp index that be checked by pmp_hart_has_privs can be used by pmp_get_tlb_size to avoid an error pmp index. Before modification, we may use an error pmp index. For example, we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there is an pmp rule, valid range is [0x4fc, 0x500), then pmp_hart_has_privs will return true; However, this checked pmp index is discarded as pmp_hart_has_privs return bool value. In pmp_is_range_in_tlb, it will traverse all pmp rules. The tlb_sa will be 0x0, and tlb_ea will be 0xfff. If there is a pmp rule [0x10, 0x14), it will be misused as it is legal in pmp_get_tlb_size. As we have already known the correct pmp index, just remove the remove the pmp_is_range_in_tlb and get tlb size directly from pmp_get_tlb_size. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221012060016.30856-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-05Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into stagingPeter Maydell3-3/+36
Python patch roundup Mostly CI fixes and some small debugging improvements. # gpg: Signature made Wed 04 Jan 2023 21:04:26 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * tag 'python-pull-request' of https://gitlab.com/jsnow/qemu: python: add 3.11 to supported list iotests/check: Fix typing for sys.exit() value Python: fix flake8 config python/machine: Handle termination cases without QMP python/machine: Add debug logging to key state changes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05Merge tag 'mem-2023-01-02' of https://github.com/davidhildenbrand/qemu into ↵Peter Maydell3-11/+31
staging Hi, "Host Memory Backends" and "Memory devices" queue ("mem"): - virtio-mem fixes - Use new MPOL_PREFERRED_MANY mbind() policy for memory backends if possible # gpg: Signature made Mon 02 Jan 2023 11:22:04 GMT # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [marginal] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] # gpg: aka "David Hildenbrand <hildenbr@in.tum.de>" [unknown] # Primary key fingerprint: 1BD9 CAAD 735C 4C3A 460D FCCA 4DDE 10F7 00FF 835A * tag 'mem-2023-01-02' of https://github.com/davidhildenbrand/qemu: hostmem: Honor multiple preferred nodes if possible virtio-mem: Fix typo in function name virtio-mem: Fix the iterator variable in a vmem->rdl_list loop virtio-mem: Fix the bitmap index of the section offset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobsThomas Huth1-3/+4
The windows jobs (especially the 32-bit job) recently started to hit the timeout limit. Bump it a little bit to ease the situation (80 minutes is quite long already - OTOH, these jobs do not have to wait for a job from the container stage to finish, so this should still be OK). Additionally, some update on the container side recently enabled OpenGL in these jobs - but the corresponding code fails to compile. Thus disable OpenGL here for the time being until someone figured out the proper fix in the shader code for this. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20230104123559.277586-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04python: add 3.11 to supported listJohn Snow1-1/+2
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-id: 20221203005234.620788-4-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2023-01-04iotests/check: Fix typing for sys.exit() valueJohn Snow1-1/+1
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-id: 20221203005234.620788-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2023-01-04Python: fix flake8 configJohn Snow1-1/+2
Newer flake8 versions are a bit pickier about the config file, and my in-line comment confuses the parser. Fix it. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-id: 20221203005234.620788-2-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2023-01-04python/machine: Handle termination cases without QMPJohn Snow1-0/+6
If we request a shutdown of a VM without a QMP console, we'll just hang waiting. Not ideal. Add in code that attempts graceful termination in these cases. Tested lightly; it appears to work and I doubt we rely on this case anywhere, but it's a corner you're allowed to wedge yourself in, so it should be handled. Signed-off-by: John Snow <jsnow@redhat.com>
2023-01-04python/machine: Add debug logging to key state changesJohn Snow1-0/+25
When key decisions are made about the lifetime of the VM process being managed, there's no log entry. Juxtaposed with the very verbose runstate change logging of the QMP module, machine seems a bit too introverted now. Season the machine.py module with logging statements to taste to help make a tastier soup. Signed-off-by: John Snow <jsnow@redhat.com>
2023-01-04Merge tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu ↵Peter Maydell11-227/+47
into staging testing updates: - fix minor shell-ism that can break check-tcg - turn off verbose logging on custom runners - make configure echo call in CI - fix unused variable in linux-test - add binary compiler docker image for hexagon - disable doc and gui builds for tci and disable-tcg builds # gpg: Signature made Fri 23 Dec 2022 15:18:41 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu: gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobs tests/docker: use prebuilt toolchain for debian-hexagon-cross tests/tcg: fix unused variable in linux-test configure: repeat ourselves for the benefit of CI gitlab: turn off verbose logging for make check on custom runners configure: Fix check-tcg not executing any tests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04Merge tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu into ↵Peter Maydell5-38/+37
staging 9pfs: Windows host prep, cleanup * Next preparatory patches for upcoming Windows host support. * Cleanup patches. # gpg: Signature made Fri 23 Dec 2022 11:04:26 GMT # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu: hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper hw/9pfs: Drop unnecessary *xattr wrapper API declarations qemu/xattr.h: Exclude <sys/xattr.h> for Windows MAINTAINERS: Add 9p test client to section "virtio-9p" 9pfs: Fix some return statements in the synth backend Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-28hostmem: Honor multiple preferred nodes if possibleMichal Privoznik2-2/+22
If a memory-backend is configured with mode HOST_MEM_POLICY_PREFERRED then host_memory_backend_memory_complete() calls mbind() as: mbind(..., MPOL_PREFERRED, nodemask, ...); Here, 'nodemask' is a bitmap of host NUMA nodes and corresponds to the .host-nodes attribute. Therefore, there can be multiple nodes specified. However, the documentation to MPOL_PREFERRED says: MPOL_PREFERRED This mode sets the preferred node for allocation. ... If nodemask specifies more than one node ID, the first node in the mask will be selected as the preferred node. Therefore, only the first node is honored and the rest is silently ignored. Well, with recent changes to the kernel and numactl we can do better. The Linux kernel added in v5.15 via commit cfcaa66f8032 ("mm/hugetlb: add support for mempolicy MPOL_PREFERRED_MANY") support for MPOL_PREFERRED_MANY, which accepts multiple preferred NUMA nodes instead. Then, numa_has_preferred_many() API was introduced to numactl (v2.0.15~26) allowing applications to query kernel support. Wiring this all together, we can pass MPOL_PREFERRED_MANY to the mbind() call instead and stop ignoring multiple nodes, silently. Signed-off-by: Michal Privoznik <mprivozn@redhat.com> Message-Id: <a0b4adce1af5bd2344c2218eb4a04b3ff7bcfdb4.1671097918.git.mprivozn@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-28virtio-mem: Fix typo in function namePhilippe Mathieu-Daudé1-6/+6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221228130956.80515-1-philmd@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-28virtio-mem: Fix the iterator variable in a vmem->rdl_list loopChenyi Qiang1-1/+1
It should be the variable rdl2 to revert the already-notified listeners. Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface") Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20221228090312.17276-1-chenyi.qiang@intel.com> Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-28virtio-mem: Fix the bitmap index of the section offsetChenyi Qiang1-2/+2
vmem->bitmap indexes the memory region of the virtio-mem backend at a granularity of block_size. To calculate the index of target section offset, the block_size should be divided instead of the bitmap_size. Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface") Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20221216062231.11181-1-chenyi.qiang@intel.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-stable@nongnu.org Signed-off-by: David Hildenbrand <david@redhat.com>
2022-12-23gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobsThomas Huth1-2/+4
These jobs use their own "script:" section and thus do not profit from the global "--disable-docs" from the template. While we're at it, disable also some GUI front ends here since we do not gain any additional test coverage by compiling those here again. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20221208135945.99975-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-7-alex.bennee@linaro.org>
2022-12-23tests/docker: use prebuilt toolchain for debian-hexagon-crossMukilan Thiyagarajan6-205/+20
The current docker image for cross compiling hexagon guests is manually built since it takes >2 hours to build from source. This patch: 1. Solves the above issue by using the prebuilt clang toolchain hosted on CodeLinaro [1] and maintained by QUIC [2]. 2. The dockerfile is also switched from multi-stage to single stage build to allow the CI docker engine to reuse the layer cache. 3. Re-enables the hexagon-cross-container job to be always run in CI and makes it a non-optional dependency for the build-user-hexagon job. The changes for 1 & 2 together bring down the build time to ~3 minutes in GitLab CI when cache is reused and ~9 minutes when cache cannot be reused. [1]: https://github.com/CodeLinaro/hexagon-builder [2]: https://github.com/quic/toolchain_for_hexagon/releases/ Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> [AJB: also tweak MAINTAINERS, remove QEMU_JOB_ONLY_FORKS and comment] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221219144354.11659-1-quic_mthiyaga@quicinc.com> Message-Id: <20221221090411.1995037-6-alex.bennee@linaro.org>
2022-12-23tests/tcg: fix unused variable in linux-testAlex Bennée1-1/+5
The latest hexagon compiler picks up that we never consume wcount. Given the name of the #define that rcount checks against is WCOUNT_MAX I figured the check just got missed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-5-alex.bennee@linaro.org>
2022-12-23configure: repeat ourselves for the benefit of CIAlex Bennée1-3/+4
Our CI system echos the lines it executes but not the expansions. For the sake of a line of extra verbosity during the configure phase lets echo the invocation of script to stdout as well as the log when on CI. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-4-alex.bennee@linaro.org>
2022-12-23gitlab: turn off verbose logging for make check on custom runnersAlex Bennée3-13/+13
The verbosity adds a lot of unnecessary output to the CI logs which end up getting truncated anyway. We can always extract information from the meson test logs on a failure and for the custom runners its generally easier to re-create failures anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20221221090411.1995037-3-alex.bennee@linaro.org>
2022-12-23configure: Fix check-tcg not executing any testsMukilan Thiyagarajan1-3/+1
After configuring with --target-list=hexagon-linux-user running `make check-tcg` just prints the following: ``` make: Nothing to be done for 'check-tcg' ``` In the probe_target_compiler function, the 'break' command is used incorrectly. There are no lexically enclosing loops associated with that break command which is an unspecfied behaviour in the POSIX standard. The dash shell implementation aborts the currently executing loop, in this case, causing the rest of the logic for the loop in line 2490 to be skipped, which means no Makefiles are generated for the tcg target tests. Fixes: c3b570b5a9a24d25 (configure: don't enable cross compilers unless in target_list) Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Link: https://patchew.org/QEMU/20221207082309.9966-1-quic._5Fmthiyaga@quicinc.com/ Message-Id: <20221207082309.9966-1-quic_mthiyaga@quicinc.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221221090411.1995037-2-alex.bennee@linaro.org>
2022-12-23hw/9pfs: Replace the direct call to xxxat() APIs with a wrapperBin Meng2-20/+27
xxxat() APIs are only available on POSIX platforms. For future extension to Windows, let's replace the direct call to xxxat() APIs with a wrapper. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20221219102022.2167736-4-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23hw/9pfs: Drop unnecessary *xattr wrapper API declarationsBin Meng1-11/+0
These are not used anywhere in the source tree. Drop them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20221219102022.2167736-3-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23qemu/xattr.h: Exclude <sys/xattr.h> for WindowsBin Meng1-1/+3
Windows does not have <sys/xattr.h>. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20221219102022.2167736-2-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23MAINTAINERS: Add 9p test client to section "virtio-9p"Christian Schoenebeck1-0/+1
The 9p test cases use a dedicated, lite-weight 9p client implementation (using virtio transport) under tests/qtest/libqos/ to communicate with QEMU's 9p server. It's already there for a long time. Let's officially assign it to 9p maintainers. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <E1ozhlV-0007BU-0g@lizzy.crudebyte.com>
2022-12-239pfs: Fix some return statements in the synth backendGreg Kurz1-6/+6
The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions currently return a positive errno value on failure. This causes checkpatch.pl to spit several errors like the one below: ERROR: return of an errno should typically be -ve (return -EAGAIN) + return EAGAIN; Simply change the sign. This has no consequence since callers assert() the returned value to be equal to 0. Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <166930551818.827792.10663674346122681963.stgit@bahia> [C.S.: - Resolve conflict with 66997c42e02c. ] Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-21Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell20-34/+220
ppc patch queue for 2022-12-21: This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board). # gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu: target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement the DEXCR and HDEXCR hw/ppc/e500: Move comment to more appropriate place hw/ppc/e500: Resolve variable shadowing hw/ppc/e500: Prefer local variable over qdev_get_machine() hw/ppc/virtex_ml507: Prefer local over global variable target/ppc/mmu_common: Fix table layout of "info tlb" HMP command target/ppc/mmu_common: Log which effective address had no TLB entry found hw/ppc/spapr: Reduce "vof.h" inclusion hw/ppc/vof: Do not include the full "cpu.h" target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" hw/ppc/e500: Add Freescale eSDHC to e500plat hw/sd/sdhci: Support big endian SD host controller interfaces MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21target/ppc: Check DEXCR on hash{st, chk} instructionsNicholas Miehlbradt1-15/+43
Adds checks to the hashst and hashchk instructions to only execute if enabled by the relevant aspect in the DEXCR and HDEXCR. This behaviour is guarded behind TARGET_PPC64 since Power10 is currently the only implementation which has the DEXCR. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Message-Id: <20221220042330.2387944-3-nicholas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc: Implement the DEXCR and HDEXCRNicholas Miehlbradt4-0/+64
Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the same underlying value. Note that the ISA uses the abbreviation UDEXCR in two different contexts: the userspace DEXCR, the SPR index which can be read from userspace (implemented in this patch), and the ultravisor DEXCR, the equivalent register for the ultravisor state (not implemented). Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Move comment to more appropriate placeBernhard Beschow1-1/+1
The TLB entries are set up in mmubooke_create_initial_mapping(), not in booke206_page_size_to_tlb(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20221216145709.271940-7-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Resolve variable shadowingBernhard Beschow1-3/+1
Assign to the outer variable instead which even saves some code. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20221216145709.271940-6-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Prefer local variable over qdev_get_machine()Bernhard Beschow1-3/+2
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-5-shentey@gmail.com> [danielhb: remove linebreak in object_property_add_child()] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/virtex_ml507: Prefer local over global variableBernhard Beschow1-1/+1
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-4-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc/mmu_common: Fix table layout of "info tlb" HMP commandBernhard Beschow1-1/+1
Starting with the URWX columns the columns didn't line up. Before: QEMU 7.2.50 monitor - type 'help' for more information (qemu) info tlb TLB0: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x0000000000a80000 0x000000000105d000 4K 117 0 SR--UR-- --M-- U---- 0x0000000000100000 0x000000000114e000 4K 117 0 SR--UR-- --M-- U---- <snip TLB1: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x00000000c0000000 0x0000000000000000 16M 0 0 SR-XU--- --M-- U---- 0x00000000c1000000 0x0000000001000000 16M 0 0 SRW-U--- --M-- U---- <snip> (qemu) After: QEMU 7.2.50 monitor - type 'help' for more information (qemu) info tlb TLB0: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x00000000b7a00000 0x000000000fcf5000 4K 18 0 SR-- UR-- --M-- U---- 0x0000000000800000 0x000000000fd73000 4K 18 0 SR-- UR-X --M-- U---- <snip> TLB1: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x00000000c0000000 0x0000000000000000 16M 0 0 SR-X U--- --M-- U---- 0x00000000c1000000 0x0000000001000000 16M 0 0 SRW- U--- --M-- U---- <snip> (qemu) Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-3-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc/mmu_common: Log which effective address had no TLB entry foundBernhard Beschow1-1/+2
Let's not leave developers in the dark where this log message comes from. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-2-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.1 at 2025-01-18 19:15:11 +0000