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2024-01-12tests/fp: Bump fp-test-mulAdd test timeout to 3 minutesThomas Huth1-1/+1
When running the tests in slow mode with --enable-debug on a very loaded system, the fp-test-mulAdd test can take longer than 2 minutes. Bump the timeout to three minutes to make sure it passes in such situations, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-16-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12tests/unit: Bump test-crypto-block test timeout to 5 minutesThomas Huth1-0/+1
When running the tests in slow mode on a very loaded system and with --enable-debug, the test-crypto-block can take longer than 4 minutes. Bump the timeout to 5 minutes to make sure that it also passes in such situations. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-15-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12tests/unit: Bump test-aio-multithread test timeout to 2 minutesThomas Huth1-0/+1
When running the tests in slow mode on a very loaded system and with --enable-debug, the test-aio-multithread can take longer than 1 minute. Bump the timeout to two minutes to make sure that it also passes in such situations. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-14-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12tests/qtest: Bump the device-introspect-test timeout to 12 minutesThomas Huth1-0/+1
When running the test in slow mode on a very loaded system with the arm/aarch64 target and with --enable-debug, it can take longer than 10 minutes to finish the introspection test. Bump the timeout to twelve minutes to make sure that it also finishes in such situations. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-13-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump bios-table-test timeout to 9 minutesDaniel P. Berrangé1-1/+1
This is reliably hitting the current 2 minute timeout in GitLab CI, and for the TCI job, it even hits a 6 minute timeout. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-12-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-12-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump aspeed_smc-test timeout to 6 minutesDaniel P. Berrangé1-0/+1
On a loaded system with --enable-debug, this test can take longer than 5 minutes. Raising the timeout to 6 minutes gives greater headroom for such situations. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [thuth: Increase the timeout to 6 minutes for very loaded systems] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-11-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump qos-test timeout to 2 minutesDaniel P. Berrangé1-0/+1
The qos-test takes just under 1 minute in a --enable-debug build. Bumping to 2 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-10-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-10-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump boot-serial-test timeout to 3 minutesDaniel P. Berrangé1-0/+1
The boot-serial-test takes about 1 + 1/2 minutes in a --enable-debug build. Bumping to 3 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-9-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-9-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump prom-env-test timeout to 6 minutesDaniel P. Berrangé1-0/+1
The prom-env-test can take more than 5 minutes in a --enable-debug build on a loaded system. Bumping to 6 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [thuth: Bump timeout to 6 minutes instead of 3] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-8-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump pxe-test timeout to 10 minutesDaniel P. Berrangé1-0/+1
The pxe-test uses the boot_sector_test() function, and that already uses a timeout of 600 seconds. So adjust the timeout on the meson side accordingly. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [thuth: Bump timeout to 600s and adjust commit description] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-7-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump test-hmp timeout to 4 minutesDaniel P. Berrangé1-1/+1
The hmp test takes just under 3 minutes in a --enable-debug build. Bumping to 4 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-6-berrange@redhat.com> [thuth: fix copy-n-paste error in the description] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-6-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump npcm7xx_pwm-test timeout to 5 minutesDaniel P. Berrangé1-1/+1
The npcm7xx_pwm-test takes 3 & 1/2 minutes in a --enable-debug build. Bumping to 5 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20230717182859.707658-5-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-5-thuth@redhat.com> [AJB: s/pwn/pwm] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump qom-test timeout to 15 minutesDaniel P. Berrangé1-1/+1
The qom-test is periodically hitting the 5 minute timeout when running on the aarch64 emulator under GitLab CI. With an --enable-debug build it can take over 10 minutes for arm/aarch64 targets. Setting timeout to 15 minutes gives enough headroom to hopefully make it reliable. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-4-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-4-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump migration-test timeout to 8 minutesDaniel P. Berrangé1-1/+1
The migration test should take between 1 min 30 and 2 mins on reasonably modern hardware. The test is not especially compute bound, rather its running time is dominated by the guest RAM size relative to the bandwidth cap, which forces each iteration to take at least 30 seconds. None the less under high load conditions with multiple QEMU processes spawned and competing with other parallel tests, the worst case running time might be somewhat extended. Bumping the timeout to 8 minutes gives us good headroom, while still catching stuck tests relatively quickly. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-3-berrange@redhat.com> [thuth: Bump timeout to 8 minutes to make it work on very loaded systems, too] Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-3-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12qtest: bump min meson timeout to 60 secondsDaniel P. Berrangé1-7/+2
Even some of the relatively fast qtests can sometimes hit the 30 second timeout in GitLab CI under high parallelism/load conditions. Bump the min to 60 seconds to give a higher margin for reliability. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20230717182859.707658-2-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215070357.10888-2-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-12chardev: use bool for fe_is_openAlex Bennée3-16/+21
The function qemu_chr_fe_init already treats be->fe_open as a bool and if it acts like a bool it should be one. While we are at it make the variable name more descriptive and add kdoc decorations. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231211145959.93759-1-alex.bennee@linaro.org>
2024-01-12gitlab: include microblazeel in testingAlex Bennée1-2/+2
This reverts aeb5f8f248e (gitlab: build the correct microblaze target) now we actually have a little-endian test in avocado thanks to this years advent calendar. Message-Id: <20240103173349.398526-4-alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-01-12tests/avocado: use snapshot=on in kvm_xen_guestAlex Bennée1-1/+1
This ensures the rootfs is never permanently changed as we don't need persistence between tests anyway. Message-Id: <20240103173349.398526-3-alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-01-12tests/avocado: Add a test for a little-endian microblaze machineThomas Huth1-0/+26
We've already got a test for a big endian microblaze machine, but so far we lack one for a little endian machine. Now that the QEMU advent calendar featured such an image, we can test the little endian mode, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231215161851.71508-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-01-11.gitlab-ci.d/buildtest.yml: Work around htags bug when environment is largePeter Maydell1-1/+4
Sometimes the CI "pages" job fails with a message like this from htags: $ htags -anT --tree-view=filetree -m qemu_init -t "Welcome to the QEMU sourcecode" htags: Negative exec line limit = -371 This is due to a bug in hflags where if the environment is too large it falls over: https://lists.gnu.org/archive/html/bug-global/2024-01/msg00000.html This happens to us because GitLab CI puts the commit message of the commit under test into the CI_COMMIT_MESSAGE and/or CI_COMMIT_TAG_MESSAGE environment variables, so the job will fail if the commit happens to have a verbose commit message. Work around the htags bug by unsetting these variables while running htags. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2080 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240111125543.1573473-1-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11Merge tag 'firmware/edk2-20231213-pull-request' of ↵Peter Maydell11-3/+9
https://gitlab.com/kraxel/qemu into staging edk2: update to git snapshot (maybe for-8.2) This updates edk2 to git master as of today. This picks up a patch (merged only yesterday, that's why this last-minute PR) which allows to work around a bug in shim, and enables that workaround in the qemu firmware builds. This solves a real-world problem on arm hardware, walk over to https://gitlab.com/qemu-project/qemu/-/issues/1990 to see the details. Merging this firmware update that close to the 8.2 release clearly is not without risks. If I get a 'no', I'm not going to complain. That said I'm not aware of any bugs, and landing this in 8.2.0 would make a bunch of folks hanging around in issue 1990 very happy. Alternative plan would be to merge this after the release, give it some time for testing, and assuming everything goes well schedule a backport for 8.2.1 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmV5i70ACgkQTLbY7tPo # cTg5mA//VDjGNmBYWhIhf5c7Z8+h1FspnqkxqResX3KgE2indCWkTlyZnCFGb7CO # NgDiCR7xKMw9S1Cun14vTs/OK8BVFvmXGhTIgjecK+k6w6D8PtR4QvfXYUKxNajA # Sd6reWAlojlgKOkpcrejrSSvtBTZqrJc8CrkowMR3FZXzD0GstUCMZ0jBvVhzlO6 # o9RMk0kbf+VNupsA+v9ZWPstMHXjLKs8v1eUqrc6LYOanY6mqQM5Wz9yWteUfrNp # /0zShBrkmB+BgPoRQypphFdXRacP82fVXDMeTSbbXaReI0PR9MLKZnyk0UUkES6k # BTtEVEM0cCAYLGaGFjHZVEpbrtFmVBisE0fLgdozsCU8SMCuxjNzXyj0HGRsJ7m4 # UQ+qGJLOR3Zx/Bnz3LLKOmWBlq6MQD5lYgxk3dwSPKzXTqun1ndlVKenJ3Z9fgXQ # gibVbS/2fNylR9aoPSYkXnlE8l8vSo24sXIn8R2wX8rJ0xBc6bFDs1MKizzv2b9l # YUeybDwgDvbbDLGSN4DgIeNSZxQBgNO/nmuFnx8jNxTqcNlCJFHO2jR7gPijj5ct # ZPQQwLCCEIxD3OY3Dg94zXDm1EfWZQpNBFDD/83joJt/15Vu9GLsPqEs4QUdiQsp # MO4Bd7HFavLSGsyX1rMe0yonWirbRX2uKYmyc+KwGjjS9LRGesU= # =bcZj # -----END PGP SIGNATURE----- # gpg: Signature made Wed 13 Dec 2023 10:47:25 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'firmware/edk2-20231213-pull-request' of https://gitlab.com/kraxel/qemu: tests/acpi: disallow tests/data/acpi/virt/SSDT.memhp changes tests/acpi: update expected data files edk2: update binaries to git snapshot edk2: update build config, set PcdUninstallMemAttrProtocol = TRUE. edk2: update to git snapshot tests/acpi: allow tests/data/acpi/virt/SSDT.memhp changes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-11Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell18-258/+1210
staging pull-loongarch-20240111 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZZ/QKgAKCRBAov/yOSY+ # 34eqBADA48++Z9gETFNheLUHdYEaja2emn+gSaoHLFquyq/l53w8RfrUII+BzV1o # T7D8xjlVQldAYZzqQn2pQe2S7r4ggfeNmxGxwJbCTW9sooGMwBnU8+Ix3ruSet7K # gI+UHLU4oHk6jdrT384tux2EG+qUmlLN1c7j4G/z1OzKEwFv7Q== # =+Pi0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 11 Jan 2024 11:25:30 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu: hw/intc/loongarch_extioi: Add vmstate post_load support hw/intc/loongarch_extioi: Add dynamic cpu number support hw/loongarch/virt: Set iocsr address space per-board rather than percpu hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops target/loongarch: Add loongarch kvm into meson build target/loongarch: Implement set vcpu intr for kvm target/loongarch: Restrict TCG-specific code target/loongarch: Implement kvm_arch_handle_exit target/loongarch: Implement kvm_arch_init_vcpu target/loongarch: Implement kvm_arch_init function target/loongarch: Implement kvm get/set registers target/loongarch: Supplement vcpu env initial when vcpu reset target/loongarch: Define some kvm_arch interfaces linux-headers: Synchronize linux headers from linux v6.7.0-rc8 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-11tests/tcg/s390x: Test LOAD ADDRESS EXTENDEDIlya Leoshkevich2-0/+32
Add a small test to prevent regressions. Userspace runs in primary mode, so LAE should always set the access register to 0. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240111092328.929421-3-iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11target/s390x: Fix LAE setting a wrong access registerIlya Leoshkevich1-1/+2
LAE should set the access register corresponding to the first operand, instead, it always modifies access register 1. Co-developed-by: Ido Plat <Ido.Plat@ibm.com> Cc: qemu-stable@nongnu.org Fixes: a1c7610a6879 ("target-s390x: implement LAY and LAEY instructions") Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240111092328.929421-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11scripts/checkpatch: Support codespell checkingZhao Liu1-20/+105
Add two spelling check options (--codespell and --codespellfile) to enhance spelling check through dictionary, which copied the Linux kernel's implementation in checkpatch.pl. This check uses the dictionary at "/usr/share/codespell/dictionary.txt" by default, if there is no dictionary specified under this path, it will look for the dictionary of python3's codespell (This requires user to add python3's path in environment variable $PATH, and to install codespell by "pip install codespell"). Tested-by: Yongwei Ma <yongwei.ma@intel.com> Tested-by: Samuel Tardieu <sam@rfc1149.net> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240105083848.267192-1-zhao1.liu@linux.intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11hw/s390x/ccw: Replace dirname() with g_path_get_dirname()Zhao Liu1-1/+3
As commit 3e015d815b3f ("use g_path_get_basename instead of basename") said, g_path_get_dirname() should be preferred over dirname() since the former is a portable utility function that has the advantage of not modifying the string argument. Replace dirname() with g_path_get_dirname(). Suggested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20231221171921.57784-3-zhao1.liu@linux.intel.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11hw/s390x/ccw: Replace basename() with g_path_get_basename()Zhao Liu1-2/+3
g_path_get_basename() is a portable utility function that has the advantage of not modifying the string argument, so it should be preferred over basename(). And also to avoid potential compile breakage with the Musl C library similar to [1], replace basename() with g_path_get_basename(). [1]: https://lore.kernel.org/all/20231212010228.2701544-1-raj.khem@gmail.com/ Suggested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20231221171921.57784-2-zhao1.liu@linux.intel.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11target/s390x/kvm/pv: Provide some more useful information if decryption failsThomas Huth5-12/+30
It's a common scenario to copy guest images from one host to another to run the guest on the other machine. This (of course) does not work with "secure execution" guests since they are encrypted with one certain host key. However, if you still (accidentally) do it, you only get a very user-unfriendly error message that looks like this: qemu-system-s390x: KVM PV command 2 (KVM_PV_SET_SEC_PARMS) failed: header rc 108 rrc 5 IOCTL rc: -22 Let's provide at least a somewhat nicer hint to the users so that they are able to figure out what might have gone wrong. Buglink: https://issues.redhat.com/browse/RHEL-18212 Message-ID: <20240110142916.850605-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11hw/intc/loongarch_extioi: Add vmstate post_load supportBibo Mao1-44/+76
There are elements sw_ipmap and sw_coremap, which is usd to speed up irq injection flow. They are saved and restored in vmstate during migration, indeed they can calculated from hw registers. Here post_load is added for get sw_ipmap and sw_coremap from extioi hw state. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/intc/loongarch_extioi: Add dynamic cpu number supportBibo Mao3-40/+81
On LoongArch physical machine, one extioi interrupt controller only supports 4 cpus. With processor more than 4 cpus, there are multiple extioi interrupt controllers; if interrupts need to be routed to other cpus, they are forwarded from extioi node0 to other extioi nodes. On virt machine model, there is simple extioi interrupt device model. All cpus can access register of extioi interrupt controller, however interrupt can only be route to 4 vcpu for compatible with old kernel. This patch adds dynamic cpu number support about extioi interrupt. With old kernel legacy extioi model is used, however kernel can detect and choose new route method in future, so that interrupt can be routed to all vcpus. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/loongarch/virt: Set iocsr address space per-board rather than percpuBibo Mao10-104/+128
LoongArch system has iocsr address space, most iocsr registers are per-board, however some iocsr register spaces banked for percpu such as ipi mailbox and extioi interrupt status. For banked iocsr space, each cpu has the same iocsr space, but separate data. This patch changes iocsr address space per-board rather percpu, for iocsr registers specified for cpu, MemTxAttrs.requester_id can be parsed for the cpu. With this patches, the total address space on board will be simple, only iocsr address space and system memory, rather than the number of cpu and system memory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi opsBibo Mao1-59/+77
There are two interface pairs for MemoryRegionOps, read/write and read_with_attrs/write_with_attrs. The later is better for ipi device emulation since initial cpu can be parsed from attrs.requester_id. And requester_id can be overrided for IOCSR_IPI_SEND and mail_send function when it is to forward message to another vcpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Add loongarch kvm into meson buildTianrui Zhao3-0/+4
Add kvm.c into meson.build to compile it when kvm is configed. Meanwhile in meson.build, we set the kvm_targets to loongarch64-softmmu when the cpu is loongarch. And fix the compiling error when config is enable-kvm,disable-tcg. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-10-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Implement set vcpu intr for kvmTianrui Zhao4-1/+40
Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-ID: <20240105075804.1228596-9-zhaotianrui@loongson.cn> [PMD: Split from bigger patch, part 2] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240110094152.52138-2-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Restrict TCG-specific codeTianrui Zhao1-9/+21
In preparation of supporting KVM in the next commit. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-ID: <20240105075804.1228596-9-zhaotianrui@loongson.cn> [PMD: Split from bigger patch, part 1] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240110094152.52138-1-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Implement kvm_arch_handle_exitTianrui Zhao2-1/+24
Implement kvm_arch_handle_exit for loongarch. In this function, the KVM_EXIT_LOONGARCH_IOCSR is handled, we read or write the iocsr address space by the addr, length and is_write argument in kvm_run. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-8-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Implement kvm_arch_init_vcpuTianrui Zhao3-0/+27
Implement kvm_arch_init_vcpu interface for loongarch, in this function, we register VM change state handler. And when VM state changes to running, the counter value should be put into kvm to keep consistent with kvm, and when state change to stop, counter value should be refreshed from kvm. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-7-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Implement kvm_arch_init functionTianrui Zhao1-0/+1
Implement the kvm_arch_init of loongarch, in the function, the KVM_CAP_MP_STATE cap is checked by kvm ioctl. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-6-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Implement kvm get/set registersTianrui Zhao7-3/+599
Implement kvm_arch_get/set_registers interfaces, many regs can be get/set in the function, such as core regs, csr regs, fpu regs, mp state, etc. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Change-Id: Ia8fc48fe08b1768853f7729e77d37cdf270031e4 Message-Id: <20240105075804.1228596-5-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Supplement vcpu env initial when vcpu resetTianrui Zhao2-1/+3
Supplement vcpu env initial when vcpu reset, including init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two regs will be used in kvm_get/set_csr_ioctl. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-4-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11target/loongarch: Define some kvm_arch interfacesTianrui Zhao1-0/+131
Define some functions in target/loongarch/kvm/kvm.c, such as kvm_arch_put_registers, kvm_arch_get_registers and kvm_arch_handle_exit, etc. which are needed by kvm/kvm-all.c. Now the most functions has no content and they will be implemented in the next patches. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-3-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11linux-headers: Synchronize linux headers from linux v6.7.0-rc8Tianrui Zhao1-4/+6
Use the scripts/update-linux-headers.sh to synchronize linux headers from linux v6.7.0-rc8. We mainly want to add the loongarch linux headers and then add the loongarch kvm support based on it. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240105075804.1228596-2-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11Merge tag 'pull-target-arm-20240111' of ↵Peter Maydell39-80/+1203
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Emulate FEAT_NV, FEAT_NV2 * add cache controller for Freescale i.MX6 * Add minimal support for the B-L475E-IOT01A board * Allow SoC models to configure M-profile CPUs with correct number of NVIC priority bits * Add missing QOM parent for v7-M SoCs * Set CTR_EL0.{IDC,DIC} for the 'max' CPU * hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWfypMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sleD/4tQOMteba5BNMDns6R96E4 # kj5q0Iy9XyzQ486Q4cIZXI5N3BddCp2ks8WeS2W3w4IT/lms0U6UwXV4E98I4I/b # KSfOoUd/cp8IvdvzfpWbmQcPMoauHZdCUN33pYYXOjfi1RkpzgNU5Qgh09Nl/xYU # V3oaEvWhLtepT/fwJLYxoqVHDaEmyW+6zriF0+eGjZvkhgPyhllla9eti7AyHTfH # T3A4Fyx/wudRE3NP6xsLfxldriJTxQeba+TqLSh3IXn/PMtK13/ARsY/hl72Q4ML # Fgad8Zho4eXbuOQ9oiqb7gp4K3IKd9/8FbCzECoIAq7AnLAD4KwpLQR8GULRvYW3 # 0eQq2txTXQWNcmWpIyDRRME+qeNVwWSk+QJDs5WuhVqlVQ4hpqtgFf1EX+7ORdS1 # WG0fb8etvr8oCSkzCmP/o6xYGJ0EyTVMU5DmWviy3bxMrUMcmobjvCQr/n2gC713 # 1NDmEaYPbl+pX8EMu8byst7/No2PXRgIO0UVVb4KZybfhNy+BBs+LiMVlSRS5YH4 # 8NWtoYZlG9RcPnY+8Xrxz9VTi2cNAAcdbf5uK3snJxkFV2SmV3oBoMxWen3mee0f # 2PNVEbt9zvPV8hViBVLsqRhVXd9wMq6motIRlkKge1u1TvwIxO21ibykI3tvYOGv # BffIjhUdnYtX90JAtXtFDw== # =yQwf # -----END PGP SIGNATURE----- # gpg: Signature made Thu 11 Jan 2024 11:01:39 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240111' of https://git.linaro.org/people/pmaydell/qemu-arm: (41 commits) target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) target/arm: Mark up VNCR offsets (offsets 0x100..0x160) target/arm: Mark up VNCR offsets (offsets 0x0..0xff) target/arm: Report VNCR_EL2 based faults correctly target/arm: Implement FEAT_NV2 redirection of sysregs to RAM target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 target/arm: Implement VNCR_EL2 register target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs target/arm: Handle FEAT_NV page table attribute changes target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} target/arm: Always use arm_pan_enabled() when checking if PAN is enabled target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-11Merge tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell5-25/+67
tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor tcg/ppc: Use new registers for LQ destination util: fix build with musl libc on ppc64le # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmWfESodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8OLQf/TnNOeBPGFVFRLycp # rRbLxFar/oRP0SfH7I1S09vKFH+mlb5JK5Er4DL9CmUxV596r9ZGiwC6RlowK8nD # INfC9Nnf3MgeyViDG41bA5oxiWom+XxbFtN4iVZo84CVDFEZFt0xjaq7d9Zhfj9J # xWWAlCr013MnhamjmEB2NKxQzLnIMhJs1JuhkAbThKsaPoDwHLSmIMSMJlRwrf27 # Ey9blEt8GAOkd1iMA0xpw2vthNUfpCgZibg//CzqZevIq8pdxcieQ9ZjuxLjDM32 # N3u3eaX9SyuLwj4682MYuHYIxpuZ+HkIkjmuIQBsBuG8d3EoDs+rr/9Jzi47f/nR # 0btVug== # =rXXF # -----END PGP SIGNATURE----- # gpg: Signature made Wed 10 Jan 2024 21:50:34 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu: util: fix build with musl libc on ppc64le tcg/ppc: Use new registers for LQ destination tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates tcg/i386: convert add/sub of 128 to sub/add of -128 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-11gitlab: fix s390x tag for avocado-system-centosNicholas Piggin1-1/+1
The 390x tag should be s390x. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20240107170119.82222-2-npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11tests/qtest/virtio-ccw: Fix device presence checkingSamuel Tardieu1-1/+1
An apparent copy-paste error tests for the presence of the virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw device. Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Message-ID: <20240106130121.1244993-1-sam@rfc1149.net> Fixes: 65331bf5d1 ("tests/qtest: Check for virtio-ccw devices before using them") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11qtest: ensure netdev-socket tests have non-overlapping namesDaniel P. Berrangé1-1/+1
When naming glib tests if the name of one test is a substring of the name of another test, it is not possible to use the '-p /the/name' option to run a single test. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240104162942.211458-7-berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11net: handle QIOTask completion to report useful error messageDaniel P. Berrangé1-5/+10
The network stream backend uses the async QIO socket APIs for listening and connecting sockets. It does not check the task object completion status, however, instead just looking at whether the socket FD is -1 or not. By checking the task completion, we can set a useful error message for users instead of the non-actionable "connection error" string. eg so users will see: (qemu) info network net: index=0,type=stream,error: Failed to connect to '/foo.unix': No such file or directory Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240104162942.211458-6-berrange@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11net: add explicit info about connecting/listening stateDaniel P. Berrangé2-6/+9
When running 'info network', if the stream backend is still in the process of connecting, or waiting for an incoming connection, no information is displayed. There is also no way to distinguish whether the server is still in the process of setting up the listener socket, or whether it is ready to accept incoming client connections. This leads to a race condition in the netdev-socket qtest which launches a server process followed by a client process. Under high load conditions it is possible for the client to attempt to connect before the server is accepting clients. For the scenarios which do not set the 'reconnect' option, this opens up a race which can lead to the test scenario failing to reach the expected state. Now that 'info network' can distinguish between initialization phase and the listening phase, the netdev-socket qtest will correctly synchronize, such that the client QEMU is not spawned until the server is ready. This should solve the non-deterministic failures seen with the netdev-socket qtest. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240104162942.211458-5-berrange@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-01-11Revert "tests/qtest/netdev-socket: Raise connection timeout to 120 seconds"Daniel P. Berrangé1-1/+1
This reverts commit 0daaf2761f6d268ffaa2d01d450e202e127452b1. The test was not timing out because of slow execution. It was timing out due to a race condition leading to the client QEMU attempting (and fatally failing) to connect before the server QEMU was listening. Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com> Message-ID: <20240104162942.211458-4-berrange@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.1 at 2025-09-20 17:07:29 +0000