riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-10-31	qom: use object_new_with_class when possible	Paolo Bonzini	3	-4/+5
2024-10-31	qom: remove unused function	Paolo Bonzini	2	-16/+0
2024-10-31	i386/cpu: Drop the check of phys_bits in host_cpu_realizefn()	Xiaoyao Li	1	-13/+3
2024-10-31	accel: remove dead statement and useless assertion	Paolo Bonzini	1	-3/+1
2024-10-31	MAINTAINERS: Add myself as a reviewer of x86 general architecture support	Zhao Liu	1	-0/+1
2024-10-31	configure, meson: deprecate 32-bit MIPS	Paolo Bonzini	3	-5/+17
2024-10-31	configure: detect 64-bit MIPS	Paolo Bonzini	1	-3/+7
2024-10-31	Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/q...	Peter Maydell	65	-139/+4790
2024-10-31	Merge tag 'pull-target-arm-20241029' of https://git.linaro.org/people/pmaydel...	Peter Maydell	28	-210/+425
2024-10-31	target/riscv: Fix vcompress with rvv_ta_all_1s	Anton Blanchard	1	-1/+1
2024-10-31	target/riscv/kvm: clarify how 'riscv-aia' default works	Daniel Henrique Barboza	1	-10/+4
2024-10-31	target/riscv/kvm: set 'aia_mode' to default in error path	Daniel Henrique Barboza	1	-7/+15
2024-10-31	docs/specs: add riscv-iommu	Daniel Henrique Barboza	3	-0/+104
2024-10-31	qtest/riscv-iommu-test: add init queues test	Daniel Henrique Barboza	2	-0/+155
2024-10-31	hw/riscv/riscv-iommu: add DBG support	Tomasz Jeznach	2	-0/+76
2024-10-31	hw/riscv/riscv-iommu: add ATS support	Tomasz Jeznach	4	-3/+171
2024-10-31	hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)	Tomasz Jeznach	2	-4/+203
2024-10-31	test/qtest: add riscv-iommu-pci tests	Daniel Henrique Barboza	5	-0/+237
2024-10-31	hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug	Tomasz Jeznach	1	-1/+32
2024-10-31	hw/riscv: add riscv-iommu-pci reference device	Tomasz Jeznach	2	-1/+203
2024-10-31	pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device	Daniel Henrique Barboza	2	-0/+3
2024-10-31	hw/riscv: add RISC-V IOMMU base emulation	Tomasz Jeznach	9	-0/+2222
2024-10-31	hw/riscv: add riscv-iommu-bits.h	Tomasz Jeznach	1	-0/+345
2024-10-31	exec/memtxattr: add process identifier to the transaction attributes	Tomasz Jeznach	1	-0/+5
2024-10-31	target/riscv: Expose zicfiss extension as a cpu property	Deepak Gupta	1	-0/+1
2024-10-31	disas/riscv: enable disassembly for compressed sspush/sspopchk	Deepak Gupta	2	-1/+19
2024-10-31	disas/riscv: enable disassembly for zicfiss instructions	Deepak Gupta	2	-1/+40
2024-10-30	scripts: remove erroneous file that breaks git clone on Windows	Pierrick Bouvier	1	-0/+0
2024-10-30	target/i386: fix CPUID check for LFENCE and SFENCE	Paolo Bonzini	1	-2/+2
2024-10-30	ci: enable rust in the Fedora system build job	Daniel P. Berrangé	1	-1/+1
2024-10-30	tests: add 'rust' and 'bindgen' to CI package list	Daniel P. Berrangé	23	-3/+51
2024-10-30	stubs: avoid duplicate symbols in libqemuutil.a	Paolo Bonzini	1	-1/+6
2024-10-30	target/riscv: compressed encodings for sspush and sspopchk	Deepak Gupta	1	-0/+4
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta	4	-2/+140
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta	11	-34/+35
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta	4	-2/+30
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta	2	-14/+53
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta	3	-0/+9
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta	6	-0/+111
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta	3	-0/+25
2024-10-30	target/riscv: Expose zicfilp extension as a cpu property	Deepak Gupta	1	-0/+1
2024-10-30	disas/riscv: enable `lpad` disassembly	Deepak Gupta	2	-1/+19
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta	3	-1/+60
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta	4	-0/+39
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta	3	-0/+6
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta	3	-0/+72
2024-10-30	target/riscv: Introduce elp state and enabling controls for zicfilp	Deepak Gupta	7	-1/+68
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta	3	-0/+7
2024-10-30	target/riscv: expose *envcfg csr and priv to qemu-user as well	Deepak Gupta	2	-4/+10
2024-10-30	hw/char: sifive_uart: Print uart characters async	Alistair Francis	2	-8/+105