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2017-06-02aspeed/i2c: handle LAST command under the RX commandCédric Le Goater1-3/+6
Today, the LAST command is handled with the STOP command but this is incorrect. Also nack the I2C bus when a LAST is issued. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1494827476-1487-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02aspeed/i2c: improve command handlingCédric Le Goater1-6/+18
Multiple I2C commands can be fired simultaneously and the controller execute the commands following these priorities: (1) Master Start Command (2) Master Transmit Command (3) Slave Transmit Command or Master Receive Command (4) Master Stop Command The current code is incorrect with respect to the above sequence and needs to be reworked to handle each individual command. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1494827476-1487-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02arm: Implement HFNMIENA support for M profile MPUPeter Maydell3-2/+41
Implement HFNMIENA support for the M profile MPU. This bit controls whether the MPU is treated as enabled when executing at execution priorities of less than zero (in NMI, HardFault or with the FAULTMASK bit set). Doing this requires us to use a different MMU index for "running at execution priority < 0", because we will have different access permissions for that case versus the normal case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-14-git-send-email-peter.maydell@linaro.org
2017-06-02arm: add MPU support to M profile CPUsMichael Davidsaver4-3/+137
The M series MPU is almost the same as the already implemented R profile MPU (v7 PMSA). So all we need to implement here is the MPU register interface in the system register space. This implementation has the same restriction as the R profile MPU that it doesn't permit regions to be sized down smaller than 1K. We also do not yet implement support for MPU_CTRL.HFNMIENA; this bit should if zero disable use of the MPU when running HardFault, NMI or with FAULTMASK set to 1 (ie at an execution priority of less than zero) -- if the MPU is enabled we don't treat these cases any differently. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1493122030-32191-13-git-send-email-peter.maydell@linaro.org [PMM: Keep all the bits in mpu_ctrl field, rather than using SCTLR bits for them; drop broken HFNMIENA support; various cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02armv7m: Classify faults as MemManage or BusFaultMichael Davidsaver1-3/+42
General logic is that operations stopped by the MPU are MemManage, and those which go through the MPU and are caught by the unassigned handle are BusFault. Distinguish these by looking at the exception.fsr values, and set the CFSR bits and (if appropriate) fill in the BFAR or MMFAR with the exception address. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1493122030-32191-12-git-send-email-peter.maydell@linaro.org [PMM: i-side faults do not set BFAR/MMFAR, only d-side; added some CPU_LOG_INT logging] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02arm: All M profile cores are PMSAPeter Maydell1-0/+8
All M profile CPUs are PMSA, so set the feature bit. (We haven't actually implemented the M profile MPU register interface yet, but setting this feature bit gives us closer to correct behaviour for the MPU-disabled case.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-11-git-send-email-peter.maydell@linaro.org
2017-06-02armv7m: Implement M profile default memory mapMichael Davidsaver1-9/+32
Add support for the M profile default memory map which is used if the MPU is not present or disabled. The main differences in behaviour from implementing this correctly are that we set the PAGE_EXEC attribute on the right regions of memory, such that device regions are not executable. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1493122030-32191-10-git-send-email-peter.maydell@linaro.org [PMM: rephrased comment and commit message; don't mark the flash memory region as not-writable; list all the cases in the default map explicitly rather than using a 'default' case for the non-executable regions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02armv7m: Improve "-d mmu" tracing for PMSAv7 MPUMichael Davidsaver1-12/+27
Improve the "-d mmu" tracing for the PMSAv7 MPU translation process as an aid in debugging guest MPU configurations: * fix a missing newline for a guest-error log * report the region number with guest-error or unimp logs of bad region register values * add a log message for the overall result of the lookup * print "0x" prefix for hex values Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-9-git-send-email-peter.maydell@linaro.org [PMM: a little tidyup, report region number in all messages rather than just one] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02arm: Remove unnecessary check on cpu->pmsav7_dregionPeter Maydell1-2/+1
Now that we enforce both: * pmsav7_dregion == 0 implies has_mpu == false * PMSA with has_mpu == false means SCTLR.M cannot be set we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(), because we can only reach this code path if the MPU is enabled (and so region_translation_disabled() returned false). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-8-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Don't let no-MPU PMSA cores write to SCTLR.MPeter Maydell1-0/+5
If the CPU is a PMSA config with no MPU implemented, then the SCTLR.M bit should be RAZ/WI, so that the guest can never turn on the non-existent MPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Don't clear ARM_FEATURE_PMSA for no-mpu configsPeter Maydell1-1/+7
Fix the handling of QOM properties for PMSA CPUs with no MPU: Allow no-MPU to be specified by either: * has-mpu = false * pmsav7_dregion = 0 and make setting one imply the other. Don't clear the PMSA feature bit in this situation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-6-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Clean up handling of no-MPU PMSA CPUsPeter Maydell4-14/+14
ARM CPUs come in two flavours: * proper MMU ("VMSA") * only an MPU ("PMSA") For PMSA, the MPU may be implemented, or not (in which case there is default "always acts the same" behaviour, but it isn't guest programmable). QEMU is a bit confused about how we indicate this: we have an ARM_FEATURE_MPU, but it's not clear whether this indicates "PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we use it for one purpose and sometimes the other. Currently trying to implement a PMSA-without-MPU core won't work correctly because we turn off the ARM_FEATURE_MPU bit and then a lot of things which should still exist get turned off too. As the first step in cleaning this up, rename the feature bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with or without MPU). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-5-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Use different ARMMMUIdx values for M profilePeter Maydell3-2/+27
Make M profile use completely separate ARMMMUIdx values from those that A profile CPUs use. This is a prelude to adding support for the MPU and for v8M, which together will require 6 MMU indexes which don't map cleanly onto the A profile uses: non secure User non secure Privileged non secure Privileged, execution priority < 0 secure User secure Privileged secure Privileged, execution priority < 0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-4-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Add support for M profile CPUs having different MMU index semanticsPeter Maydell6-99/+156
The M profile CPU's MPU has an awkward corner case which we would like to implement with a different MMU index. We can avoid having to bump the number of MMU modes ARM uses, because some of our existing MMU indexes are only used by non-M-profile CPUs, so we can borrow one. To avoid that getting too confusing, clean up the code to try to keep the two meanings of the index separate. Instead of ARMMMUIdx enum values being identical to core QEMU MMU index values, they are now the core index values with some high bits set. Any particular CPU always uses the same high bits (so eventually A profile cores and M profile cores will use different bits). New functions arm_to_core_mmu_idx() and core_to_arm_mmu_idx() convert between the two. In general core index values are stored in 'int' types, and ARM values are stored in ARMMMUIdx types. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-3-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()Peter Maydell1-1/+1
When identifying the DFSR format for an alignment fault, use the mmu index that we are passed, rather than calling cpu_mmu_index() to get the mmu index for the current CPU state. This doesn't actually make any difference since the only cases where the current MMU index differs from the index used for the load are the "unprivileged load/store" instructions, and in that case the mmu index may differ but the translation regime is the same (apart from the "use from Hyp mode" case which is UNPREDICTABLE). However it's the more logical thing to do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-2-git-send-email-peter.maydell@linaro.org
2017-06-02target/arm: clear PMUVER field of AA64DFR0 when vPMU=offWei Huang1-1/+1
The PMUv3 driver of linux kernel (in arch/arm64/kernel/perf_event.c) relies on the PMUVER field of id_aa64dfr0_el1 to decide if PMU support is present or not. This patch clears the PMUVER field under TCG mode when vPMU=off. Without it, PMUv3 will init insider guest VMs even with vPMU=off. This patch also removes a redundant line inside the if-statement. Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1495123889-32301-1-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1Peter Maydell1-4/+38
When we calculate the mask to use to get the group priority from an interrupt priority, the way that NS BPR1 is handled differs from how BPR0 and S BPR1 work -- a BPR1 value of 1 means the group priority is in bits [7:1], whereas for BPR0 and S BPR1 this is indicated by a 0 BPR value. Subtract 1 from the BPR value before creating the mask if we're using the NS BPR value, for both hardware and virtual interrupts, as the GICv3 pseudocode does, and fix the comments accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493226792-3237-4-git-send-email-peter.maydell@linaro.org
2017-06-02hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimumPeter Maydell1-0/+6
icc_bpr_write() was not enforcing that writing a value below the minimum for the BPR should behave as if the BPR was set to the minimum value. This doesn't make a difference for the secure BPRs (since we define the minimum for the QEMU implementation as zero) but did mean we were allowing the NS BPR1 to be set to 0 when 1 should be the lowest value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493226792-3237-3-git-send-email-peter.maydell@linaro.org
2017-06-02hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1Peter Maydell1-1/+1
We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr() on reset, but this is not correct. The field should reset to the minimum value of ICV_BPR0_EL1 plus one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493226792-3237-2-git-send-email-peter.maydell@linaro.org
2017-06-02load_uboot_image: don't assume a full header readAndrew Jones1-1/+2
Don't allow load_uboot_image() to proceed when less bytes than header-size was read. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20170524091315.20284-1-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02libvixl: Correct build failures on NetBSDKamil Rytarowski1-0/+3
Ensure that C99 macros are defined regardless of the inclusion order of headers in vixl. This is required at least on NetBSD. The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be included before other system headers. This file defines unconditionally the following macros, without altering the original sources: - __STDC_CONSTANT_MACROS - __STDC_LIMIT_MACROS - __STDC_FORMAT_MACROS Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170514051820.15985-1-n54@gmx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02char: move char devices to chardev/Marc-André Lureau12-27/+28
Suggested by Paolo Bonzini during series review. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char: make chr_fe_deinit() optionaly delete backendMarc-André Lureau16-58/+34
This simplifies removing a backend for a frontend user (no need to retrieve the associated driver and separate delete call etc). NB: many frontends have questionable handling of ending a chardev. They should probably delete the backend to prevent broken reusage. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char: rename functions that are not part of feMarc-André Lureau1-8/+7
There is no clear reason to have those functions associated with frontend. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char: move CharBackend handling in char-fe unitMarc-André Lureau56-623/+664
Move all the frontend struct and methods to a seperate unit. This avoids accidentally mixing backend and frontend calls, and helps with readabilty. Make qemu_chr_replay() a macro shared by both char and char-fe. Export qemu_chr_write(), and use a macro for qemu_chr_write_all() (nb: yes, CharBackend is for char frontend :) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char: generalize qemu_chr_write_all()Marc-André Lureau1-42/+28
qemu_chr_fe_write() is similar to qemu_chr_write_all(): the later write all with a chardev backend. Make qemu_chr_write() and qemu_chr_fe_write_buffer() take an 'all' argument. If false, handle 'partial' write the way qemu_chr_fe_write() use to, and call qemu_chr_write() from qemu_chr_fe_write(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02be-hci: use backend functionsMarc-André Lureau1-6/+3
Avoid accessing CharBackend directly, use qemu_chr_be_* methods instead. be->chr_read should exists if qemu_chr_be_can_write() is true. (use qemu_chr_be_write(), _impl() bypasses replay) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Andrzej Zaborowski <balrogg@gmail.com>
2017-06-02chardev: serial & parallel declaration to own headersMarc-André Lureau12-46/+50
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02chardev: move headers to include/chardevMarc-André Lureau98-116/+117
So they are all in one place. The following patch will move serial & parallel declarations to the respective headers. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02Remove/replace sysemu/char.h inclusionMarc-André Lureau13-13/+1
Those are apparently unnecessary includes. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char-win: close file handle except with consoleMarc-André Lureau4-13/+8
Only the console handle shouldn't be closed, however, the "file" handle should. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char-win: rename hcom->fileMarc-André Lureau3-24/+24
hcom is the name of the file handle, regardless of the actual chardev driver (serial, file, console etc..). Rename it to be more explicit. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char-win: rename win_chr_init/poll win_chr_serial_init/pollMarc-André Lureau3-6/+6
Those 2 functions are specific to serial chardev, make it more clear. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char-win: remove WinChardev.lenMarc-André Lureau2-10/+7
The "len" argument can be passed directly to win_chr_read() Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char-win: simplify win_chr_read()Marc-André Lureau2-27/+10
win_chr_read_poll() is always used before win_chr_read(). We can easily fold win_chr_readfile() too. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02char: cast ARRAY_SIZE() as signed to silent warning on empty arrayPhilippe Mathieu-Daudé1-2/+2
chardev/char.c: In function 'chardev_name_foreach': chardev/char.c:546:19: error: comparison of unsigned expression < 0 is always false [-Werror=type-limits] for (i = 0; i < ARRAY_SIZE(chardev_alias_table); i++) { ^ Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170530120919.8874-1-f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
2017-06-02hw/sparc64: QOM'ify sun4u.cxiaoqiang zhao1-11/+9
Drop the old SysBusDeviceClass::init and use instance_init or DeviceClass::realize instead Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/sparc: QOM'ify sun4m.cxiaoqiang zhao1-35/+19
Drop the old SysBusDeviceClass::init and use instance_init or DeviceClass::realize instead Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/timer: QOM'ify slavio_timerxiaoqiang zhao1-7/+5
rename slavio_timer_init1 to slavio_timer_init and assign it to slavio_timer_info.instance_init, then we drop the SysBusDeviceClass::init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/timer: QOM'ify m48txx_sysbusxiaoqiang zhao1-19/+19
* split the old SysBus init function into an instance_init and a Device realize function * use DeviceClass::realize instead of SysBusDeviceClass::init * assign DeviceClass::vmsd instead of using vmstate_register function Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/misc: QOM'ify slavio_misc.cxiaoqiang zhao1-26/+17
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/dma: QOM'ify sun4m_iommu.cxiaoqiang zhao1-7/+5
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/dma: QOM'ify sparc32_dma.cxiaoqiang zhao1-10/+15
Drop the old SysBus init function and use instance_init and an realize function Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-02hw/misc: QOM'ify eccmemctl.cxiaoqiang zhao1-9/+16
* Split the old SysBus init into an instance_init and a DeviceClass::realize function * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2017-06-01migration: Move include/migration/block.h into migration/Juan Quintela6-6/+12
All functions were internal, except blk_mig_init() that is exported in misc.h now. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-06-01migration: Export ram.c functions in its own fileJuan Quintela9-39/+98
All functions are internal except for ram_mig_init(). Create migration/misc.h for this kind of functions. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-06-01migration: Create include for migration snapshotsJuan Quintela7-12/+34
Start removing migration code from sysemu/sysemu.h. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-06-01migration: Export rdma.c functions in its own fileJuan Quintela4-4/+27
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-06-01migration: Export tls.c functions in its own fileJuan Quintela5-11/+36
Just for the functions exported from tls.c. Notice that we can't remove the migration/migration.h include from tls.c because it access directly MigrationState for the tls params. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-06-01migration: Export socket.c functions in its own fileJuan Quintela4-8/+30
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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