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2018-02-16Merge remote-tracking branch 'remotes/berrange/tags/qio-next-pull-request' ↵Peter Maydell7-17/+48
into staging # gpg: Signature made Thu 15 Feb 2018 17:50:22 GMT # gpg: using RSA key BE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qio-next-pull-request: allow to build with older sed io/channel-command: Do not kill the child process after closing the pipe io: Add /dev/fdset/ support to QIOChannelFile io: Don't call close multiple times in QIOChannelFile io: Fix QIOChannelFile when creating and opening read-write io/channel-websock: handle continuous reads without any data io: fix QIONetListener memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-16tests/boot-serial-test: Fix problem with timeout due to dropped charactersThomas Huth1-2/+2
Commit 92b540dac9fc3a5 introduce a counter to handle the timeouts in a better way. But in case ccnt reaches 512, the current read character is ignored - and if that character is part of the string that we are looking for, the test fails to match the string. Almost all of the tests look for a string within the first 512 bytes of firmware output, so the problem never triggered there. But the hppa test that has been added recently looks for a longer string at the very end of a long output, thus there's a chance that we miss a character there so that the test fails unexpectedly. Fix it by *not* reading and dropping a character if the counter reaches 512. Fixes: 92b540dac9fc3a572c7342edd0b073000f5a6abf Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1518761564-9899-1-git-send-email-thuth@redhat.com [PMM: added initializer for nbd to silence false-positive warning from OpenBSD 6 compiler] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15Merge remote-tracking branch ↵Peter Maydell12-211/+429
'remotes/pmaydell/tags/pull-target-arm-20180215-1' into staging target-arm queue: * aspeed: code cleanup to use unimplemented_device * preparatory work for 'raspi3' RaspberryPi 3 machine model * more SVE prep work * v8M: add minor missing registers * v7M: fix bug where we weren't migrating v7m.other_sp * v7M: fix bugs in handling of interrupt registers for external interrupts beyond 32 # gpg: Signature made Thu 15 Feb 2018 18:34:40 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180215-1: raspi: Raspberry Pi 3 support bcm2836: Make CPU type configurable target/arm: Implement v8M MSPLIM and PSPLIM registers target/arm: Migrate v7m.other_sp target/arm: Add AIRCR to vmstate struct hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions target/arm: Implement writing to CONTROL_NS for v8M hw/intc/armv7m_nvic: Implement SCR hw/intc/armv7m_nvic: Implement cache ID registers hw/intc/armv7m_nvic: Implement v8M CPPWR register hw/intc/armv7m_nvic: Implement M profile cache maintenance ops hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC target/arm: Handle SVE registers when using clear_vec_high target/arm: Enforce access to ZCR_EL at translation target/arm: Suppress TB end for FPCR/FPSR target/arm: Enforce FP access to FPCR/FPSR target/arm: Remove ARM_CP_64BIT from ZCR_EL registers hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io hw/arm/aspeed: directly map the serial device to the system address space Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15raspi: Raspberry Pi 3 supportPekka Enberg1-10/+21
This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The differences to Pi 2 are: - Firmware address - Board ID - Board revision The CPU is different too, but that's going to be configured as part of the machine default CPU when we introduce a new machine type. The patch was written from scratch by me but the logic is similar to Zoltán Baldaszti's previous work, which I used as a reference (with permission from the author): https://github.com/bztsrc/qemu-raspi3 Signed-off-by: Pekka Enberg <penberg@iki.fi> [PMM: fixed trailing whitespace on one line] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15bcm2836: Make CPU type configurablePekka Enberg3-8/+13
This patch adds a "cpu-type" property to BCM2836 SoC in preparation for reusing the code for the Raspberry Pi 3, which has a different processor model. Signed-off-by: Pekka Enberg <penberg@iki.fi> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell3-0/+69
The v8M architecture includes hardware support for enforcing stack pointer limits. We don't implement this behaviour yet, but provide the MSPLIM and PSPLIM stack pointer limit registers as reads-as-written, so that when we do implement the checks in future this won't break guest migration. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-12-peter.maydell@linaro.org
2018-02-15target/arm: Migrate v7m.other_spPeter Maydell1-0/+11
In commit abc24d86cc0364f we accidentally broke migration of the stack pointer value for the mode (process, handler) the CPU is not currently running as. (The commit correctly removed the no-longer-used v7m.current_sp flag from the VMState but also deleted the still very much in use v7m.other_sp SP value field.) Add a subsection to migrate it again. (We don't need to care about trying to retain compatibility with pre-abc24d86cc0364f versions of QEMU, because that commit bumped the version_id and we've since bumped it again a couple of times.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-11-peter.maydell@linaro.org
2018-02-15target/arm: Add AIRCR to vmstate structPeter Maydell1-0/+4
In commit commit 3b2e934463121 we added support for the AIRCR register holding state, but forgot to add it to the vmstate structs. Since it only holds r/w state if the security extension is implemented, we can just add it to vmstate_m_security. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-10-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversionsPeter Maydell1-4/+4
In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>, NVIC_IABR<n> -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR<n> had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180209165810.6668-9-peter.maydell@linaro.org
2018-02-15target/arm: Implement writing to CONTROL_NS for v8MPeter Maydell1-0/+10
In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-8-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell3-4/+27
We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell3-0/+78
M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection Register (CSSELR) The only difference is that they're in the NVIC memory mapped register space rather than being coprocessor registers. Implement the M profile view of them. Since neither Cortex-M3 nor Cortex-M4 implement caches, we don't need to update their init functions and can leave the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. Newer cores (like the Cortex-M33) will want to be able to set these ID registers to non-zero values, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-6-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement v8M CPPWR registerPeter Maydell1-0/+14
The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-5-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Implement M profile cache maintenance opsPeter Maydell1-0/+12
For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-4-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handlingPeter Maydell1-3/+3
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-3-peter.maydell@linaro.org
2018-02-15hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell2-14/+44
Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M. (The values of the ID registers might be wrong for the M4 -- this commit leaves the behaviour there unchanged.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-2-peter.maydell@linaro.org
2018-02-15target/arm: Handle SVE registers when using clear_vec_highRichard Henderson1-100/+62
When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. Therefore, call it more often with is_q as a parameter. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Enforce access to ZCR_EL at translationRichard Henderson4-19/+28
This also makes sure that we get the correct ordering of SVE vs FP exceptions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Suppress TB end for FPCR/FPSRRichard Henderson1-2/+2
Nothing in either register affects the TB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Enforce FP access to FPCR/FPSRRichard Henderson3-19/+25
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15target/arm: Remove ARM_CP_64BIT from ZCR_EL registersRichard Henderson1-4/+4
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.ioPhilippe Mathieu-Daudé2-30/+3
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom - 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io + 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180209085755.30414-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15hw/arm/aspeed: directly map the serial device to the system address spacePhilippe Mathieu-Daudé1-1/+2
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io - 000000001e784000-000000001e78401f (prio 0, i/o): serial 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 [...] 000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram 000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer + 000000001e784000-000000001e78401f (prio 0, i/o): serial 000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt 000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180209085755.30414-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15allow to build with older sedJan Beulich1-2/+1
sed's -E option may not be supported by older distros. As there's no point using sed here at all, use just shell mechanisms to establish the variable values, starting from the stem instead of the full target. Signed-off-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15io/channel-command: Do not kill the child process after closing the pipeThomas Huth1-1/+11
We are currently facing some migration failure on s390x when running certain avocado-vt tests, e.g. when running the test type_specific.io-github-autotest-qemu.migrate.with_reboot.exec.gzip_exec. This test is using 'migrate -d "exec:nc localhost 5200"' for the migration. The problem is detected at the receiving side, where the migration stream apparently ends too early. However, the cause for the problem is at the sending side: After writing the migration stream into the pipe to netcat, the source QEMU calls qio_channel_command_close() which closes the pipe and immediately (!) kills the child process afterwards (via the function qio_channel_command_abort()). So if the sending netcat did not read the final bytes from the pipe yet, or if it did not manage to send out all its buffers yet, it is killed before the whole migration stream is passed to the destination side. QEMU can not know how much time is required by the child process to send over all migration data, so we should not kill it, neither directly nor after a delay. Let's simply wait for the child process to exit gracefully instead (this was also the behaviour of pclose() that was used in "exec:" migration before the QIOChannel rework). Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-02-15io: Add /dev/fdset/ support to QIOChannelFileRoss Lagerwall1-3/+3
Add /dev/fdset/ support to QIOChannelFile by calling qemu_open() instead of open() and qemu_close() instead of close(). There is a subtle semantic change since qemu_open() automatically sets O_CLOEXEC, but this doesn't affect any of the users of the function. Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15io: Don't call close multiple times in QIOChannelFileRoss Lagerwall1-0/+1
If the file descriptor underlying QIOChannelFile is closed in the io_close() method, don't close it again in the finalize() method since the file descriptor number may have been reused in the meantime. Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15io: Fix QIOChannelFile when creating and opening read-writeRoss Lagerwall3-10/+27
The code wrongly passes the mode to open() only if O_WRONLY is set. Instead, the mode should be passed when O_CREAT is set (or O_TMPFILE on Linux). Fix this by always passing the mode since open() will correctly ignore the mode if it is not needed. Add a testcase which exercises this bug and also change the existing testcase to check that the mode of the created file is correct. Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15io/channel-websock: handle continuous reads without any dataEdgar Kaziakhmedov1-2/+5
According to the current implementation of websocket protocol in QEMU, qio_channel_websock_handshake_io tries to read handshake from the channel to start communication over socket. But this approach doesn't cover scenario when socket was closed while handshaking. Therefore, if G_IO_IN is caught and qio_channel_read returns zero, error has to be set and connection has to be done. Such behaviour causes 100% CPU load in main QEMU loop, because main loop poll continues to receive and handle G_IO_IN events from websocket. Step to reproduce 100% CPU load: 1) start qemu with the simplest configuration $ qemu -vnc [::1]:1,websocket=7500 2) open any vnc listener (which doesn't follow websocket protocol) $ vncviewer :7500 3) kill listener 4) qemu main thread eats 100% CPU Signed-off-by: Edgar Kaziakhmedov <edgar.kaziakhmedov@virtuozzo.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15io: fix QIONetListener memory leakPaolo Bonzini1-0/+1
The sources array does not escape out of qio_net_listener_wait_client, so we have to free it. Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2018-02-15Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell3-8/+15
staging Pull request v2: * Dropped Fam's git-publish series because there is still ongoing discussion # gpg: Signature made Thu 15 Feb 2018 09:42:03 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: misc: fix spelling ratelimit: don't align wait time with slices vl: pause vcpus before stopping iothreads Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15Merge remote-tracking branch 'remotes/huth/tags/pull-request-2018-02-14' ↵Peter Maydell55-374/+416
into staging Various improvements to the qtest checks: - Clean-ups by Eric Blake with regards to the global_qtest variable - Some more test cases for the boot-serial tester - Re-activation of the m48t59-test # gpg: Signature made Wed 14 Feb 2018 11:07:44 GMT # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" # gpg: aka "Thomas Huth <thuth@redhat.com>" # gpg: aka "Thomas Huth <huth@tuxfamily.org>" # gpg: aka "Thomas Huth <th.huth@posteo.de>" # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth/tags/pull-request-2018-02-14: tests/m48t59: Use the m48t59 test on ppc, too tests/Makefile: Derive check-qtest-ppc64-y from check-qtest-ppc-y tests/m48t59: Make the test independent of global_qtest tests/m48t59: Fix and re-enable the test for sparc tests/boot-serial-test: Add support for the aarch64 virt machine tests/boot-serial: Add tests for PowerPC Mac machines tests/boot-serial: Enable the boot-serial test on SPARC machines, too wdt_ib700-test: Drop dependence on global_qtest tests/boot-sector: Drop dependence on global_qtest qmp-test: Drop dependence on global_qtest libqos: Use explicit QTestState for remaining libqos operations libqos: Use explicit QTestState for ahci operations libqos: Use explicit QTestState for i2c operations libqos: Use explicit QTestState for rtas operations libqos: Use explicit QTestState for fw_cfg operations libqos: Track QTestState with QPCIBus libqtest: Use qemu_strtoul() tests: Clean up wait for event Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15Merge remote-tracking branch ↵Peter Maydell3-0/+49
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Wed 14 Feb 2018 10:37:02 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: m68k: implement movep instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-15misc: fix spellingMarc-André Lureau1-1/+1
s/pupulate/populate Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180208162447.10851-1-marcandre.lureau@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-15ratelimit: don't align wait time with slicesWolfgang Bumiller1-6/+5
It is possible for rate limited writes to keep overshooting a slice's quota by a tiny amount causing the slice-aligned waiting period to effectively halve the rate. Signed-off-by: Wolfgang Bumiller <w.bumiller@proxmox.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Message-id: 20180207071758.6818-1-w.bumiller@proxmox.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-15vl: pause vcpus before stopping iothreadsStefan Hajnoczi1-1/+9
Commit dce8921b2baaf95974af8176406881872067adfa ("iothread: Stop threads before main() quits") introduced iothread_stop_all() to avoid the following virtio-scsi assertion failure: assert(blk_get_aio_context(d->conf.blk) == s->ctx); Back then the assertion failed because when bdrv_close_all() made d->conf.blk NULL, blk_get_aio_context() returned the global AioContext instead of s->ctx. The same assertion can still fail today when vcpus submit new I/O requests after iothread_stop_all() has moved the BDS to the global AioContext. This patch hardens the iothread_stop_all() approach by pausing vcpus before calling iothread_stop_all(). Note that the assertion failure is a race condition. It is not possible to reproduce it reliably. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180201110708.8080-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-02-14tests/m48t59: Use the m48t59 test on ppc, tooThomas Huth2-1/+10
The ref405ep machine has a memory-mapped m48t59 device, so we can run the m48t59 test on this machine, too. Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/Makefile: Derive check-qtest-ppc64-y from check-qtest-ppc-yThomas Huth1-7/+4
ppc64 is a superset of ppc, so the ppc64 tests should include all the ppc tests. Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/m48t59: Make the test independent of global_qtestThomas Huth1-30/+30
Stop using the functions that require global_qtest here and pass around the QTestState instead (global_qtest should finally get removed since this causes problems with tests running in parallel). Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/m48t59: Fix and re-enable the test for sparcThomas Huth2-30/+34
The m48t59 test has been disabled in commit baeddded5fe6fa37d13fb94bf8d ("sparc: disable qtest in make check"), likely due to some timing issues in the bcd_check_time tests which might fail if it gets interrupted for too long. It should be OK to re-enable this test if we make sure that we do not run it on timing-sensitive machines, thus it should be OK if we only run it in the g_test_slow() mode. Additionally, there are two other issues: First, the test can not run so easily on sparc64 anymore, since commit f3b18f35a23c60edbda6420cd ("sun4u: switch m48t59 NVRAM to MMIO access") moved the m48t59 device to the ebus instead, and for this you first have to set up the corresponding PCI device (which is currently not possible from within the m48t59 test). So we can only re-enable this test on sparc, but not the sparc64 target. Second, the fuzzing test is executed before the bcd-check-time test (due to the naming of the tests), without having the base address set up properly, so the fuzzing test does not really check anything at all. Fix it by setting up the base address from the main function already and by moving the qtest_start() to the tests themselves, so that each test starts with a clean environment (since after the fuzzing, the clock is unusable for the bcd-check-time test). Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-serial-test: Add support for the aarch64 virt machineWei Huang2-0/+10
This patch adds a small binary kernel to test aarch64 virt machine's UART. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> [thuth: Fixed contextual conflicts with the hppa and sdhci patches] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-serial: Add tests for PowerPC Mac machinesThomas Huth1-0/+3
OpenBIOS prints out the CPU type on these machine types, so we can use this string to test whether the CPU detection is working correctly. Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-serial: Enable the boot-serial test on SPARC machines, tooThomas Huth2-0/+6
OpenBIOS prints out the name of the detected CPU here, so looking for this string is a nice test to verify that the CPU detection is still working correctly. Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14wdt_ib700-test: Drop dependence on global_qtestEric Blake1-29/+34
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Improve this test to be explicit about the state. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14tests/boot-sector: Drop dependence on global_qtestEric Blake5-9/+11
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Adjust the helper code to use explicit state instead, and update all callers. Fix some trailing whitespace while touching the file. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14qmp-test: Drop dependence on global_qtestEric Blake1-17/+18
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Although qmp-test does not maintain parallel qtest connections, it was the last test assigning to global_qtest. It's just as easy to be explicit about the state; once all tests have been cleaned up, a later patch can then get rid of global_qtest and a layer of wrappers in libqtest. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for remaining libqos operationsEric Blake11-35/+39
Drop one more client of global_qtest by teaching all remaining libqos stragglers to pass in an explicit QTestState. Change the setting of global_qtest from being implicit in libqos' call to qtest_start() to instead be explicit in all clients that are still relying on global_qtest. Note that qmp_execute() can be greatly simplified in the process, and that we also get rid of interpolation of a JSON string into a temporary variable when qtest_qmp() can do it more reliably. Signed-off-by: Eric Blake <eblake@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Reviewed-by: John Snow <jsnow@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for ahci operationsEric Blake1-22/+23
Drop one more client of global_qtest by teaching all ahci test functionality to pass in an explicit QTestState. The state was already available, so no callers had to be adjusted. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for i2c operationsEric Blake5-65/+66
Drop one more client of global_qtest by teaching all i2c test functionality to pass in an explicit QTestState, adjusting all callers. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-02-14libqos: Use explicit QTestState for rtas operationsEric Blake4-28/+40
Drop one more client of global_qtest by teaching all rtas test functionality to pass in an explicit QTestState, adjusting all callers. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Use nicer indentation in rtas.h] Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.1 at 2025-01-22 05:02:26 +0000