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2014-11-03vga: flip qemu 2.2 pc machine types from cirrus to stdvgaGerd Hoffmann2-4/+10
This patch switches the default display from cirrus to vga for the new (qemu 2.2+) machine types. Old machines types stay as-is for compatibility reasons. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-11-03vga: add default display to machine classGerd Hoffmann3-1/+7
This allows machine classes to specify which display device they want as default. If unspecified the current behavior (try cirrus, failing that try stdvga, failing that use no display) will be used. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-11-03vhost-user: fix mmap offset calculationMichael S. Tsirkin1-1/+1
qemu_get_ram_block_host_ptr should get ram_addr_t, vhost-user passes in GPA. That's very wrong. Reported-by: Linhaifeng <haifeng.lin@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-11-03Merge remote-tracking branch ↵Peter Maydell21-82/+59
'remotes/mjt/tags/pull-trivial-patches-2014-11-02' into staging trivial patches for 2014-11-02 # gpg: Signature made Sun 02 Nov 2014 11:54:43 GMT using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2014-11-02: (23 commits) vdi: wrapped uuid_unparse() in #ifdef tap: fix possible fd leak in net_init_tap tap: do not close(fd) in net_init_tap_one target-i386: Remove unused model_features_t struct tap_int.h: remove repeating NETWORK_SCRIPT defines os-posix: reorder parent notification for -daemonize pidfile: stop making pidfile error a special case os-posix: replace goto again with a proper loop os-posix: use global daemon_pipe instead of cryptic fds[1] dump: Fix dump-guest-memory termination and use-after-close virtio-9p-proxy: improve error messages in connect_namedsocket() virtio-9p-proxy: fix error return in proxy_init() virtio-9p-proxy: Fix sockfd leak target-tricore: check return value before using it net/slirp: specify logbase for smbd Revert "os-posix: report error message when lock file failed" util: Improve os_mem_prealloc error message sparse: fix build target-arm: A64: remove redundant store target-xtensa: mark XtensaConfig structs as unused ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-03Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell27-332/+824
The last round of patches for soft freeze. Includes ivshmem bugfixes, megasas 2108 emulation, and other small patches here and there. # gpg: Signature made Fri 31 Oct 2014 17:17:54 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (35 commits) virtio-scsi: fix dataplane ivshmem: use error_report ivshmem: Fix fd leak on error ivshmem: Fix potential OOB r/w access ivshmem: validate incoming_posn value from server ivshmem: Check ivshmem_read() size argument i386: fix breakpoints handling in icount mode kvm_stat: Add powerpc support kvm_stat: Abstract ioctl numbers kvm_stat: Rework platform detection kvm_stat: Fix the non-x86 exit reasons kvm_stat: Only consider online cpus virtio-scsi: Fix num_queue input validation scsi: devirtualize unrealize of SCSI devices virtio-scsi: Fix memory leak when realize failed iscsi: Refuse to open as writable if the LUN is write protected kvmvapic: patch_instruction fix vl.c: Fix Coverity complaining for vmstate_dump_file Add skip_dump flag to ignore memory region during dump -machine vmport=off: Allow disabling of VMWare ioport emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-03target-mips: add MSA support to mips32r5-genericYongbok Kim1-2/+2
add MSA support to mips32r5-generic core definition Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03disas/mips.c: disassemble MSA instructionsYongbok Kim1-2/+714
disassemble MIPS SIMD Architecture instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim3-5/+131
add MSA MI10 format instructions update LSA and DLSA for MSA add 16, 64 bit load and store Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim3-0/+621
add MSA 2RF format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim3-0/+265
add MSA VEC/2R format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim3-0/+1699
add MSA 3RF format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim3-0/+290
add MSA ELM format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim3-0/+963
add MSA 3R format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim3-0/+297
add MSA BIT format instructions Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim3-0/+232
add MSA I5 format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim3-2/+156
add MSA I8 format instructions Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA branch instructionsYongbok Kim1-114/+220
add MSA branch instructions Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add msa_helper.cYongbok Kim2-1/+50
add msa_helper.c Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim2-0/+90
add msa_reset() and global msa register (d type only) Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA opcode enumYongbok Kim1-0/+245
add MSA opcode enum Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: stop translation after ctc1Yongbok Kim1-0/+6
stop translation as ctc1 instruction can change hflags Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim3-9/+6
Remove the duplicated ieee_rm in gdbstub.c. Make the other ieee_rm and ieee_ex_to_mips available to other files. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA exceptionsYongbok Kim1-0/+10
add MSA exceptions Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA defines and data structureYongbok Kim3-2/+52
add defines and data structure for MIPS SIMD Architecture Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: enable features in MIPS64R6-generic CPULeon Alrae1-2/+9
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae1-278/+260
Release 6 limits the number of cases where software can cause UNDEFINED or UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented CP0 register, writes are ignored and reads return 0. In pre-R6 the behaviour is not specified, but generating RI exception is not what the real HW does. Additionally, remove CP0 Random register as it became reserved in Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add restrictions for possible values in registersLeon Alrae1-17/+53
In Release 6 not all the values are allowed to be written to a register. If the value is not valid or unsupported then it should stay unchanged. For pre-R6 the existing behaviour has been changed only for CP0_Index register as the current implementation does not seem to be correct - it looks like it tries to limit the input value but the limit is higher than the actual number of tlb entries. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae1-1/+2
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: implement forbidden slotLeon Alrae2-36/+76
When conditional compact branch is encountered decode one more instruction in current translation block - that will be forbidden slot. Instruction in forbidden slot will be executed only if conditional compact branch is not taken. Any control transfer instruction (CTI) which are branches, jumps, ERET, DERET, WAIT and PAUSE will generate RI exception if executed in forbidden or delay slot. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add Config5.SBRILeon Alrae2-3/+32
SDBBP instruction Reserved Instruction control. The purpose of this field is to restrict availability of SDBBP to kernel mode operation. If the bit is set then SDBBP instruction can only be executed in kernel mode. User execution of SDBBP will cause a Reserved Instruction exception. Additionally add missing Config4 and Config5 cases for dm{f,t}c0. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2-2/+26
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae4-11/+133
BadInstr Register (CP0 Register 8, Select 1) The BadInstr register is a read-only register that capture the most recent instruction which caused an exception. BadInstrP Register (CP0 Register 8, Select 2) The BadInstrP register contains the prior branch instruction, when the faulting instruction is in a branch delay slot. Using error_code to indicate whether AdEL or TLBL was triggered during instruction fetch, in this case BadInstr is not updated as valid instruction word is not available. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add TLBINV supportLeon Alrae7-8/+94
For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae2-2/+28
An Execute-Inhibit exception occurs when the virtual address of an instruction fetch matches a TLB entry whose XI bit is set. This exception type can only occur if the XI bit is implemented within the TLB and is enabled, this is denoted by the PageGrain XIE bit. An Read-Inhibit exception occurs when the virtual address of a memory load reference matches a TLB entry whose RI bit is set. This exception type can only occur if the RI bit is implemented within the TLB and is enabled, this is denoted by the PageGrain RIE bit. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae5-5/+57
PageGrain needs rw bitmask which differs between MIPS architectures. In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable, whereas in R6 they are read-only 1. On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward compatiblity, therefore there are separate mtc0 and dmtc0 helpers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae3-1/+29
In Revision 3 of the architecture, the RI and XI bits were added to the TLB to enable more secure access of memory pages. These bits (along with the Dirty bit) allow the implementation of read-only, write-only, no-execute access policies for mapped pages. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: distinguish between data load and instruction fetchLeon Alrae1-11/+10
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03softmmu: provide softmmu access type enumLeon Alrae2-10/+22
New MIPS features depend on the access type and enum is more convenient than using the numbers directly. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
2014-11-03target-mips: add KScratch registersLeon Alrae2-0/+47
KScratch<n> Registers (CP0 Register 31, Selects 2 to 7) The KScratch registers are read/write registers available for scratch pad storage by kernel mode software. They are 32-bits in width for 32-bit processors and 64-bits for 64-bit processors. CP0Config4.KScrExist[2:7] bits indicate presence of CP0_KScratch1-6 registers. For Release 6, all KScratch registers are required. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03block: declare blockjobs and dataplane friends!Stefan Hajnoczi2-0/+6
Now that blockjobs use AioContext they are safe for use with dataplane. Unblock them! Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-12-git-send-email-stefanha@redhat.com
2014-11-03block: let commit blockjob run in BDS AioContextStefan Hajnoczi2-35/+64
The commit block job must run in the BlockDriverState AioContext so that it works with dataplane. Acquire the AioContext in blockdev.c so starting the block job is safe. One detail here is that the bdrv_drain_all() must be moved inside the aio_context_acquire() region so requests cannot sneak in between the drain and acquire. The completion code in block/commit.c must perform backing chain manipulation and bdrv_reopen() from the main loop. Use block_job_defer_to_main_loop() to achieve that. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-11-git-send-email-stefanha@redhat.com
2014-11-03block: let mirror blockjob run in BDS AioContextStefan Hajnoczi3-39/+97
The mirror block job must run in the BlockDriverState AioContext so that it works with dataplane. Acquire the AioContext in blockdev.c so starting the block job is safe. Note that to_replace is treated separately from other BlockDriverStates in that it does not need to be in the same AioContext. Explicitly acquire/release to_replace's AioContext when accessing it. The completion code in block/mirror.c must perform BDS graph manipulation and bdrv_reopen() from the main loop. Use block_job_defer_to_main_loop() to achieve that. The bdrv_drain_all() call is not allowed outside the main loop since it could lead to lock ordering problems. Use bdrv_drain(bs) instead because we have acquired the AioContext so nothing else can sneak in I/O. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-10-git-send-email-stefanha@redhat.com
2014-11-03block: let stream blockjob run in BDS AioContextStefan Hajnoczi2-18/+48
The stream block job must run in the BlockDriverState AioContext so that it works with dataplane. The basics of acquiring the AioContext are easy in blockdev.c. The tricky part is the completion code which drops part of the backing file chain. This must be done in the main loop where bdrv_unref() and bdrv_close() are safe to call. Use block_job_defer_to_main_loop() to achieve that. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-9-git-send-email-stefanha@redhat.com
2014-11-03block: let backup blockjob run in BDS AioContextStefan Hajnoczi2-9/+35
The backup block job must run in the BlockDriverState AioContext so that it works with dataplane. The basics of acquiring the AioContext are easy in blockdev.c. The completion code in block/backup.c must call bdrv_unref() from the main loop. Use block_job_defer_to_main_loop() to achieve that. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-8-git-send-email-stefanha@redhat.com
2014-11-03block: add bdrv_drain()Stefan Hajnoczi2-7/+30
Now that op blockers are in use, we can ensure that no other sources are generating I/O on a BlockDriverState. Therefore it is possible to drain requests for a single BDS. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-7-git-send-email-stefanha@redhat.com
2014-11-03blockjob: add block_job_defer_to_main_loop()Stefan Hajnoczi2-0/+64
Block jobs will run in the BlockDriverState's AioContext, which may not always be the QEMU main loop. There are some block layer APIs that are either not thread-safe or risk lock ordering problems. This includes bdrv_unref(), bdrv_close(), and anything that calls bdrv_drain_all(). The block_job_defer_to_main_loop() API allows a block job to schedule a function to run in the main loop with the BlockDriverState AioContext held. This function will be used to perform cleanup and backing chain manipulations in block jobs. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-6-git-send-email-stefanha@redhat.com
2014-11-03blockdev: add note that block_job_cb() must be thread-safeStefan Hajnoczi1-0/+5
This function is correct but we should document the constraint that everything must be thread-safe. Emitting QMP events and scheduling BHs are both thread-safe so nothing needs to be done here. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-5-git-send-email-stefanha@redhat.com
2014-11-03blockdev: acquire AioContext in blockdev_mark_auto_del()Stefan Hajnoczi1-0/+7
When an emulated storage controller is unrealized it will call blockdev_mark_auto_del(). This will cancel any running block job (and that eventually releases its reference to the BDS so it can be freed). Since the block job may be executing in another AioContext we must acquire/release to ensure thread safety. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-4-git-send-email-stefanha@redhat.com
2014-11-03blockdev: acquire AioContext in do_qmp_query_block_jobs_one()Stefan Hajnoczi1-0/+6
Make sure that query-block-jobs acquires the BlockDriverState AioContext so that the blockjob isn't running in another thread while we access its state. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-3-git-send-email-stefanha@redhat.com
2014-11-03block: acquire AioContext in generic blockjob QMP commandsStefan Hajnoczi1-13/+39
block-job-set-speed, block-job-cancel, block-job-pause, block-job-resume, and block-job-complete must acquire the BlockDriverState AioContext so that it is safe to access bs. At the moment bs->job is always NULL when dataplane is active because op blockers prevent blockjobs from starting. Once the rest of the blockjob API has been made aware of AioContext we can drop the op blocker. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 1413889440-32577-2-git-send-email-stefanha@redhat.com
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