riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-01-28	hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method	Francisco Iglesias	2	-2/+34
2022-01-28	include/hw/dma/xlnx_csu_dma: Add in missing includes in the header	Francisco Iglesias	1	-0/+5
2022-01-28	hw/arm/xlnx-versal: Connect Versal's PMC SLCR	Francisco Iglesias	2	-1/+75
2022-01-28	hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models	Francisco Iglesias	3	-5/+30
2022-01-28	hw/misc: Add a model of Versal's PMC SLCR	Francisco Iglesias	3	-1/+1528
2022-01-28	rtc: Move RTC function prototypes to their own header	Peter Maydell	24	-25/+80
2022-01-28	hw/char/exynos4210_uart: Fix crash on trying to load VM state	Peter Maydell	1	-1/+1
2022-01-28	hw/armv7m: Fix broken VMStateDescription	Peter Maydell	1	-2/+2
2022-01-28	Update copyright dates to 2022	Peter Maydell	2	-2/+2
2022-01-28	Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20220127' into st...	Peter Maydell	2	-3/+11
2022-01-27	Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2022-01-27-v2' in...	Peter Maydell	14	-27/+190
2022-01-27	xen-mapcache: Avoid entry->lock overflow	Ross Lagerwall	1	-1/+7
2022-01-27	xen-hvm: Allow disabling buffer_io_timer	Jason Andryuk	1	-2/+4
2022-01-27	qapi: generate trace events by default	Vladimir Sementsov-Ogievskiy	4	-7/+9
2022-01-27	meson: document why we don't generate trace events for tests/ and qga/	Vladimir Sementsov-Ogievskiy	2	-0/+14
2022-01-27	docs/qapi-code-gen: update to cover trace events code generation	Vladimir Sementsov-Ogievskiy	2	-0/+25
2022-01-27	meson: generate trace events for qmp commands	Vladimir Sementsov-Ogievskiy	3	-4/+19
2022-01-27	qapi/commands: Optionally generate trace for QMP commands	Vladimir Sementsov-Ogievskiy	2	-14/+90
2022-01-27	qapi/commands: refactor error handling code	Vladimir Sementsov-Ogievskiy	2	-4/+8
2022-01-27	qapi/gen: Add FOO.trace-events output module	Vladimir Sementsov-Ogievskiy	1	-4/+27
2022-01-27	schemas: add missing vim modeline	Victor Toso	4	-0/+4
2022-01-26	Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-2022...	Peter Maydell	1	-0/+27
2022-01-26	virtiofsd: Drop membership of all supplementary groups (CVE-2022-0358)	Vivek Goyal	1	-0/+27
2022-01-22	Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' ...	Peter Maydell	24	-90/+151
2022-01-21	scripts/render-block-graph: switch to AQMP	John Snow	1	-5/+3
2022-01-21	scripts/cpu-x86-uarch-abi: switch to AQMP	John Snow	1	-2/+2
2022-01-21	scripts/cpu-x86-uarch-abi: fix CLI parsing	John Snow	1	-2/+1
2022-01-21	python: move qmp-shell under the AQMP package	John Snow	4	-3/+3
2022-01-21	python: move qmp utilities to python/qemu/utils	John Snow	11	-14/+14
2022-01-21	python/qmp: switch qmp-shell to AQMP	John Snow	2	-14/+20
2022-01-21	python/qmp: switch qom tools to AQMP	John Snow	3	-8/+11
2022-01-21	python/qmp: switch qemu-ga-client to AQMP	John Snow	1	-11/+11
2022-01-21	python/qemu-ga-client: don't use deprecated CLI syntax in usage comment	John Snow	1	-1/+1
2022-01-21	python/aqmp: rename AQMPError to QMPError	John Snow	6	-21/+21
2022-01-21	python/aqmp: add SocketAddrT to package root	John Snow	1	-1/+9
2022-01-21	python/aqmp: copy type definitions from qmp	John Snow	2	-8/+30
2022-01-21	python/aqmp: handle asyncio.TimeoutError on execute()	John Snow	1	-2/+6
2022-01-21	python/aqmp: add __del__ method to legacy interface	John Snow	1	-0/+18
2022-01-21	python/aqmp: fix docstring typo	John Snow	1	-1/+1
2022-01-21	python: use avocado's "new" runner	John Snow	1	-1/+1
2022-01-21	python: pin setuptools below v60.0.0	John Snow	2	-0/+3
2022-01-21	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220...	Peter Maydell	42	-356/+1608
2022-01-21	target/riscv: Relax UXL field for debugging	LIU Zhiwei	1	-4/+4
2022-01-21	target/riscv: Enable uxl field write	LIU Zhiwei	2	-6/+25
2022-01-21	target/riscv: Set default XLEN for hypervisor	LIU Zhiwei	1	-0/+10
2022-01-21	target/riscv: Adjust scalar reg in vector with XLEN	LIU Zhiwei	1	-1/+1
2022-01-21	target/riscv: Adjust vector address with mask	LIU Zhiwei	1	-10/+15
2022-01-21	target/riscv: Fix check range for first fault only	LIU Zhiwei	1	-2/+2
2022-01-21	target/riscv: Remove VILL field in VTYPE	LIU Zhiwei	1	-1/+0
2022-01-21	target/riscv: Adjust vsetvl according to XLEN	LIU Zhiwei	2	-2/+10