riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-28	Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v...	Peter Maydell	10	-210/+922
2019-05-28	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf0' i...	Peter Maydell	27	-514/+1053
2019-05-28	Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...	Peter Maydell	22	-187/+146
2019-05-26	BootLinuxSshTest: Test some userspace commands on Malta	Philippe Mathieu-Daudé	3	-0/+232
2019-05-26	target/mips: realign comments to fix checkpatch warnings	Jules Irenge	1	-12/+22
2019-05-26	target/mips: add or remove space to fix checkpatch errors	Jules Irenge	1	-81/+94
2019-05-26	linux-user: fix __NR_semtimedop undeclared error	Laurent Vivier	1	-8/+16
2019-05-26	mips: Decide to map PAGE_EXEC in map_address	Jakub Jermář	1	-5/+8
2019-05-26	target/mips: Refactor and fix INSERT.<B\|H\|W\|D> instructions	Mateja Marjanovic	3	-18/+71
2019-05-26	target/mips: Refactor and fix COPY_U.<B\|H\|W> instructions	Mateja Marjanovic	3	-21/+59
2019-05-26	target/mips: Refactor and fix COPY_S.<B\|H\|W\|D> instructions	Mateja Marjanovic	3	-21/+67
2019-05-26	target/mips: Fix MSA instructions ST.<B\|H\|W\|D> on big endian host	Mateja Marjanovic	1	-20/+180
2019-05-26	target/mips: Fix MSA instructions LD.<B\|H\|W\|D> on big endian host	Mateja Marjanovic	1	-20/+168
2019-05-26	target/mips: Make the results of MOD_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic	1	-2/+2
2019-05-26	target/mips: Make the results of DIV_<U\|S>.<B\|H\|W\|D> the same as on hardware	Mateja Marjanovic	1	-2/+3
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens	1	-1/+3
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens	1	-2/+5
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson	2	-3/+14
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis	1	-0/+11
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis	1	-0/+18
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis	1	-3/+6
2019-05-24	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis	1	-9/+8
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis	1	-3/+2
2019-05-24	target/riscv: Improve the scause logic	Alistair Francis	1	-1/+1
2019-05-24	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis	2	-8/+27
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis	1	-1/+1
2019-05-24	riscv: spike: Add a generic spike machine	Alistair Francis	2	-1/+111
2019-05-24	target/riscv: Deprecate the generic no MMU CPUs	Alistair Francis	1	-0/+6
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	4	-2/+27
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis	2	-0/+57
2019-05-24	riscv: virt: Allow specifying a CPU via commandline	Alistair Francis	1	-1/+2
2019-05-24	linux-user/riscv: Add the CPU type as a comment	Alistair Francis	1	-0/+1
2019-05-24	target/riscv: Remove unused include of riscv_htif.h for virt board riscv	Jonathan Behrens	1	-1/+0
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson	1	-8/+8
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson	2	-9/+24
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson	6	-151/+67
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson	3	-69/+29
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson	3	-53/+12
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson	2	-170/+58
2019-05-24	target/riscv: Use --static-decode for decodetree	Richard Henderson	2	-7/+4
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson	2	-3/+25
2019-05-24	RISC-V: fix single stepping over ret and other branching instructions	Fabien Chouteau	3	-12/+32
2019-05-24	target/riscv: Do not allow sfence.vma from user mode	Jonathan Behrens	1	-3/+4
2019-05-24	SiFive RISC-V GPIO Device	Fabien Chouteau	7	-4/+501
2019-05-24	hw/intc/nvic: Use object_initialize_child for correct reference counting	Philippe Mathieu-Daudé	1	-3/+3
2019-05-24	hw/arm/mps2: Use object_initialize_child for correct reference counting	Philippe Mathieu-Daudé	2	-8/+8
2019-05-24	hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting	Philippe Mathieu-Daudé	1	-3/+3
2019-05-24	hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting	Philippe Mathieu-Daudé	1	-3/+4
2019-05-24	hw/microblaze/zynqmp: Let the SoC manage the IPI devices	Philippe Mathieu-Daudé	1	-20/+16
2019-05-24	hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state	Philippe Mathieu-Daudé	1	-7/+7