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2017-09-08PPC: KVM: Support machine option to set VSMT modeSam Bobroff5-15/+126
KVM now allows writing to KVM_CAP_PPC_SMT which has previously been read only. Doing so causes KVM to act, for that VM, as if the host's SMT mode was the given value. This is particularly important on Power 9 systems because their default value is 1, but they are able to support values up to 8. This patch introduces a way to control this capability via a new machine property called VSMT ("Virtual SMT"). If the value is not set on the command line a default is chosen that is, when possible, compatible with legacy systems. Note that the intialization of KVM_CAP_PPC_SMT has changed slightly because it has changed (in KVM) from a global capability to a VM-specific one. This won't cause a problem on older KVMs because VM capabilities fall back to global ones. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr: fallback to raw mode if best compat mode cannot be set during CASGreg Kurz1-4/+14
KVM PR doesn't allow to set a compat mode. This causes ppc_set_compat_all() to fail and we return H_HARDWARE to the guest right away. This is excessive: even if we favor compat mode since commit 152ef803ceb19, we should at least fallback to raw mode if the guest supports it. This patch modifies cas_check_pvr() so that it also reports that the real PVR was found in the table supplied by the guest. Note that this is only makes sense if raw mode isn't explicitely disabled (ie, the user didn't set the machine "max-cpu-compat" property). If this is the case, we can simply ignore ppc_set_compat_all() failures, and let the guest run in raw mode. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08hw/nvram/spapr_nvram: Device can not be created by the usersThomas Huth1-0/+2
Trying to add a spapr-nvram device currently aborts QEMU like this: $ ppc64-softmmu/qemu-system-ppc64 -device spapr-nvram qemu-system-ppc64: hw/ppc/spapr_rtas.c:407: spapr_rtas_register: Assertion `!rtas_table[token].name' failed. Aborted (core dumped) This NVRAM device registers RTAS calls during its realize function and thus can only be used once - and that's internally from spapr.c. So let's mark the device with user_creatable = false to avoid that the users can crash their QEMU this way. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08hw/ppc/spapr_cpu_core: Add a proper check for spapr machineThomas Huth2-0/+8
QEMU currently crashes when the user tries to add a spapr-cpu-core on a non-pseries machine: $ qemu-system-ppc64 -S -machine ppce500,accel=tcg \ -device POWER5+_v2.1-spapr-cpu-core hw/ppc/spapr_cpu_core.c:178:spapr_cpu_core_realize_child: Object 0x55cee1f55160 is not an instance of type spapr-machine Aborted (core dumped) So let's add a proper check for the correct machine time with a more friendly error message here. Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Export ECB and PLB emulationBALATON Zoltan2-2/+5
Make these device models available outside ppc405_uc.c for reuse in 460EX emulation. They are left in their current place for now because they are used mostly unchanged and I'm not sure these correctly model the components in 440 SoCs (but they seem to be good enough). These functions could be moved in a subsequent clean up series when this is confirmed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx_i2c: Move to hw/i2cBALATON Zoltan6-1/+5
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx_i2c: QOMifyBALATON Zoltan4-109/+113
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own fileBALATON Zoltan4-242/+275
This device appears in other SoCs as well not just in 405 ones and subsequent patches will modify it, so move it out of ppc405_uc.c in preparation Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Make MAL emulation more genericBALATON Zoltan3-106/+70
Allow MAL with more RX and TX channels as found in newer versions. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Move MAL from ppc405_uc to ppc4xx_devsBALATON Zoltan3-263/+266
This device appears in other SoCs as well not just in 405 ones Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: Realloc guest visible TCE table when hot(un)plugging vfio-pciAlexey Kardashevskiy1-21/+14
This replaces g_malloc() with spapr_tce_alloc_table() as this is the standard way of allocating tables and this allows moving the table back to KVM when unplugging a VFIO PCI device and VFIO TCE acceleration support is not present in the KVM. Although spapr_tce_alloc_table() is expected to fail with EBUSY if called when previous fd is not closed yet, in practice we will not see it because cap_spapr_vfio is false at the moment. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc64: introduce e6500KONRAD Frederic3-1/+93
This introduces e6500 core. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08booke206: allow to specify an mmucfg value at the initKONRAD Frederic1-4/+5
This allows to init the MMUCFG SPR with a non NULL value. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08booke206: fix tlbnps for fixed size TLBKONRAD Frederic2-6/+32
Some OS don't populate the TSIZE field when using a fixed size TLB which result in a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be ignored. Fix this wrong behavior with MAV 2.0. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08booke206: fix booke206_tlbnps for mav 2.0KONRAD Frederic1-2/+2
This fixes booke206_tlbnps for MAV 2.0 by checking the MMUCFG register and return directly the right tlbnps instead of computing it from non existing field. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Make VCPU ID handling private to SPAPRSam Bobroff7-51/+41
The concept of a VCPU ID that differs from the CPU's index (cpu->cpu_index) exists only within SPAPR machines so, move the functions ppc_get_vcpu_id() and ppc_get_cpu_by_vcpu_id() into spapr.c and rename them appropriately. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Rename cpu_dt_id to vcpu_idSam Bobroff7-29/+29
This field actually records the VCPU ID used by KVM and, although the value is also used in the device tree it is primarily the VCPU ID so rename it as such. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> [dwg: Updated comment missed in cpu.h] Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08e500: Use cpu_index instead of vcpu_dt_idSam Bobroff1-6/+2
The e500 platform code uses the function ppc_get_vcpu_dt_id() to get an id to put in its device tree. Which seems like it makes sense, but ppc_get_vcpu_dt_id() is actually badly named - it only differs from cpu_index in cases where you're running on KVM HV and the host's number of threads differs from the guests. Since KVM HV only supports PAPR, not e500, it doesn't make sense to use it here. Simply use the cpu_index instead (which is 'i' in this context because qemu_get_cpu(i) returns the cpu with cpu_index == i). Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> [dwg: Rewrote commit message] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr: add pseries-2.11 machine typeGreg Kurz1-2/+20
Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: unregister vmstate at unrealize timeGreg Kurz1-0/+2
Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: pass object ownership to parent/ownerMichael Roth1-0/+1
TCE table objects attach themselves to an owner as a child property. unref afterward to allow them to be finalized when their owner is finalized. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_drc: pass object ownership to parent/ownerMichael Roth1-0/+1
DRC objects attach themselves to an owner as a child property. unref afterward to allow them to be finalized when their owner is finalized. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_drc: add unrealize method to physical DRC classGreg Kurz1-0/+16
When hot-unplugging a PHB, all its PCI DRC connectors get unrealized. This patch adds an unrealize method to the physical DRC class, in order to undo registrations performed in realize_physical(). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_pci: parent the MSI memory region to the PHBGreg Kurz1-1/+1
This memory region should be owned by the PHB. This ensures the PHB cannot be finalized as long as the the region is guest visible, or used by a CPU or a device. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: convert TCE table object to realize()Greg Kurz1-4/+2
Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_drc: use g_strdup_printf() instead of snprintf()Greg Kurz1-6/+9
Passing a stack allocated buffer of arbitrary length to snprintf() without checking the return value can cause the resultant strings to be silently truncated. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: use g_strdup_printf() instead of snprintf()Greg Kurz1-5/+8
Passing a stack allocated buffer of arbitrary length to snprintf() without checking the return value can cause the resultant strings to be silently truncated. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_pci: use memory_region_add_subregion() with DMA windowsGreg Kurz1-2/+2
Passing a null priority to memory_region_add_subregion_overlap() is strictly equivalent to calling memory_region_add_subregion(). Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08hw/ppc: CAS reset on early device hotplugDaniel Henrique Barboza3-2/+27
This patch is a follow up on the discussions made in patch "hw/ppc: disable hotplug before CAS is completed" that can be found at [1]. At this moment, we do not support CPU/memory hotplug in early boot stages, before CAS. When a hotplug occurs, the event is logged in an internal RTAS event log queue and an IRQ pulse is fired. In regular conditions, the guest handles the interrupt by executing check_exception, fetching the generated hotplug event and enabling the device for use. In early boot, this IRQ isn't caught (SLOF does not handle hotplug events), leaving the event in the rtas event log queue. If the guest executes check_exception due to another hotplug event, the re-assertion of the IRQ ends up de-queuing the first hotplug event as well. In short, a device hotplugged before CAS is considered coldplugged by SLOF. This leads to device misbehavior and, in some cases, guest kernel Ooops when trying to unplug the device. A proper fix would be to turn every device hotplugged before CAS as a colplugged device. This is not trivial to do with the current code base though - the FDT is written in the guest memory at ppc_spapr_reset and can't be retrieved without adding extra state (fdt_size for example) that will need to managed and migrated. Adding the hotplugged DT in the middle of CAS negotiation via the updated DT tree works with CPU devs, but panics the guest kernel at boot. Additional analysis would be necessary for LMBs and PCI devices. There are questions to be made in QEMU/SLOF/kernel level about how we can make this change in a sustainable way. With Linux guests, a fix would be the kernel executing check_exception at boot time, de-queueing the events that happened in early boot and processing them. However, even if/when the newer kernels start fetching these events at boot time, we need to take care of older kernels that won't be doing that. This patch works around the situation by issuing a CAS reset if a hotplugged device is detected during CAS: - the DRC conditions that warrant a CAS reset is the same as those that triggers a DRC migration - the DRC must have a device attached and the DRC state is not equal to its ready_state. With that in mind, this patch makes use of 'spapr_drc_needed' to determine if a CAS reset is needed. - In the middle of CAS negotiations, the function 'spapr_hotplugged_dev_before_cas' goes through all the DRCs to see if there are any DRC that requires a reset, using spapr_drc_needed. If that happens, returns '1' in 'spapr_h_cas_compose_response' which will set spapr->cas_reboot to true, causing the machine to reboot. No changes are made for coldplug devices. [1] http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg02855.html Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08hw/ppc: clear pending_events on machine resetDaniel Henrique Barboza3-0/+13
The sPAPR machine isn't clearing up the pending events QTAILQ on machine reboot. This allows for unprocessed hotplug/epow events to persist in the queue after reset and, when reasserting the IRQs in check_exception later on, these will be being processed by the OS. This patch implements a new function called 'spapr_clear_pending_events' that clears up the pending_events QTAILQ. This helper is then called inside ppc_spapr_reset to clear up the events queue, preventing old/deprecated events from persisting after a reset. Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->devDaniel Henrique Barboza1-2/+1
This patch makes a small fix in 'spapr_drc_needed' to change how we detect if a DRC has a device attached. Previously it used dr_entity_sense for this, which works for physical DRCs. However, for logical DRCs, it didn't cover the case where a logical DRC has a drc->dev but the state is LOGICAL_UNUSABLE (e.g. a hotplugged CPU before CAS). In this case, the dr_entity_sense of this DRC returns UNUSABLE and the code was considering that there were no dev attached, making spapr_drc_needed return 'false' when in fact we would like to migrate the DRC. Changing it to check for drc->dev instead works for all DRC types. Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-07tcg/tci: Add TCG_TARGET_DEFAULT_MORichard Henderson1-0/+5
Missed being added as part of 71650df7b0ee. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-09-06' into ↵Peter Maydell10-111/+141
staging nbd patches for 2017-09-06 - Daniel P. Berrange: [0/2] Fix / skip recent iotests with LUKS driver - Eric Blake: [0/3] nbd: Use common read/write-all qio functions # gpg: Signature made Wed 06 Sep 2017 16:17:55 BST # gpg: using RSA key 0xA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2017-09-06: nbd: Use new qio_channel_*_all() functions io: Add new qio_channel_read{, v}_all_eof functions io: Yield rather than wait when already in coroutine iotests: blacklist 194 with the luks driver iotests: rewrite 192 to use _launch_qemu to fix LUKS support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch ↵Peter Maydell48-213/+978
'remotes/pmaydell/tags/pull-target-arm-20170907' into staging target-arm: * cleanups converting to DEFINE_PROP_LINK * allwinner-a10: mark as not user-creatable * initial patches working towards ARMv8M support * implement generating aborts on memory transaction failures * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later # gpg: Signature made Thu 07 Sep 2017 14:26:07 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits) target/arm: Add Jazelle feature target/arm: Implement new do_transaction_failed hook hw/arm: Set ignore_memory_transaction_failures for most ARM boards boards.h: Define new flag ignore_memory_transaction_failures target/arm: Implement BXNS, and banked stack pointers target/arm: Move regime_is_secure() to target/arm/internals.h target/arm: Make CFSR register banked for v8M target/arm: Make MMFAR banked for v8M target/arm: Make CCR register banked for v8M target/arm: Make MPU_CTRL register banked for v8M target/arm: Make MPU_RNR register banked for v8M target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M target/arm: Make VTOR register banked for v8M nvic: Add NS alias SCS region target/arm: Make CONTROL register banked for v8M target/arm: Make FAULTMASK register banked for v8M target/arm: Make PRIMASK register banked for v8M target/arm: Make BASEPRI register banked for v8M target/arm: Add MMU indexes for secure v8M ... # Conflicts: # target/arm/translate.c
2017-09-07Merge remote-tracking branch ↵Peter Maydell9-85/+35
'remotes/dgilbert/tags/pull-migration-20170906a' into staging migration pull 2017-09-06 # gpg: Signature made Wed 06 Sep 2017 19:39:23 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20170906a: migration: dump str in migrate_set_state trace snapshot/tests: Try loadvm twice migration: Reset rather than destroy main_thread_load_event runstate/migrate: Two more transitions host-utils: Simplify pow2ceil() host-utils: Proactively fix pow2floor(), switch to unsigned xbzrle: Drop unused cache_resize() migration: Report when bdrv_inactivate_all fails Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07Merge remote-tracking branch 'remotes/rth/tags/pull-tgt-20170906' into stagingPeter Maydell17-570/+909
tcg generic translate loop v15 # gpg: Signature made Wed 06 Sep 2017 17:02:31 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tgt-20170906: (32 commits) target/arm: Perform per-insn cross-page check only for Thumb target/arm: Split out thumb_tr_translate_insn target/arm: Move ss check to init_disas_context target/arm: [a64] Move page and ss checks to init_disas_context target/arm: [tcg] Port to generic translation framework target/arm: [tcg,a64] Port to disas_log target/arm: [tcg] Port to disas_log target/arm: [tcg,a64] Port to tb_stop target/arm: [tcg] Port to tb_stop target/arm: [tcg,a64] Port to translate_insn target/arm: [tcg] Port to translate_insn target/arm: [tcg,a64] Port to breakpoint_check target/arm: [tcg,a64] Port to insn_start target/arm: [tcg] Port to insn_start target/arm: [tcg] Port to tb_start target/arm: [tcg,a64] Port to init_disas_context target/arm: [tcg] Port to init_disas_context target/arm: [tcg] Port to DisasContextBase target/i386: [tcg] Port to generic translation framework target/i386: [tcg] Port to disas_log ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07target/arm: Add Jazelle featurePortia Stephens3-1/+5
This adds a feature bit indicating support of the (trivial) Jazelle implementation if ARM_FEATURE_V6 is set or if the processor is arm926 or arm1026. This fixes the issue that any BXJ instruction will result in an illegal_op. BXJ instructions will now check if the architecture supports ARM_FEATURE_JAZELLE. Signed-off-by: Portia Stephens <portia.stephens@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com [PMM: edited commit message and comment text a bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07target/arm: Implement new do_transaction_failed hookPeter Maydell3-0/+54
Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1504626814-23124-4-git-send-email-peter.maydell@linaro.org
2017-09-07hw/arm: Set ignore_memory_transaction_failures for most ARM boardsPeter Maydell27-0/+43
Set the MachineClass flag ignore_memory_transaction_failures for almost all ARM boards. This means they retain the legacy behaviour that accesses to unimplemented addresses will RAZ/WI rather than aborting, when a subsequent commit adds support for external aborts. The exceptions are: * virt -- we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables * mps2 -- this board was written to use unimplemented-device for all the ranges with devices we don't yet handle New boards should not set the flag, but instead be written like the mps2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org For the Xilinx boards: Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-09-07boards.h: Define new flag ignore_memory_transaction_failuresPeter Maydell3-1/+33
Define a new MachineClass field ignore_memory_transaction_failures. If this is flag is true then the CPU will ignore memory transaction failures which should cause the CPU to take an exception due to an access to an unassigned physical address; the transaction will instead return zero (for a read) or be ignored (for a write). This should be set only by legacy board models which rely on the old RAZ/WI behaviour for handling devices that QEMU does not yet model. New board models should instead use "unimplemented-device" for all memory ranges where the guest will attempt to probe for a device that QEMU doesn't implement and a stub device is required. We need this for ARM boards, where we're about to implement support for generating external aborts on memory transaction failures. Too many of our legacy board models rely on the RAZ/WI behaviour and we would break currently working guests when their "probe for device" code provoked an external abort rather than a RAZ. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1504626814-23124-2-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell6-1/+138
Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear. This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state. BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Move regime_is_secure() to target/arm/internals.hPeter Maydell2-26/+26
Move the regime_is_secure() utility function to internals.h; we are going to want to call it from translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell4-13/+30
Make the CFSR register banked if v8M security extensions are enabled. Not all the bits in this register are banked: the BFSR bits [15:8] are shared between S and NS, and we store them in the NS copy of the register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell4-6/+7
Make the MMFAR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell5-13/+42
Make the CCR register banked if v8M security extensions are enabled. This is slightly more complicated than the other "add banking" patches because there is one bit in the register which is not banked. We keep the live data in the NS copy of the register, and adjust it on register reads and writes. (Since we don't currently implement the behaviour that the bit controls, there is nowhere else that needs to care.) This patch includes the enforcement of the bits which are newly RES1 in ARMv8M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell4-8/+11
Make the MPU_CTRL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell5-16/+26
Make the MPU_RNR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell5-21/+40
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8MPeter Maydell4-10/+14
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org
2017-09-07target/arm: Make VTOR register banked for v8MPeter Maydell4-9/+11
Make the VTOR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org
generated by cgit v1.1 at 2024-12-28 17:49:21 +0000